diff --git a/librz/arch/il/analysis_il.c b/librz/arch/il/analysis_il.c index 007924c8021..dc6d5495584 100644 --- a/librz/arch/il/analysis_il.c +++ b/librz/arch/il/analysis_il.c @@ -257,7 +257,6 @@ static RzAnalysisILStepResult analysis_il_vm_step_while( ut64 addr = rz_bv_to_ut64(vm->vm->pc); ut8 code[32] = { 0 }; analysis->read_at(analysis, addr, code, sizeof(code)); - rz_analysis_op_init(&op); int r = rz_analysis_op(analysis, &op, addr, code, sizeof(code), RZ_ANALYSIS_OP_MASK_IL | RZ_ANALYSIS_OP_MASK_HINT | RZ_ANALYSIS_OP_MASK_DISASM); if (r < 0 || !op.il_op) { @@ -275,7 +274,7 @@ static RzAnalysisILStepResult analysis_il_vm_step_while( RzStrBuf sb = { 0 }; rz_strbuf_init(&sb); - rz_il_op_effect_stringify(op.il_op, &sb, true); + rz_il_op_effect_stringify(op.il_op, &sb, false); rz_strbuf_append(&sb, "\n"); il_events(vm->vm, &sb); @@ -284,6 +283,7 @@ static RzAnalysisILStepResult analysis_il_vm_step_while( rz_cons_printf("%x", code[i]); } rz_cons_printf("] %s\n%s\n", op.mnemonic, rz_strbuf_get(&sb)); + rz_cons_flush(); rz_strbuf_fini(&sb); rz_analysis_op_fini(&op); } diff --git a/librz/arch/isa/pic/pic.h b/librz/arch/isa/pic/pic.h new file mode 100644 index 00000000000..e583c899bdb --- /dev/null +++ b/librz/arch/isa/pic/pic.h @@ -0,0 +1,18 @@ +// SPDX-FileCopyrightText: 2024 billow +// SPDX-License-Identifier: LGPL-3.0-only// + +#ifndef RIZIN_PIC_H +#define RIZIN_PIC_H + +#include + +typedef struct { + RzIODesc *mem_sram; + RzIODesc *mem_stack; + bool init_done; + HtSU *pic18_mm; +} PicContext; + +#define SEXT(B, x, b) ((st##B)(x << (B - b)) >> (B - b)) + +#endif // RIZIN_PIC_H diff --git a/librz/arch/isa/pic/pic14.c b/librz/arch/isa/pic/pic14.c new file mode 100644 index 00000000000..071a68f47ec --- /dev/null +++ b/librz/arch/isa/pic/pic14.c @@ -0,0 +1,261 @@ +// SPDX-FileCopyrightText: 2018 thestr4ng3r +// SPDX-License-Identifier: LGPL-3.0-only + +#include "pic14.h" + +static const Pic14OpInfo pic14_op_info[PIC14_OPCODE_INVALID] = { + { "nop", PIC14_OP_ARGS_NONE }, + { "option", PIC14_OP_ARGS_NONE }, + { "sleep", PIC14_OP_ARGS_NONE }, + { "clrwdt", PIC14_OP_ARGS_NONE }, + { "tris", PIC14_OP_ARGS_3F }, + { "movlb", PIC14_OP_ARGS_3K }, + { "return", PIC14_OP_ARGS_NONE }, + { "retfie", PIC14_OP_ARGS_NONE }, + { "movwf", PIC14_OP_ARGS_5F }, + { "clrf", PIC14_OP_ARGS_5F }, + { "clrw", PIC14_OP_ARGS_NONE }, + { "subwf", PIC14_OP_ARGS_1D_5F }, + { "decf", PIC14_OP_ARGS_1D_5F }, + { "iorwf", PIC14_OP_ARGS_1D_5F }, + { "andwf", PIC14_OP_ARGS_1D_5F }, + { "xorwf", PIC14_OP_ARGS_1D_5F }, + { "andwf", PIC14_OP_ARGS_1D_5F }, + { "movf", PIC14_OP_ARGS_1D_5F }, + { "comf", PIC14_OP_ARGS_1D_5F }, + { "incf", PIC14_OP_ARGS_1D_5F }, + { "decfsz", PIC14_OP_ARGS_1D_5F }, + { "rrf", PIC14_OP_ARGS_1D_5F }, + { "rlf", PIC14_OP_ARGS_1D_5F }, + { "swapf", PIC14_OP_ARGS_1D_5F }, + { "incfsz", PIC14_OP_ARGS_1D_5F }, + { "bcf", PIC14_OP_ARGS_3B_5F }, + { "bsf", PIC14_OP_ARGS_3B_5F }, + { "btfsc", PIC14_OP_ARGS_3B_5F }, + { "btfss", PIC14_OP_ARGS_3B_5F }, + { "retlw", PIC14_OP_ARGS_8K }, + { "call", PIC14_OP_ARGS_8K }, + { "goto", PIC14_OP_ARGS_9K }, + { "movlw", PIC14_OP_ARGS_8K }, + { "iorlw", PIC14_OP_ARGS_8K }, + { "andlw", PIC14_OP_ARGS_8K }, + { "xorlw", PIC14_OP_ARGS_8K } +}; + +Pic14Opcode pic14_get_opcode(ut16 instr) { + if (instr & 0xf000) { + return PIC14_OPCODE_INVALID; + } + + switch ((instr >> 6) & 0x3f) { // first 6 bits + case 0x7: // 0b000111 + return PIC14_OPCODE_ADDWF; + case 0x5: // 0b000101 + return PIC14_OPCODE_ANDWF; + case 0x1: // 0b000001 + if (instr & (1 << 5)) { + return PIC14_OPCODE_CLRF; + } + if ((instr & 0x1f) == 0) { // last 5 bits + return PIC14_OPCODE_CLRW; + } + return PIC14_OPCODE_INVALID; + case 0x9: // 0b001001 + return PIC14_OPCODE_COMF; + case 0x3: // 0b000011 + return PIC14_OPCODE_DECF; + case 0xb: // 0b001011 + return PIC14_OPCODE_DECFSZ; + case 0xa: // 0b001010 + return PIC14_OPCODE_INCF; + case 0xf: // 0b001111 + return PIC14_OPCODE_INCFSZ; + case 0x4: // 0b000100 + return PIC14_OPCODE_IORWF; + case 0x8: // 0b001000 + return PIC14_OPCODE_MOVF; + case 0x0: + if (instr & (1 << 5)) { + return PIC14_OPCODE_MOVWF; + } else { + switch (instr & 0x1f) { // last 5 bits + case 0x0: // 0b00000 + return PIC14_OPCODE_NOP; + case 0x4: // 0b00100 + return PIC14_OPCODE_CLRWDT; + case 0x2: // 0b00010 + return PIC14_OPCODE_OPTION; + case 0x3: // 0b00011 + return PIC14_OPCODE_SLEEP; + case 0x1: // 0b00001 + case 0x5: // 0b00101 + case 0x6: // 0b00110 + case 0x7: // 0b00111 + return PIC14_OPCODE_TRIS; + case 0x10: // 0b10000 + case 0x11: // 0b10001 + case 0x12: // 0b10010 + case 0x13: // 0b10011 + case 0x14: // 0b10100 + case 0x15: // 0b10101 + case 0x16: // 0b10110 + case 0x17: // 0b10111 + return PIC14_OPCODE_MOVLB; + case 0x1e: // 0b11110 + return PIC14_OPCODE_RETURN; + case 0x1f: // 0b11111 + return PIC14_OPCODE_RETFIE; + default: + return PIC14_OPCODE_INVALID; + } + } + case 0xd: // 0b001101 + return PIC14_OPCODE_RLF; + case 0xc: // 0b001100 + return PIC14_OPCODE_RRF; + case 0x2: // 0b000010 + return PIC14_OPCODE_SUBWF; + case 0xe: // 0b001110 + return PIC14_OPCODE_SWAPF; + case 0x6: // 0b000110 + return PIC14_OPCODE_XORWF; + case 0x10: // 0b010000 + case 0x11: // 0b010001 + case 0x12: // 0b010010 + case 0x13: // 0b010011 + return PIC14_OPCODE_BCF; + case 0x14: // 0b010100 + case 0x15: // 0b010101 + case 0x16: // 0b010110 + case 0x17: // 0b010111 + return PIC14_OPCODE_BSF; + case 0x18: // 0b011000 + case 0x19: // 0b011001 + case 0x1a: // 0b011010 + case 0x1b: // 0b011011 + return PIC14_OPCODE_BTFSC; + case 0x1c: // 0b011100 + case 0x1d: // 0b011101 + case 0x1e: // 0b011110 + case 0x1f: // 0b011111 + return PIC14_OPCODE_BTFSS; + case 0x38: // 0b111000 + case 0x39: // 0b111001 + case 0x3a: // 0b111010 + case 0x3b: // 0b111011 + return PIC14_OPCODE_ANDLW; + case 0x24: // 0b100100 + case 0x25: // 0b100101 + case 0x26: // 0b100110 + case 0x27: // 0b100111 + return PIC14_OPCODE_CALL; + case 0x28: // 0b101000 + case 0x29: // 0b101001 + case 0x2a: // 0b101010 + case 0x2b: // 0b101011 + case 0x2c: // 0b101100 + case 0x2d: // 0b101101 + case 0x2e: // 0b101110 + case 0x2f: // 0b101111 + return PIC14_OPCODE_GOTO; + case 0x34: // 0b110100 + case 0x35: // 0b110101 + case 0x36: // 0b110110 + case 0x37: // 0b110111 + return PIC14_OPCODE_IORLW; + case 0x30: // 0b110000 + case 0x31: // 0b110001 + case 0x32: // 0b110010 + case 0x33: // 0b110011 + return PIC14_OPCODE_MOVLW; + case 0x20: // 0b100000 + case 0x21: // 0b100001 + case 0x22: // 0b100010 + case 0x23: // 0b100011 + return PIC14_OPCODE_RETLW; + case 0x3c: // 0b111100 + case 0x3d: // 0b111101 + case 0x3e: // 0b111110 + case 0x3f: // 0b111111 + return PIC14_OPCODE_XORLW; + default: + return PIC14_OPCODE_INVALID; + } +} + +Pic14OpArgs pic14_get_opargs(Pic14Opcode opcode) { + if (opcode >= PIC14_OPCODE_INVALID) { + return -1; + } + return pic14_op_info[opcode].args; +} + +const Pic14OpInfo *pic14_get_op_info(Pic14Opcode opcode) { + if (opcode >= PIC14_OPCODE_INVALID) { + return NULL; + } + return &pic14_op_info[opcode]; +} + +int pic14_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { +#define EMIT_INVALID \ + { \ + op->size = 1; \ + rz_asm_op_set_asm(op, "invalid"); \ + return 1; \ + } + if (!b || l < 2) { + EMIT_INVALID + } + + ut16 instr = rz_read_le16(b); + Pic14Opcode opcode = pic14_get_opcode(instr); + if (opcode == PIC14_OPCODE_INVALID) { + EMIT_INVALID + } + + const Pic14OpInfo *op_info = pic14_get_op_info(opcode); + if (!op_info) { + EMIT_INVALID + } + +#undef EMIT_INVALID + + op->size = 2; + switch (op_info->args) { + case PIC14_OP_ARGS_NONE: + rz_asm_op_set_asm(op, op_info->mnemonic); + break; + case PIC14_OP_ARGS_2F: + rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_2F_MASK_F); + break; + case PIC14_OP_ARGS_3F: + rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_3F_MASK_F); + break; + case PIC14_OP_ARGS_3K: + rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_3K_MASK_K); + break; + case PIC14_OP_ARGS_1D_5F: + rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic, instr & PIC14_OP_ARGS_1D_5F_MASK_F, + (instr & PIC14_OP_ARGS_1D_5F_MASK_D) >> 5 ? 'f' : 'w'); + break; + case PIC14_OP_ARGS_5F: + rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_5F_MASK_F); + break; + case PIC14_OP_ARGS_3B_5F: + rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_3B_5F_MASK_F, + (instr & PIC14_OP_ARGS_3B_5F_MASK_B) >> 5); + break; + case PIC14_OP_ARGS_8K: + rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_8K_MASK_K); + break; + case PIC14_OP_ARGS_9K: + rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC14_OP_ARGS_9K_MASK_K); + break; + default: + rz_asm_op_set_asm(op, "invalid"); + break; + } + + return op->size; +} diff --git a/librz/arch/isa/pic/pic14.h b/librz/arch/isa/pic/pic14.h new file mode 100644 index 00000000000..62fb9a249fb --- /dev/null +++ b/librz/arch/isa/pic/pic14.h @@ -0,0 +1,88 @@ +// SPDX-FileCopyrightText: 2018 thestr4ng3r +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef PIC14_H +#define PIC14_H + +#include +#include + +static inline bool is_pic14(const char *x) { + return RZ_STR_EQ(x, "baseline") || + RZ_STR_EQ(x, "pic14"); +} + +typedef enum { + PIC14_OP_ARGS_NONE = 0, + PIC14_OP_ARGS_2F, + PIC14_OP_ARGS_3F, + PIC14_OP_ARGS_3K, + PIC14_OP_ARGS_1D_5F, + PIC14_OP_ARGS_5F, + PIC14_OP_ARGS_3B_5F, + PIC14_OP_ARGS_8K, + PIC14_OP_ARGS_9K +} Pic14OpArgs; + +#define PIC14_OP_ARGS_2F_MASK_F 0x3 +#define PIC14_OP_ARGS_3F_MASK_F 0x7 +#define PIC14_OP_ARGS_3K_MASK_K 0x7 +#define PIC14_OP_ARGS_1D_5F_MASK_D (1 << 5) +#define PIC14_OP_ARGS_1D_5F_MASK_F 0x1f +#define PIC14_OP_ARGS_5F_MASK_F 0x1f +#define PIC14_OP_ARGS_3B_5F_MASK_B (0x7 << 5) +#define PIC14_OP_ARGS_3B_5F_MASK_F 0x1f +#define PIC14_OP_ARGS_8K_MASK_K 0xff +#define PIC14_OP_ARGS_9K_MASK_K 0x1ff + +typedef struct _pic14_op { + const char *mnemonic; + Pic14OpArgs args; +} Pic14OpInfo; + +typedef enum { + PIC14_OPCODE_NOP = 0, + PIC14_OPCODE_OPTION, + PIC14_OPCODE_SLEEP, + PIC14_OPCODE_CLRWDT, + PIC14_OPCODE_TRIS, + PIC14_OPCODE_MOVLB, + PIC14_OPCODE_RETURN, + PIC14_OPCODE_RETFIE, + PIC14_OPCODE_MOVWF, + PIC14_OPCODE_CLRF, + PIC14_OPCODE_CLRW, + PIC14_OPCODE_SUBWF, + PIC14_OPCODE_DECF, + PIC14_OPCODE_IORWF, + PIC14_OPCODE_ANDWF, + PIC14_OPCODE_XORWF, + PIC14_OPCODE_ADDWF, + PIC14_OPCODE_MOVF, + PIC14_OPCODE_COMF, + PIC14_OPCODE_INCF, + PIC14_OPCODE_DECFSZ, + PIC14_OPCODE_RRF, + PIC14_OPCODE_RLF, + PIC14_OPCODE_SWAPF, + PIC14_OPCODE_INCFSZ, + PIC14_OPCODE_BCF, + PIC14_OPCODE_BSF, + PIC14_OPCODE_BTFSC, + PIC14_OPCODE_BTFSS, + PIC14_OPCODE_RETLW, + PIC14_OPCODE_CALL, + PIC14_OPCODE_GOTO, + PIC14_OPCODE_MOVLW, + PIC14_OPCODE_IORLW, + PIC14_OPCODE_ANDLW, + PIC14_OPCODE_XORLW, + PIC14_OPCODE_INVALID +} Pic14Opcode; + +Pic14Opcode pic14_get_opcode(ut16 instr); +Pic14OpArgs pic14_get_opargs(Pic14Opcode opcode); +const Pic14OpInfo *pic14_get_op_info(Pic14Opcode opcode); +int pic14_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l); + +#endif // PIC14_H diff --git a/librz/arch/isa/pic/pic16.c b/librz/arch/isa/pic/pic16.c new file mode 100644 index 00000000000..eadddad8901 --- /dev/null +++ b/librz/arch/isa/pic/pic16.c @@ -0,0 +1,365 @@ +// SPDX-FileCopyrightText: 2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#include "pic.h" +#include "pic16.h" + +static const char *pic16_regname(ut32 reg) { + const char *Pic16Bank0[] = { + "indf0", + "indf1", + "pcl", + "status", + "fsr0l", + "fsr0h", + "fsr1l", + "fsr1h", + "bsr", + "wreg", + "pclath", + "intcon", + "porta", + "portb", + "portc", + "portd", + "porte", + "pir1", + "pir2", + "pir3", + "---", + "tmr0", + "tmr1l", + "tmr1h", + "t1con", + "t1con", + "tmr2", + "pr2", + "t2con", + "---", + "cpscon0", + "cpscon1", + }; + + if (reg >= RZ_ARRAY_SIZE(Pic16Bank0)) { + return NULL; + } + return Pic16Bank0[reg]; +} + +static const Pic16OpAsmInfo pic16_op_info[PIC16_OPCODE_INVALID] = { + { "nop", PIC16_OP_ARGS_NONE }, + { "return", PIC16_OP_ARGS_NONE }, + { "retfie", PIC16_OP_ARGS_NONE }, + { "option", PIC16_OP_ARGS_NONE }, + { "sleep", PIC16_OP_ARGS_NONE }, + { "clrwdt", PIC16_OP_ARGS_NONE }, + { "clrf", PIC16_OP_ARGS_7F }, + { "clrw", PIC16_OP_ARGS_NONE }, + { "tris", PIC16_OP_ARGS_2F }, + { "movwf", PIC16_OP_ARGS_7F }, + { "subwf", PIC16_OP_ARGS_1D_7F }, + { "decf", PIC16_OP_ARGS_1D_7F }, + { "iorwf", PIC16_OP_ARGS_1D_7F }, + { "andwf", PIC16_OP_ARGS_1D_7F }, + { "xorwf", PIC16_OP_ARGS_1D_7F }, + { "addwf", PIC16_OP_ARGS_1D_7F }, + { "movf", PIC16_OP_ARGS_1D_7F }, + { "comf", PIC16_OP_ARGS_1D_7F }, + { "incf", PIC16_OP_ARGS_1D_7F }, + { "decfsz", PIC16_OP_ARGS_1D_7F }, + { "rrf", PIC16_OP_ARGS_1D_7F }, + { "rlf", PIC16_OP_ARGS_1D_7F }, + { "swapf", PIC16_OP_ARGS_1D_7F }, + { "incfsz", PIC16_OP_ARGS_1D_7F }, + { "bcf", PIC16_OP_ARGS_3B_7F }, + { "bsf", PIC16_OP_ARGS_3B_7F }, + { "btfsc", PIC16_OP_ARGS_3B_7F }, + { "btfss", PIC16_OP_ARGS_3B_7F }, + { "call", PIC16_OP_ARGS_11K }, + { "goto", PIC16_OP_ARGS_11K }, + { "movlw", PIC16_OP_ARGS_8K }, + { "retlw", PIC16_OP_ARGS_8K }, + { "iorlw", PIC16_OP_ARGS_8K }, + { "andlw", PIC16_OP_ARGS_8K }, + { "xorlw", PIC16_OP_ARGS_8K }, + { "sublw", PIC16_OP_ARGS_8K }, + { "addlw", PIC16_OP_ARGS_8K }, + { "reset", PIC16_OP_ARGS_NONE }, + { "callw", PIC16_OP_ARGS_NONE }, + { "brw", PIC16_OP_ARGS_NONE }, + { "moviw", PIC16_OP_ARGS_1N_2M }, + { "movwi", PIC16_OP_ARGS_1N_2M }, + { "movlb", PIC16_OP_ARGS_4K }, + { "lslf", PIC16_OP_ARGS_1D_7F }, + { "lsrf", PIC16_OP_ARGS_1D_7F }, + { "asrf", PIC16_OP_ARGS_1D_7F }, + { "subwfb", PIC16_OP_ARGS_1D_7F }, + { "addwfc", PIC16_OP_ARGS_1D_7F }, + { "addfsr", PIC16_OP_ARGS_1N_6K }, + { "movlp", PIC16_OP_ARGS_7F }, + { "bra", PIC16_OP_ARGS_9K }, + { "moviw", PIC16_OP_ARGS_1N_6K }, + { "movwi", PIC16_OP_ARGS_1N_6K } +}; + +static const char *Pic16FsrOps[] = { "++FSR%d", "--FSR%d", "FSR%d++", + "FSR%d--" }; + +/** + * \brief Decode a Pic 16 instruction to it's corresponding opcode enum. + * */ +Pic16Opcode pic16_get_opcode(ut16 instr) { + switch (instr >> 11) { // 3 first MSB bits + case 0x4: return PIC16_OPCODE_CALL; + case 0x5: return PIC16_OPCODE_GOTO; + } + + switch (instr >> 10) { // 4 first MSB bits + case 0x4: return PIC16_OPCODE_BCF; + case 0x5: return PIC16_OPCODE_BSF; + case 0x6: return PIC16_OPCODE_BTFSC; + case 0x7: return PIC16_OPCODE_BTFSS; + case 0xd: return PIC16_OPCODE_RETLW; + } + + switch (instr >> 9) { // 5 first MSB bits + case 0x19: return PIC16_OPCODE_BRA; + } + + switch (instr >> 8) { // 6 first MSB bits + case 0x2: return PIC16_OPCODE_SUBWF; + case 0x3: return PIC16_OPCODE_DECF; + case 0x4: return PIC16_OPCODE_IORWF; + case 0x5: return PIC16_OPCODE_ANDWF; + case 0x6: return PIC16_OPCODE_XORWF; + case 0x7: return PIC16_OPCODE_ADDWF; + case 0x8: return PIC16_OPCODE_MOVF; + case 0x9: return PIC16_OPCODE_COMF; + case 0xa: return PIC16_OPCODE_INCF; + case 0xb: return PIC16_OPCODE_DECFSZ; + case 0xc: return PIC16_OPCODE_RRF; + case 0xd: return PIC16_OPCODE_RLF; + case 0xe: return PIC16_OPCODE_SWAPF; + case 0xf: return PIC16_OPCODE_INCFSZ; + case 0x38: return PIC16_OPCODE_IORLW; + case 0x39: return PIC16_OPCODE_ANDLW; + case 0x3a: return PIC16_OPCODE_XORLW; + case 0x30: return PIC16_OPCODE_MOVLW; + case 0x3c: return PIC16_OPCODE_SUBLW; + case 0x3e: return PIC16_OPCODE_ADDLW; + case 0x35: return PIC16_OPCODE_LSLF; + case 0x36: return PIC16_OPCODE_LSRF; + case 0x37: return PIC16_OPCODE_ASRF; + case 0x3b: return PIC16_OPCODE_SUBWFB; + case 0x3d: return PIC16_OPCODE_ADDWFC; + } + + switch (instr >> 7) { // 7 first MSB bits + case 0x1: return PIC16_OPCODE_MOVWF; + case 0x2: return PIC16_OPCODE_CLRW; + case 0x3: return PIC16_OPCODE_CLRF; + case 0x62: return PIC16_OPCODE_ADDFSR; + case 0x63: return PIC16_OPCODE_MOVLP; + case 0x7e: return PIC16_OPCODE_MOVIW_2; + case 0x7f: return PIC16_OPCODE_MOVWI_2; + } + + switch (instr >> 5) { // 9 first MSB bits + case 0x1: return PIC16_OPCODE_MOVLB; + } + + switch (instr >> 3) { // 11 first MSB bits + case 0x2: return PIC16_OPCODE_MOVIW_1; + case 0x3: return PIC16_OPCODE_MOVWI_1; + } + + switch (instr >> 2) { // 12 first MSB bits + case 0x19: return PIC16_OPCODE_TRIS; + } + + switch (instr) { + case 0x0: return PIC16_OPCODE_NOP; + case 0x1: return PIC16_OPCODE_RESET; + case 0xa: return PIC16_OPCODE_CALLW; + case 0xb: return PIC16_OPCODE_BRW; + case 0x8: return PIC16_OPCODE_RETURN; + case 0x9: return PIC16_OPCODE_RETFIE; + case 0x62: return PIC16_OPCODE_OPTION; + case 0x63: return PIC16_OPCODE_SLEEP; + case 0x64: return PIC16_OPCODE_CLRWDT; + } + + return PIC16_OPCODE_INVALID; +} + +static void analysis_pic16_extract_args( + ut16 instr, + Pic16OpArgs args, + Pic16OpArgsVal *args_val) { + + memset(args_val, 0, sizeof(Pic16OpArgsVal)); + + switch (args) { + case PIC16_OP_ARGS_NONE: return; + case PIC16_OP_ARGS_2F: + args_val->f = instr & PIC16_OP_ARGS_2F_MASK_F; + return; + case PIC16_OP_ARGS_7F: + args_val->f = instr & PIC16_OP_ARGS_7F_MASK_F; + return; + case PIC16_OP_ARGS_1D_7F: + args_val->f = instr & PIC16_OP_ARGS_1D_7F_MASK_F; + args_val->d = + (instr & PIC16_OP_ARGS_1D_7F_MASK_D) >> 7; + return; + case PIC16_OP_ARGS_1N_6K: { + args_val->n = (instr & PIC16_OP_ARGS_1N_6K_MASK_N) >> 6; + ut16 k = instr & PIC16_OP_ARGS_1N_6K_MASK_K; + args_val->k = SEXT(16, k, 6); + return; + } + case PIC16_OP_ARGS_3B_7F: + args_val->b = (instr & PIC16_OP_ARGS_3B_7F_MASK_B) >> 7; + args_val->f = instr & PIC16_OP_ARGS_3B_7F_MASK_F; + return; + case PIC16_OP_ARGS_4K: + args_val->k = instr & PIC16_OP_ARGS_4K_MASK_K; + return; + case PIC16_OP_ARGS_8K: + args_val->k = instr & PIC16_OP_ARGS_8K_MASK_K; + return; + case PIC16_OP_ARGS_9K: { + ut16 k = instr & PIC16_OP_ARGS_9K_MASK_K; + args_val->k = SEXT(16, k, 9); + return; + } + case PIC16_OP_ARGS_11K: + args_val->k = instr & PIC16_OP_ARGS_11K_MASK_K; + return; + case PIC16_OP_ARGS_1N_2M: + args_val->n = (instr & PIC16_OP_ARGS_1N_2M_MASK_N) >> 2; + args_val->m = instr & PIC16_OP_ARGS_1N_2M_MASK_M; + return; + } +} + +/** + * \brief Get opcode information (mnemonic and arguments) corresponding + * to a given \c Pic16Opcode. + * + * \param opcode + * \return \c Pic16OpInfo pointer. + * */ +const Pic16OpAsmInfo *pic16_get_op_info(Pic16Opcode opcode) { + if (opcode >= PIC16_OPCODE_INVALID) { + return NULL; + } + return &pic16_op_info[opcode]; +} + +#define F pic16_regname(op->args.f) +#define K (op->args.k) + +bool pic16_disasm_op(Pic16Op *op, ut64 addr, const ut8 *b, ut64 l) { + if (!b || l < 2) { + return false; + } + + op->instr = rz_read_le16(b) & 0x3fff; + Pic16Opcode opcode = pic16_get_opcode(op->instr); + if (opcode == PIC16_OPCODE_INVALID) { + return false; + } + const Pic16OpAsmInfo *op_info = pic16_get_op_info(opcode); + if (!op_info) { + return false; + } + + op->opcode = opcode; + op->size = 2; + op->addr = addr; + op->mnemonic = op_info->mnemonic; + op->args_tag = op_info->args; + analysis_pic16_extract_args(op->instr, op_info->args, &op->args); + + switch (op_info->args) { + case PIC16_OP_ARGS_NONE: + break; + case PIC16_OP_ARGS_2F: + case PIC16_OP_ARGS_7F: + if (F) { + rz_strf(op->operands, "%s", F); + } else { + rz_strf(op->operands, "0x%x", op->args.f); + } + break; + case PIC16_OP_ARGS_1D_7F: + if (F) { + rz_strf(op->operands, "%s, %d", F, op->args.d); + } else { + rz_strf(op->operands, "0x%x, %d", op->args.f, op->args.d); + } + break; + case PIC16_OP_ARGS_1N_6K: + if (opcode == PIC16_OPCODE_ADDFSR) { + rz_strf(op->operands, "FSR%d, %s%#x", op->args.n, K < 0 ? "-" : "", (unsigned)abs(K)); + } else { + rz_strf(op->operands, "%s%#x[FSR%d]", K < 0 ? "-" : "", (unsigned)abs(K), op->args.n); + } + break; + case PIC16_OP_ARGS_3B_7F: + if (F) { + rz_strf(op->operands, "%s, %d", F, op->args.b); + } else { + rz_strf(op->operands, "0x%x, %d", op->args.f, op->args.b); + } + break; + case PIC16_OP_ARGS_4K: + case PIC16_OP_ARGS_8K: + case PIC16_OP_ARGS_11K: + rz_strf(op->operands, "0x%x", op->args.k); + break; + case PIC16_OP_ARGS_9K: + rz_strf(op->operands, "%s%#x", K < 0 ? "-" : "", (unsigned)abs(K)); + break; + case PIC16_OP_ARGS_1N_2M: + rz_strf(op->operands, Pic16FsrOps[op->args.m], op->args.n); + break; + default: + break; + } + return true; +} + +/** + * \brief Disassemble a PIC 16 instruction. + * + * \param op RzAsmOp to tell number of instructions decoded. + * \param opbuf Decoded instruction mnemonic will be stored in this before return. + * \param b Opcode buffer containing Pic16 opcodes. + * \param l Length of opcode buffer \p b. + * + * \return Number of decoded bytes (2 on success, 1 on failure). + * */ +int pic16_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { +#define EMIT_INVALID \ + { \ + op->size = 2; \ + rz_asm_op_set_asm(op, "invalid"); \ + return 1; \ + } + + Pic16Op x = { 0 }; + if (!pic16_disasm_op(&x, a->pc, b, l)) { + EMIT_INVALID; + } + + op->size = x.size; + if (x.operands[0]) { + rz_asm_op_setf_asm(op, "%s %s", x.mnemonic, x.operands); + } else { + rz_asm_op_setf_asm(op, x.mnemonic); + } + + return op->size; +} diff --git a/librz/arch/isa/pic/pic16.h b/librz/arch/isa/pic/pic16.h new file mode 100644 index 00000000000..79c43bff8f7 --- /dev/null +++ b/librz/arch/isa/pic/pic16.h @@ -0,0 +1,142 @@ +// SPDX-FileCopyrightText: 2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef PIC16_H +#define PIC16_H + +#include +#include + +static inline bool is_pic16(const char *x) { + return RZ_STR_EQ(x, "midrange") || RZ_STR_EQ(x, "pic16"); +} + +static inline bool is_pic14_or_pic16(const char *x) { + return RZ_STR_EQ(x, "baseline") || + RZ_STR_EQ(x, "pic14") || + is_pic16(x); +} + +typedef enum { + PIC16_OP_ARGS_NONE = 0, + PIC16_OP_ARGS_2F, + PIC16_OP_ARGS_7F, + PIC16_OP_ARGS_1D_7F, + PIC16_OP_ARGS_1N_6K, + PIC16_OP_ARGS_3B_7F, + PIC16_OP_ARGS_4K, + PIC16_OP_ARGS_8K, + PIC16_OP_ARGS_9K, + PIC16_OP_ARGS_11K, + PIC16_OP_ARGS_1N_2M +} Pic16OpArgs; + +#define PIC16_OP_ARGS_2F_MASK_F 0x3 +#define PIC16_OP_ARGS_7F_MASK_F 0x7f +#define PIC16_OP_ARGS_1D_7F_MASK_D (1 << 7) +#define PIC16_OP_ARGS_1D_7F_MASK_F 0x7f +#define PIC16_OP_ARGS_1N_6K_MASK_N (1 << 6) +#define PIC16_OP_ARGS_1N_6K_MASK_K 0x3f +#define PIC16_OP_ARGS_3B_7F_MASK_B (0x7 << 7) +#define PIC16_OP_ARGS_3B_7F_MASK_F 0x7f +#define PIC16_OP_ARGS_4K_MASK_K 0xf +#define PIC16_OP_ARGS_8K_MASK_K 0xff +#define PIC16_OP_ARGS_9K_MASK_K 0x1ff +#define PIC16_OP_ARGS_11K_MASK_K 0x7ff +#define PIC16_OP_ARGS_1N_2M_MASK_N (1 << 2) +#define PIC16_OP_ARGS_1N_2M_MASK_M 0x3 + +typedef struct _pic16_op { + const char *mnemonic; + Pic16OpArgs args; +} Pic16OpAsmInfo; + +typedef enum { + PIC16_OPCODE_NOP = 0, + PIC16_OPCODE_RETURN, + PIC16_OPCODE_RETFIE, + PIC16_OPCODE_OPTION, + PIC16_OPCODE_SLEEP, + PIC16_OPCODE_CLRWDT, + PIC16_OPCODE_CLRF, + PIC16_OPCODE_CLRW, + PIC16_OPCODE_TRIS, + PIC16_OPCODE_MOVWF, + PIC16_OPCODE_SUBWF, + PIC16_OPCODE_DECF, + PIC16_OPCODE_IORWF, + PIC16_OPCODE_ANDWF, + PIC16_OPCODE_XORWF, + PIC16_OPCODE_ADDWF, + PIC16_OPCODE_MOVF, + PIC16_OPCODE_COMF, + PIC16_OPCODE_INCF, + PIC16_OPCODE_DECFSZ, + PIC16_OPCODE_RRF, + PIC16_OPCODE_RLF, + PIC16_OPCODE_SWAPF, + PIC16_OPCODE_INCFSZ, + PIC16_OPCODE_BCF, + PIC16_OPCODE_BSF, + PIC16_OPCODE_BTFSC, + PIC16_OPCODE_BTFSS, + PIC16_OPCODE_CALL, + PIC16_OPCODE_GOTO, + PIC16_OPCODE_MOVLW, + PIC16_OPCODE_RETLW, + PIC16_OPCODE_IORLW, + PIC16_OPCODE_ANDLW, + PIC16_OPCODE_XORLW, + PIC16_OPCODE_SUBLW, + PIC16_OPCODE_ADDLW, + PIC16_OPCODE_RESET, + PIC16_OPCODE_CALLW, + PIC16_OPCODE_BRW, + PIC16_OPCODE_MOVIW_1, + PIC16_OPCODE_MOVWI_1, + PIC16_OPCODE_MOVLB, + PIC16_OPCODE_LSLF, + PIC16_OPCODE_LSRF, + PIC16_OPCODE_ASRF, + PIC16_OPCODE_SUBWFB, + PIC16_OPCODE_ADDWFC, + PIC16_OPCODE_ADDFSR, + PIC16_OPCODE_MOVLP, + PIC16_OPCODE_BRA, + PIC16_OPCODE_MOVIW_2, + PIC16_OPCODE_MOVWI_2, + PIC16_OPCODE_INVALID +} Pic16Opcode; + +typedef struct _pic16_op_args_val { + ut16 f; + st16 k; + ut8 d; + ut8 m; + ut8 n; + ut8 b; +} Pic16OpArgsVal; + +typedef struct { + const char *mnemonic; + char operands[32]; + Pic16OpArgs args_tag; + Pic16OpArgsVal args; + ut32 addr; + Pic16Opcode opcode; + ut32 size; + ut16 instr; +} Pic16Op; + +Pic16Opcode pic16_get_opcode(ut16 instr); +const Pic16OpAsmInfo *pic16_get_op_info(Pic16Opcode opcode); +bool pic16_disasm_op(Pic16Op *op, ut64 addr, const ut8 *b, ut64 len); +int pic16_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l); + +int pic16_op( + RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask); +char *pic16_get_reg_profile(RzAnalysis *a); +RzAnalysisILConfig *pic16_il_config(RZ_NONNULL RzAnalysis *analysis); + +#endif // PIC16_H diff --git a/librz/arch/isa/pic/pic16_analysis.c b/librz/arch/isa/pic/pic16_analysis.c new file mode 100644 index 00000000000..4f671151102 --- /dev/null +++ b/librz/arch/isa/pic/pic16_analysis.c @@ -0,0 +1,212 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#include "pic.h" +#include "pic16.h" +#include "pic16_il.inc" + +typedef void (*pic16_inst_handler_t)(RzAnalysis *analysis, RzAnalysisOp *op, + ut64 addr, + Pic16OpArgsVal *args); + +typedef struct { + Pic16Opcode opcode; + pic16_inst_handler_t handler; + pic16_il_handler il_handler; +} Pic16OpAnalysisInfo; + +#define INST_HANDLER(OPCODE_NAME) \ + static void _inst__##OPCODE_NAME(RzAnalysis *analysis, RzAnalysisOp *op, \ + ut64 addr, \ + Pic16OpArgsVal *args) +#define INST_DECL(NAME) \ + [PIC16_OPCODE_##NAME] = { \ + PIC16_OPCODE_##NAME, _inst__##NAME, IL_LIFTER(NAME) \ + } + +#include "pic16_esil.inc" + +static const Pic16OpAnalysisInfo pic16_op_analysis_info[] = { + INST_DECL(NOP), + INST_DECL(RETURN), + INST_DECL(RETFIE), + INST_DECL(OPTION), + INST_DECL(SLEEP), + INST_DECL(CLRWDT), + INST_DECL(TRIS), + INST_DECL(MOVWF), + INST_DECL(SUBWF), + INST_DECL(DECF), + INST_DECL(IORWF), + INST_DECL(ANDWF), + INST_DECL(XORWF), + INST_DECL(ADDWF), + INST_DECL(MOVF), + INST_DECL(COMF), + INST_DECL(INCF), + INST_DECL(DECFSZ), + INST_DECL(RRF), + INST_DECL(RLF), + INST_DECL(SWAPF), + INST_DECL(INCFSZ), + INST_DECL(BCF), + INST_DECL(BSF), + INST_DECL(BTFSC), + INST_DECL(BTFSS), + INST_DECL(CALL), + INST_DECL(GOTO), + INST_DECL(MOVLW), + INST_DECL(RETLW), + INST_DECL(IORLW), + INST_DECL(ANDLW), + INST_DECL(XORLW), + INST_DECL(SUBLW), + INST_DECL(ADDLW), + INST_DECL(RESET), + INST_DECL(CALLW), + INST_DECL(BRW), + INST_DECL(MOVIW_1), + INST_DECL(MOVWI_1), + INST_DECL(MOVLB), + INST_DECL(LSLF), + INST_DECL(LSRF), + INST_DECL(ASRF), + INST_DECL(SUBWFB), + INST_DECL(ADDWFC), + INST_DECL(ADDFSR), + INST_DECL(MOVLP), + INST_DECL(BRA), + INST_DECL(MOVIW_2), + INST_DECL(MOVWI_2), + INST_DECL(CLRF), + INST_DECL(CLRW), +}; + +static RzIODesc *cpu_memory_map( + RzIOBind *iob, RzIODesc *desc, ut32 addr, ut32 size) { + char mstr[16]; + rz_strf(mstr, "malloc://%d", size); + if (desc && iob->fd_get_name(iob->io, desc->fd)) { + iob->fd_remap(iob->io, desc->fd, addr); + } else { + desc = iob->open_at(iob->io, mstr, RZ_PERM_RW, 0, addr, NULL); + } + return desc; +} + +static bool pic16_reg_write(RzReg *reg, const char *regname, ut32 num) { + if (reg) { + RzRegItem *item = rz_reg_get(reg, regname, RZ_REG_TYPE_GPR); + if (item) { + rz_reg_set_value(reg, item, num); + return true; + } + } + return false; +} + +static void analysis_pic16_setup(RzAnalysis *analysis, bool force) { + PicContext *ctx = (PicContext *)analysis->plugin_data; + + if (!ctx->init_done || force) { + // Allocate memory as needed. + // We assume that code is already allocated with firmware + // image + ctx->mem_sram = + cpu_memory_map(&analysis->iob, ctx->mem_sram, + PIC16_ESIL_SRAM_START, 0x1000); + ctx->mem_stack = + cpu_memory_map(&analysis->iob, ctx->mem_sram, + PIC16_ESIL_CSTACK_TOP, 0x20); + + pic16_reg_write(analysis->reg, "_sram", + PIC16_ESIL_SRAM_START); + pic16_reg_write(analysis->reg, "_stack", + PIC16_ESIL_CSTACK_TOP); + pic16_reg_write(analysis->reg, "stkptr", 0x1f); + + ctx->init_done = true; + } +} + +int pic16_op( + RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + + if (!buf || len < 2) { + op->type = RZ_ANALYSIS_OP_TYPE_ILL; + return -1; + } + Pic16Op x = { 0 }; + if (!pic16_disasm_op(&x, addr, buf, len)) { + return -1; + } + if (!(x.opcode < RZ_ARRAY_SIZE(pic16_op_analysis_info))) { + return -1; + } + const Pic16OpAnalysisInfo *info = pic16_op_analysis_info + x.opcode; + if (!info) { + return -1; + } + + op->size = x.size; + op->cycles = 1; + op->type = RZ_ANALYSIS_OP_TYPE_NOP; + + if (mask & RZ_ANALYSIS_OP_MASK_ESIL && info->handler) { + analysis_pic16_setup(analysis, false); + info->handler(analysis, op, addr, &x.args); + } + if (mask & RZ_ANALYSIS_OP_MASK_IL && info->il_handler) { + Pic16ILContext il_ctx = { + .analysis = analysis, + .op = op, + .x = &x, + }; + op->il_op = info->il_handler(&il_ctx, x.opcode); + } + if (mask & RZ_ANALYSIS_OP_MASK_DISASM) { + op->mnemonic = rz_str_newf("%s%s%s", + x.mnemonic, + x.operands[0] ? " " : "", + x.operands); + } + + return op->size; +} + +char *pic16_get_reg_profile(RzAnalysis *a) { + const char *p = + "=PC pc\n" + "=SP stkptr\n" + "=A0 porta\n" + "=A1 portb\n" + "gpr indf0 .8 0 0\n" + "gpr indf1 .8 1 0\n" + "gpr pcl .8 2 0\n" + "gpr status .8 3 0\n" + "flg c .1 3.0 0\n" + "flg dc .1 3.1 0\n" + "flg z .1 3.2 0\n" + "flg pd .1 3.3 0\n" + "flg to .1 3.4 0\n" + "gpr fsr0l .8 4 0\n" + "gpr fsr0h .8 5 0\n" + "gpr fsr1l .8 6 0\n" + "gpr fsr1h .8 7 0\n" + "gpr bsr .8 8 0\n" + "gpr wreg .8 9 0\n" + "gpr pclath .8 10 0\n" + "gpr intcon .8 11 0\n" + "gpr pc .16 12 0\n" + "gpr stkptr .8 14 0\n" + "gpr _sram .32 15 0\n" + "gpr _stack .32 19 0\n" + "gpr tosl .8 24 0\n" + "gpr tosh .8 25 0\n" + "gpr tris .8 26 0\n" + "gpr _bank .8 27 0\n"; + return strdup(p); +} diff --git a/librz/arch/isa/pic/pic16_esil.inc b/librz/arch/isa/pic/pic16_esil.inc new file mode 100644 index 00000000000..8788135e6b7 --- /dev/null +++ b/librz/arch/isa/pic/pic16_esil.inc @@ -0,0 +1,515 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#define e(frag) rz_strbuf_append(&op->esil, frag) +#define ef(frag, ...) rz_strbuf_appendf(&op->esil, frag, __VA_ARGS__) + +#define PIC16_ESIL_SRAM_START (1 << 16) +#define PIC16_ESIL_CSTACK_TOP ((1 << 16) + (1 << 12)) + +#define PIC16_ESIL_BSR_ADDR "bsr,0x80,*,0x%x,+,_sram,+" + +#define PIC16_ESIL_OPTION_ADDR "0x95,_sram,+" + +#define PIC16_ESIL_UPDATE_FLAGS \ + "$z,z,:=," \ + "7,$c,c,:=," \ + "4,$c,dc,:=," + +#define PIC16_ESIL_LW_OP(O) \ + "0x%x,wreg," #O "=," PIC16_ESIL_UPDATE_FLAGS + +#define PIC16_ESIL_FWF_OP(O) \ + "wreg," PIC16_ESIL_BSR_ADDR "," #O \ + "=[1]," PIC16_ESIL_UPDATE_FLAGS + +#define PIC16_ESIL_WWF_OP(O) \ + PIC16_ESIL_BSR_ADDR \ + ",[1]," \ + "wreg," #O "=," PIC16_ESIL_UPDATE_FLAGS + +#define PIC16_ESIL_FWF_OP_C(O) \ + "c,wreg," \ + "+," PIC16_ESIL_BSR_ADDR "," #O \ + "=[1]," PIC16_ESIL_UPDATE_FLAGS + +#define PIC16_ESIL_WWF_OP_C(O) \ + "c," PIC16_ESIL_BSR_ADDR ",[1]," #O "," \ + "wreg," #O "=," PIC16_ESIL_UPDATE_FLAGS + +INST_HANDLER(NOP) {} + +INST_HANDLER(RETFIE) { + op->type = RZ_ANALYSIS_OP_TYPE_RET; +} + +INST_HANDLER(OPTION) { + op->type = RZ_ANALYSIS_OP_TYPE_STORE; +} + +INST_HANDLER(TRIS) { + op->type = RZ_ANALYSIS_OP_TYPE_STORE; +} + +INST_HANDLER(RETURN) { + op->type = RZ_ANALYSIS_OP_TYPE_RET; + e("0x1f,stkptr,==,$z,?{,BREAK,},"); + e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); + e("0x01,stkptr,-=,"); + e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); +} + +INST_HANDLER(CALL) { + ut64 pclath; + op->type = RZ_ANALYSIS_OP_TYPE_CALL; + rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); + op->jump = 2 * (((pclath & 0x78) << 8) + args->k); + ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); + e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x01,stkptr,+=,"); + ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); +} + +INST_HANDLER(GOTO) { + ut64 pclath; + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); + op->jump = 2 * (((pclath & 0x78) << 8) + args->k); + ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); +} + +INST_HANDLER(BCF) { + ut8 mask = ~(1 << args->b); + ef(PIC16_ESIL_BSR_ADDR + ",[1],0x%x,&," PIC16_ESIL_BSR_ADDR ",=[1],", + args->f, mask, args->f); +} + +INST_HANDLER(BSF) { + ut8 mask = (1 << args->b); + ef(PIC16_ESIL_BSR_ADDR + ",[1],0x%x,|," PIC16_ESIL_BSR_ADDR ",=[1],", + args->f, mask, args->f); +} + +INST_HANDLER(BTFSC) { + ut8 mask = (1 << args->b); + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + ef(PIC16_ESIL_BSR_ADDR ",[1],0x%x,&,!,?{,0x%" PFMT64x ",pc,=,},", + args->f, mask, op->jump); +} + +INST_HANDLER(BTFSS) { + ut8 mask = (1 << args->b); + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + ef(PIC16_ESIL_BSR_ADDR ",[1],0x%x,&,?{,0x%" PFMT64x ",pc,=,},", args->f, + mask, op->jump); +} + +INST_HANDLER(BRA) { + st16 branch = args->k; + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + branch |= ((branch & 0x100) ? 0xfe00 : 0); + op->jump = addr + 2 * (branch + 1); + ef("%s0x%x,1,+,2,*,pc,+=,", branch < 0 ? "-" : "", + branch < 0 ? -branch : branch); +} + +INST_HANDLER(BRW) { + ut64 wreg; + op->type = RZ_ANALYSIS_OP_TYPE_UJMP; + rz_analysis_esil_reg_read(analysis->esil, "wreg", &wreg, NULL); + op->jump = addr + 2 * (wreg + 1); + e("wreg,1,+,2,*,pc,+=,"); +} + +INST_HANDLER(SUBWF) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + if (args->d) { + ef(PIC16_ESIL_FWF_OP(-), args->f); + } else { + ef(PIC16_ESIL_WWF_OP(-), args->f); + e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); + } +} + +INST_HANDLER(DECFSZ) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + if (args->d) { + ef("0x01," PIC16_ESIL_BSR_ADDR ",-=[1],", args->f); + } else { + ef("0x01," PIC16_ESIL_BSR_ADDR ",[1],-,wreg,=,", + args->f); + } + ef(PIC16_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, + op->jump); +} + +INST_HANDLER(INCFSZ) { + op->type = RZ_ANALYSIS_OP_TYPE_CJMP; + op->jump = addr + 4; + op->fail = addr + 2; + if (args->d) { + ef("0x01," PIC16_ESIL_BSR_ADDR ",+=[1],", args->f); + } else { + ef("0x01," PIC16_ESIL_BSR_ADDR ",[1],+,wreg,=,", + args->f); + } + ef(PIC16_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, + op->jump); +} + +INST_HANDLER(INCF) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->d) { + ef("0x01," PIC16_ESIL_BSR_ADDR ",+=[1],", args->f); + } else { + ef("0x01," PIC16_ESIL_BSR_ADDR ",[1],+,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(DECF) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + if (args->d) { + ef("0x01," PIC16_ESIL_BSR_ADDR ",-=[1],", args->f); + } else { + ef("0x01," PIC16_ESIL_BSR_ADDR ",[1],-,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(IORWF) { + op->type = RZ_ANALYSIS_OP_TYPE_OR; + if (args->d) { + ef(PIC16_ESIL_FWF_OP(|), args->f); + } else { + ef(PIC16_ESIL_WWF_OP(|), args->f); + } +} + +INST_HANDLER(ANDWF) { + op->type = RZ_ANALYSIS_OP_TYPE_AND; + if (args->d) { + ef(PIC16_ESIL_FWF_OP(&), args->f); + } else { + ef(PIC16_ESIL_WWF_OP(&), args->f); + } +} + +INST_HANDLER(XORWF) { + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + if (args->d) { + ef(PIC16_ESIL_FWF_OP(^), args->f); + } else { + ef(PIC16_ESIL_WWF_OP(^), args->f); + } +} + +INST_HANDLER(ADDWF) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->d) { + ef(PIC16_ESIL_FWF_OP(+), args->f); + } else { + ef(PIC16_ESIL_WWF_OP(+), args->f); + } +} + +INST_HANDLER(SUBLW) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + ef(PIC16_ESIL_LW_OP(-), args->k); +} + +INST_HANDLER(ADDLW) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + ef(PIC16_ESIL_LW_OP(+), args->k); +} + +INST_HANDLER(IORLW) { + op->type = RZ_ANALYSIS_OP_TYPE_OR; + ef(PIC16_ESIL_LW_OP(|), args->k); +} + +INST_HANDLER(ANDLW) { + op->type = RZ_ANALYSIS_OP_TYPE_AND; + ef(PIC16_ESIL_LW_OP(&), args->k); +} + +INST_HANDLER(XORLW) { + op->type = RZ_ANALYSIS_OP_TYPE_XOR; + ef(PIC16_ESIL_LW_OP(^), args->k); +} + +INST_HANDLER(MOVLW) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + ef("0x%x,wreg,=,", args->k); +} + +INST_HANDLER(RETLW) { + op->type = RZ_ANALYSIS_OP_TYPE_RET; + ef("0x%x,wreg,=,", args->k); + e("0x1f,stkptr,==,$z,?{,BREAK,},"); + e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); + e("0x01,stkptr,-=,"); + e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); +} + +INST_HANDLER(MOVLP) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + ef("0x%x,pclath,=,", args->f); +} + +INST_HANDLER(MOVLB) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + ef("0x%x,bsr,=,", args->k); +} + +INST_HANDLER(CALLW) { + op->type = RZ_ANALYSIS_OP_TYPE_UCALL; + e("8,pclath,<<,0x%x,+,wreg,2,*,pc,=,"); + e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); + e("0x01,stkptr,+=,"); + ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); +} + +INST_HANDLER(MOVWF) { + op->type = RZ_ANALYSIS_OP_TYPE_STORE; + ef("wreg," PIC16_ESIL_BSR_ADDR ",=[1],", args->f); +} + +INST_HANDLER(MOVF) { + op->type = RZ_ANALYSIS_OP_TYPE_LOAD; + if (args->d) { + ef(PIC16_ESIL_BSR_ADDR + ",[1]," PIC16_ESIL_BSR_ADDR ",=[1],", + args->f, args->f); + } else { + ef(PIC16_ESIL_BSR_ADDR ",[1],wreg,=,", args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(SWAPF) { + ef("4," PIC16_ESIL_BSR_ADDR ",[1],>>,0x0f,&,", args->f); + ef("4," PIC16_ESIL_BSR_ADDR ",[1],<<,0xf0,&,", args->f); + e("|,"); + ef(PIC16_ESIL_BSR_ADDR ",=[1],", args->f); +} + +INST_HANDLER(LSLF) { + op->type = RZ_ANALYSIS_OP_TYPE_SHL; + ef("7," PIC16_ESIL_BSR_ADDR ",[1],>>,c,=,", args->f); + if (args->d) { + ef("1," PIC16_ESIL_BSR_ADDR ",<<=[1],", args->f); + } else { + ef("1," PIC16_ESIL_BSR_ADDR ",[1],<<,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(LSRF) { + op->type = RZ_ANALYSIS_OP_TYPE_SHR; + ef("1," PIC16_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); + if (args->d) { + ef("1," PIC16_ESIL_BSR_ADDR ",>>=[1],", args->f); + } else { + ef("1," PIC16_ESIL_BSR_ADDR ",[1],>>,wreg,=,", + args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(ASRF) { + op->type = RZ_ANALYSIS_OP_TYPE_SHR; + ef("1," PIC16_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); + ef("1," PIC16_ESIL_BSR_ADDR ",[1],>>,", args->f); + ef("0x80," PIC16_ESIL_BSR_ADDR ",[1],&,", args->f); + if (args->d) { + ef("|," PIC16_ESIL_BSR_ADDR ",=[1],", args->f); + } else { + e("|,wreg,=,"); + } + e("$z,z,:=,"); +} + +INST_HANDLER(RRF) { + op->type = RZ_ANALYSIS_OP_TYPE_ROR; + ef("1," PIC16_ESIL_BSR_ADDR ",[1],&,", args->f); + if (args->d) { + ef("1," PIC16_ESIL_BSR_ADDR ",>>=[1]," + "c," PIC16_ESIL_BSR_ADDR ",|=[1],", + args->f, args->f); + } else { + ef("1," PIC16_ESIL_BSR_ADDR ",[1],>>,wreg,=," + "c,wreg,|=[1],", + args->f); + } + e("c,=,"); +} + +INST_HANDLER(RLF) { + op->type = RZ_ANALYSIS_OP_TYPE_ROL; + ef("7," PIC16_ESIL_BSR_ADDR ",[1],>>,", args->f); + if (args->d) { + ef("1," PIC16_ESIL_BSR_ADDR ",<<=[1]," + "c," PIC16_ESIL_BSR_ADDR ",|=[1],", + args->f, args->f); + } else { + ef("1," PIC16_ESIL_BSR_ADDR ",[1],<<,wreg,=," + "c,wreg,|=[1],", + args->f); + } + e("c,=,"); +} + +INST_HANDLER(COMF) { + if (args->d) { + ef("0xff," PIC16_ESIL_BSR_ADDR ",^=[1],", args->f); + } else { + ef("0xff," PIC16_ESIL_BSR_ADDR ",^,wreg,=,", args->f); + } + e("$z,z,:=,"); +} + +INST_HANDLER(RESET) { + op->type = RZ_ANALYSIS_OP_TYPE_JMP; + op->jump = 0; + e("0x0,pc,=,"); + e("0x1f,stkptr,=,"); +} + +INST_HANDLER(ADDFSR) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->n == 0) { + ef("0x%x,fsr0l,+=,", args->k); + e("7,$c,?{,0x01,fsr0h,+=,},"); + } else { + ef("0x%x,fsr1l,+=,", args->k); + e("7,$c,?{,0x01,fsr1h,+=,},"); + } +} + +INST_HANDLER(CLRWDT) { + e("1,to,=,"); + e("1,pd,=,"); +} + +INST_HANDLER(SLEEP) { + e("1,to,=,"); + e("0,pd,=,"); +} + +INST_HANDLER(SUBWFB) { + op->type = RZ_ANALYSIS_OP_TYPE_SUB; + e("c,!=,"); + if (args->d) { + ef(PIC16_ESIL_FWF_OP_C(-), args->f); + } else { + ef(PIC16_ESIL_WWF_OP_C(-), args->f); + e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); + } +} + +INST_HANDLER(ADDWFC) { + op->type = RZ_ANALYSIS_OP_TYPE_ADD; + if (args->d) { + ef(PIC16_ESIL_FWF_OP_C(+), args->f); + } else { + ef(PIC16_ESIL_WWF_OP_C(+), args->f); + } +} + +INST_HANDLER(MOVIW_1) { + if (args->n == 0) { + if (!(args->m & 2)) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + e("indf0,wreg,=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } else { + if (!(args->m & 2)) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + e("indf1,wreg,=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } +} + +INST_HANDLER(MOVWI_1) { + if (args->n == 0) { + if (!(args->m & 2)) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + e("wreg,indf0=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } else { + if (!(args->m & 2)) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7,fsr1h,%s,", (args->m & 1) ? ",!" : ""); + } + e("wreg,indf1=,"); + e("$z,z,:=,"); + if (args->m & 2) { + ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); + ef("$c7%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", + (args->m & 1) ? "-" : "+"); + } + } +} + +INST_HANDLER(MOVIW_2) { + if (args->n == 0) { + e("fsr0l,8,fsr0h,<<,+,"); + } else { + e("fsr1l,8,fsr1h,<<,+,"); + } + ef("0x%x,+,[1],wreg,=,", args->k); +} + +INST_HANDLER(MOVWI_2) { + e("wreg,"); + if (args->n == 0) { + e("fsr0l,8,fsr0h,<<,+,"); + } else { + e("fsr1l,8,fsr1h,<<,+,"); + } + e("=[1],"); +} + +INST_HANDLER(CLRF) {} + +INST_HANDLER(CLRW) {} diff --git a/librz/arch/isa/pic/pic16_il.inc b/librz/arch/isa/pic/pic16_il.inc new file mode 100644 index 00000000000..6a9fcd652d3 --- /dev/null +++ b/librz/arch/isa/pic/pic16_il.inc @@ -0,0 +1,579 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-FileCopyrightText: 2024 Billow +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include "pic16.h" +#include "pic_il.inc" + +enum { + INDF0, + INDF1, + PCL, + STATUS, + FSR0L, + FSR0H, + FSR1L, + FSR1H, + BSR, + WREG, + PCLATH, + INTCON, +} GPRs; + +static ut16 OPTION_REG = 1; + +enum { + RBIF, + INTF, + T0IF, + BEIF, + INTE, + T0IE, + PEIE, + GIE +} INTCON_Register; + +enum { + C, + DC, + Z, + PD, + TO, + RP0, + RP1, + IRP +} STAUTS_Register; + +static const ut16 STKPTR = 0xfed; +static const ut16 TOSL = 0xfee; +static const ut16 TOSH = 0xfef; + +typedef struct pic16_il_context_t { + RzAnalysis *analysis; + RzAnalysisOp *op; + const Pic16Op *x; +} Pic16ILContext; + +static RzILOpPure *register_i(ut16 i); +static RzILOpEffect *set_register_i(ut16 i, RzILOpPure *x); + +#define K (ctx->x->args.k) +#define D (ctx->x->args.d) +#define F (ctx->x->args.f) +#define B (ctx->x->args.b) +#define N (ctx->x->args.n) +#define PC (ctx->x->addr) +#define VPC (U16(PC)) + +static RzILOpPure *val_fsrn(ut8 n) { + rz_return_val_if_fail(n <= 1, NULL); + return APPEND(register_i(2 * n + FSR0L + 1), register_i(2 * n + FSR0L)); +} +static RzILOpEffect *set_fsrn(ut8 n, RzILOpPure *x) { + rz_return_val_if_fail(n <= 1, NULL); + return SEQ3( + SETL("__x", x), + set_register_i(2 * n + FSR0L + 1, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(8)))), + set_register_i(2 * n + FSR0L, UNSIGNED(8, VARL("__x")))); +} + +static RzILOpPure *val_bank() { + return VARG("_bank"); +} +static RzILOpEffect *set_bank() { + return SETG("_bank", LOGAND(register_i(BSR), U8(0x1f))); +} + +static RzILOpPure *register_i(ut16 i) { + rz_warn_if_fail(i < 0x80); + if (i == INDF0 || i == INDF1) { + return LOAD(val_fsrn(i - INDF0)); + } + + return LOAD(ADD(U16(i), UNSIGNED(16, MUL(val_bank(), U8(0x80))))); +} +static RzILOpEffect *set_register_i(ut16 i, RzILOpPure *x) { + rz_warn_if_fail(i < 0x80); + if (i == INDF0 || i == INDF1) { + return STORE(val_fsrn(i - INDF0), x); + } + + RzILOpEffect *eff = STORE(ADD(U16(i), UNSIGNED(16, MUL(val_bank(), U8(0x80)))), x); + if (i == BSR) { + return SEQ2(eff, set_bank()); + } + return eff; +} +#define VARGi(i) register_i(i) +#define SETGi(i, x) set_register_i(i, x) +#define VARGb(i, b) bit_get(register_i(i), b) +#define SETGb(i, b, x) set_register_i(i, bit_set1(register_i(i), b, x)) + +#define VRW register_i(WREG) +#define SET_W(x) set_register_i(WREG, x) +#define VRF register_i(F) +#define SET_F(x) set_register_i(F, x) + +#define VTOS APPEND(LOAD(U16(TOSH)), LOAD(U16(TOSL))) +#define SET_TOS(x) SEQ3(SETL("__tos", x), \ + STORE(U16(TOSH), UNSIGNED(8, SHIFTR0(VARL("__tos"), U8(8)))), \ + STORE(U16(TOSL), UNSIGNED(8, VARL("__tos")))) + +static RzILOpPure *register_WF(Pic16ILContext *ctx) { + rz_warn_if_fail(F < 0x80); + return D ? VRW : VRF; +} +static RzILOpEffect *set_register_WF(Pic16ILContext *ctx, RzILOpPure *x) { + rz_warn_if_fail(F < 0x80); + return D ? SET_F(x) : SET_W(x); +} +#define VRWF register_WF(ctx) +#define SET_WF(x) (set_register_WF(ctx, x)) + +typedef RzILOpEffect *(*pic16_il_handler)(Pic16ILContext *, ut16); + +RzILOpEffect *reset() { + return NOP(); +} + +RzILOpEffect *set_z(Pic16ILContext *ctx, RzILOpPure *x) { + return SETGb(STATUS, Z, IS_ZERO(x)); +} + +#define SETZ(x) set_z(ctx, x) + +// HELPER DEFINES & TYPEDEFS + +#define IL_LIFTER(op) pic16_##op##_il_lifter +#define IL_LIFTER_IMPL(op) static RzILOpEffect *pic16_##op##_il_lifter( \ + RZ_NONNULL Pic16ILContext *ctx, ut16 instr) + +#define INS_LEN 2 + +/** + * Handle C, DC & Z flags for the previous operation. + * To be used after an arithmetic operation. + * Order of operands must be preserved for subtraction + * operations, i.e `add = false` + * + * \param x First operand + * \param y Second operand + * \param res Result of last performed operation that affected the flag. + * \param add Was this an add operation? + * + * \return \c RzILOpEffect containing set of steps to set status flags. + * */ +RzILOpEffect *pic16_il_set_arithmetic_flags(Pic16ILContext *ctx, + RZ_BORROW RzILOpPure *x, RZ_BORROW RzILOpPure *y, RZ_BORROW RzILOpPure *res, bool add) { + // get carry flag + RzILOpBool *cf = NULL; + RzILOpBool *dcf = NULL; + if (add) { + cf = CHECK_CARRY(VARL("status_x"), VARL("status_y"), VARL("status_res")); + dcf = CHECK_DIGIT_CARRY(VARL("status_x"), VARL("status_y"), VARL("status_res")); + } else { // sub + cf = CHECK_CARRY(VARL("status_x"), NEG(VARL("status_y")), VARL("status_res")); + dcf = CHECK_DIGIT_CARRY(VARL("status_x"), NEG(VARL("status_y")), VARL("status_res")); + } + + // get zero flag + RzILOpBool *zf = IS_ZERO(VARL("status_res")); + + return SEQ8( + SETL("status_x", x), + SETL("status_y", y), + SETL("status_res", res), + SETL("_c", cf), + SETL("_dc", dcf), + SETL("_z", zf), + SETL("_status", register_i(STATUS)), + SETGi(STATUS, + bit_set1( + bit_set1( + bit_set1(VARL("_status"), C, VARL("_c")), + DC, + VARL("_dc")), + Z, VARL("_z")))); +} + +#define SET_STATUS_ADD(ctx, x, y, r) pic16_il_set_arithmetic_flags(ctx, x, y, r, true) +#define SET_STATUS_SUB(ctx, x, y, r) pic16_il_set_arithmetic_flags(ctx, x, y, r, false) + +/** + * NOP + * Operation: No Operation. + * Operands: NONE + * Status affected : NONE + * */ +IL_LIFTER_IMPL(NOP) { + return NOP(); +} + +/** + * ADDLW. + * Operation: Add Literal To wreg + * Operands: Literal (k) + * Status affected : C, DC, Z + * */ +IL_LIFTER_IMPL(ADDLW) { + return SEQ4( + SETL("_w", VRW), + SETL("_res", ADD(VARL("_w"), U8(K))), + SET_W(VARL("_res")), + SET_STATUS_ADD(ctx, VARL("_w"), U8(K), VARL("_res"))); +} + +/** + * ADDWF + * Operation: Add freg to wreg. + * Operands: f, d + * Status affected : C, DC, Z + * */ +IL_LIFTER_IMPL(ADDWF) { + return SEQ5( + SETL("_w", VRW), + SETL("_f", VRF), + SETL("_res", ADD(VARL("_w"), VARL("_f"))), + SET_WF(VARL("_res")), + SET_STATUS_ADD(ctx, VARL("_w"), VARL("_f"), VARL("_res"))); +} + +IL_LIFTER_IMPL(ANDLW) { + return SEQ2( + SET_W(LOGAND(VRW, U8(K))), + SETZ(VRW)); +} + +/** + * ANDWF + * Operation: Take logical AND of freg and wreg. + * Operands: f, d + * Status affected : Z + * */ +IL_LIFTER_IMPL(ANDWF) { + return SEQ2( + SET_WF(LOGAND(VRW, VRF)), + SETZ(VRWF)); +} + +IL_LIFTER_IMPL(BCF) { + return SET_F(bit_set(VRF, B, 0)); +} + +IL_LIFTER_IMPL(BSF) { + return SET_F(bit_set(VRF, B, 1)); +} + +IL_LIFTER_IMPL(BTFSC) { + return BRANCH(bit_get(VRF, B), NOP(), JMP(U16(PC + INS_LEN * 2))); +} + +IL_LIFTER_IMPL(BTFSS) { + return BRANCH(bit_get(VRF, B), JMP(U16(PC + INS_LEN * 2)), NOP()); +} + +IL_LIFTER_IMPL(CALL) { + return SEQ2( + SET_TOS(U16(PC + INS_LEN)), + JMP(LOGOR(U16(K), SHIFTL0(UNSIGNED(16, pure_slice(register_i(PCLATH), 3, 4)), U16(11))))); +} + +IL_LIFTER_IMPL(CLRF) { + return SEQ2( + SET_F(U8(0)), + SETGb(STATUS, Z, IL_TRUE)); +} + +IL_LIFTER_IMPL(CLRW) { + return SEQ2( + SET_W(U8(0)), + SETGb(STATUS, Z, IL_TRUE)); +} + +IL_LIFTER_IMPL(CLRWDT) { + return NOP(); +} + +IL_LIFTER_IMPL(COMF) { + return SEQ2( + SET_WF(NEG(VRF)), + SETGb(STATUS, Z, IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(DECF) { + return SEQ2( + SET_WF(SUB(VRF, U8(1))), + SETGb(STATUS, Z, IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(DECFSZ) { + return SEQ2( + SET_WF(SUB(VRF, U8(1))), + BRANCH(IS_ZERO(VRWF), + JMP(U16(PC + INS_LEN * 2)), + NOP())); +} + +IL_LIFTER_IMPL(GOTO) { + return JMP(LOGOR(U16(K), SHIFTL0(UNSIGNED(16, pure_slice(register_i(PCLATH), 3, 5)), U16(11)))); +} + +IL_LIFTER_IMPL(INCF) { + return SEQ2( + SET_WF(ADD(VRF, U8(1))), + SETGb(STATUS, Z, IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(INCFSZ) { + return SEQ2( + SET_WF(ADD(VRF, U8(1))), + BRANCH(IS_ZERO(VRWF), + JMP(U16(PC + INS_LEN * 2)), + NOP())); +} + +IL_LIFTER_IMPL(IORLW) { + return SEQ2( + SET_W(LOGOR(VRW, U8(K))), + SETGb(STATUS, Z, IS_ZERO(VRW))); +} + +IL_LIFTER_IMPL(IORWF) { + return SEQ2( + SET_WF(LOGOR(VRW, VRF)), + SETGb(STATUS, Z, IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(MOVLW) { + return SET_W(U8(K)); +} + +IL_LIFTER_IMPL(MOVF) { + return SEQ2(SET_WF(VRF), + SETGb(STATUS, Z, IS_ZERO(VRWF))); +} + +IL_LIFTER_IMPL(MOVWF) { + return SET_F(VRW); +} + +IL_LIFTER_IMPL(OPTION) { + return SETGi(OPTION_REG, VRW); +} + +IL_LIFTER_IMPL(RETFIE) { + return SEQ2( + SET_TOS(VPC), + SETGb(INTCON, GIE, IL_TRUE)); +} + +IL_LIFTER_IMPL(RETLW) { + return SEQ2( + SET_W(U8(K)), + JMP(VTOS)); +} + +IL_LIFTER_IMPL(RETURN) { + return JMP(VTOS); +} + +IL_LIFTER_IMPL(RLF) { + return SEQ3( + SETL("_c", LOGAND(SHIFTR0(VRF, U8(7)), U8(1))), + SET_WF(LOGOR(SHIFTL0(VRF, U8(1)), VARL("_c"))), + SETGb(STATUS, C, NON_ZERO(VARL("_c")))); +} + +IL_LIFTER_IMPL(RRF) { + return SEQ3( + SETL("_c", LOGAND(VRF, U8(1))), + SET_WF(LOGOR(SHIFTR0(VRF, U8(1)), SHIFTL0(VARL("_c"), U8(7)))), + SETGb(STATUS, C, NON_ZERO(VARL("_c")))); +} + +IL_LIFTER_IMPL(SLEEP) { + return NOP(); +} + +IL_LIFTER_IMPL(SUBLW) { + return SEQ4( + SETL("_w", VRW), + SETL("_res", SUB(U8(K), VARL("_w"))), + SET_W(VARL("_res")), + SET_STATUS_SUB(ctx, U8(K), VARL("_w"), VARL("_res"))); +} + +IL_LIFTER_IMPL(SUBWF) { + return SEQ5( + SETL("_f", VRF), + SETL("_w", VRW), + SETL("_res", SUB(VARL("_f"), VARL("_w"))), + SET_WF(VARL("_res")), + SET_STATUS_SUB(ctx, VARL("_f"), VARL("_w"), VARL("_res"))); +} + +IL_LIFTER_IMPL(SWAPF) { + return SET_WF(APPEND(UNSIGNED(4, VRF), UNSIGNED(4, SHIFTR0(VRF, U8(4))))); +} + +IL_LIFTER_IMPL(TRIS) { + // TODO: TRIS register f; + return SETG("tris", VRW); +} + +/** + * XORLW. + * Operation: Take logical XOR between literal and wreg + * Operands: Literal (k) + * Status affected : Z + * */ +IL_LIFTER_IMPL(XORLW) { + return SEQ2( + SET_W(LOGXOR(VRW, U8(K))), + SETGb(STATUS, Z, IS_ZERO(VRW))); +} + +/** + * ANDWF + * Operation: Take logical AND of freg and wreg. + * Operands: f, d + * Status affected : Z + * */ +IL_LIFTER_IMPL(XORWF) { + return SEQ3( + SETL("_res", LOGXOR(VRW, VRF)), + SET_WF(VARL("_res")), + SETZ(VARL("_res"))); +} + +IL_LIFTER_IMPL(RESET) { + return SEQ2( + reset(), + JMP(U16(0))); +} +IL_LIFTER_IMPL(CALLW) { + return SEQ2( + SET_TOS(U16(PC + INS_LEN)), + JMP(LOGOR(U16(K), UNSIGNED(16, VRW)))); +} +IL_LIFTER_IMPL(BRW) { + return JMP(ADD(UNSIGNED(16, VRW), SHIFTR0(U16(PC + INS_LEN), U16(1)))); +} +IL_LIFTER_IMPL(MOVIW_1) { + switch (ctx->x->instr & 0b11) { + case 0x0: return SEQ3( + set_fsrn(N, ADD(val_fsrn(N), U16(1))), + SET_W(LOAD(val_fsrn(N))), + SETZ(VRW)); + case 0x1: return SEQ3( + set_fsrn(N, SUB(val_fsrn(N), U16(1))), + SET_W(LOAD(val_fsrn(N))), + SETZ(VRW)); + case 0x2: return SEQ3( + SET_W(LOAD(val_fsrn(N))), + set_fsrn(N, ADD(val_fsrn(N), U16(1))), + SETZ(VRW)); + case 0x3: return SEQ3( + SET_W(LOAD(val_fsrn(N))), + set_fsrn(N, SUB(val_fsrn(N), U16(1))), + SETZ(VRW)); + default: break; + } + return NULL; +} +IL_LIFTER_IMPL(MOVIW_2) { + return SEQ2( + SET_W(LOAD(ADD(val_fsrn(N), S16(K)))), + SETZ(VRW)); +} + +IL_LIFTER_IMPL(MOVWI_1) { + return STORE(val_fsrn(N), VRW); +} +IL_LIFTER_IMPL(MOVWI_2) { + return STORE(ADD(val_fsrn(N), S16(K)), VRW); +} + +IL_LIFTER_IMPL(MOVLB) { + // imm5? + return SETGi(BSR, U8(K)); +} +IL_LIFTER_IMPL(MOVLP) { + // imm7? + return SETGi(PCLATH, U8(K)); +} + +IL_LIFTER_IMPL(LSLF) { + return SEQ3( + SETGb(STATUS, C, MSB(VRF)), + SET_WF(SHIFTL0(VRF, U8(1))), + SETZ(VRWF)); +} +IL_LIFTER_IMPL(LSRF) { + return SEQ3( + SETGb(STATUS, C, LSB(VRF)), + SET_WF(SHIFTR0(VRF, U8(1))), + SETZ(VRWF)); +} +IL_LIFTER_IMPL(ASRF) { + return SEQ3( + SETGb(STATUS, C, LSB(VRF)), + SET_WF(SHIFTRA(VRF, U8(1))), + SETZ(VRWF)); +} +IL_LIFTER_IMPL(SUBWFB) { + return SEQ3( + SETL("_res", ADD(SUB(VRF, VRW), BOOL_TO_BV(VARGb(STATUS, C), 8))), + SET_STATUS_SUB(ctx, VRF, VRW, VARL("_res")), + SET_WF(VARL("_res"))); +} +IL_LIFTER_IMPL(ADDWFC) { + return SEQ3( + SETL("_res", ADD(ADD(VRF, VRW), BOOL_TO_BV(VARGb(STATUS, C), 8))), + SET_STATUS_ADD(ctx, VRF, VRW, VARL("_res")), + SET_WF(VARL("_res"))); +} +IL_LIFTER_IMPL(ADDFSR) { + return set_fsrn(N, ADD(val_fsrn(N), S16(K))); +} +IL_LIFTER_IMPL(BRA) { + return JMP(U16(PC + K)); +} + +#undef K +#undef D +#undef F +#undef B +#undef N +#undef PC +#undef VPC + +#undef RW +#undef VRW +#undef RF +#undef VRF +#undef RWF +#undef VRWF + +const char *pic16_reg_bindings[] = { + "tris", + "_bank", + NULL, +}; + +/** + * \brief Returns IL VM config for given PIC Mid-Range device type. + * + * \param analysis \c RzAnalysis instance. + * \param device_type Device type in PIC16F family. + * + * \return valid ptr to RzAnalysisILConfig on success, NULL otherwise. + * */ +RzAnalysisILConfig *pic16_il_config( + RZ_NONNULL RzAnalysis *analysis) { + RzAnalysisILConfig *cfg = rz_analysis_il_config_new(16, false, 16); + cfg->reg_bindings = pic16_reg_bindings; + return cfg; +} \ No newline at end of file diff --git a/librz/arch/isa/pic/pic18.c b/librz/arch/isa/pic/pic18.c new file mode 100644 index 00000000000..539615aa4ae --- /dev/null +++ b/librz/arch/isa/pic/pic18.c @@ -0,0 +1,608 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-License-Identifier: LGPL-3.0-only + +#include + +#include "pic18.h" + +/** + * \file PIC18CXXX instruction set + */ + +// instruction classification according to the argument types + +static char *fsr[] = { "fsr0", "fsr1", "fsr2" }; + +typedef struct { + Pic18Opcode code; + ut16 opmin; + ut16 opmax; + const char *name; + Pic18ArgsKind optype; + // and some magical hocus pocus ;) +} Pic18OpDesc; + +static const Pic18OpDesc pic18_ops[] = { + { PIC18_OPCODE_NOP, 0xf000, 0xffff, "nop", NO_ARG }, + { PIC18_OPCODE_GOTO, 0xef00, 0xefff, "goto", K20_T }, + { PIC18_OPCODE_LFSR, 0xee00, 0xee3f, "lfsr", FK_T }, + { PIC18_OPCODE_CALL, 0xec00, 0xedff, "call", K20S_T }, + { PIC18_OPCODE_BNN, 0xe700, 0xe7ff, "bnn", N8_T }, + { PIC18_OPCODE_BN, 0xe600, 0xe6ff, "bn", N8_T }, + { PIC18_OPCODE_BNOV, 0xe500, 0xe5ff, "bnov", N8_T }, + { PIC18_OPCODE_BOV, 0xe400, 0xe4ff, "bov", N8_T }, + { PIC18_OPCODE_BNC, 0xe300, 0xe3ff, "bnc", N8_T }, + { PIC18_OPCODE_BC, 0xe200, 0xe2ff, "bc", N8_T }, + { PIC18_OPCODE_BNZ, 0xe100, 0xe1ff, "bnz", N8_T }, + { PIC18_OPCODE_BZ, 0xe000, 0xe0ff, "bz", N8_T }, + { PIC18_OPCODE_RCALL, 0xd800, 0xdfff, "rcall", N11_T }, + { PIC18_OPCODE_BRA, 0xd000, 0xd7ff, "bra", N11_T }, + { PIC18_OPCODE_MOVFF, 0xc000, 0xcfff, "movff", SD_T }, + { PIC18_OPCODE_BTFSC, 0xb000, 0xbfff, "btfsc", FBA_T }, + { PIC18_OPCODE_BTFSS, 0xa000, 0xafff, "btfss", FBA_T }, + { PIC18_OPCODE_BCF, 0x9000, 0x9fff, "bcf", FBA_T }, + { PIC18_OPCODE_BSF, 0x8000, 0x8fff, "bsf", FBA_T }, + { PIC18_OPCODE_BTG, 0x7000, 0x7fff, "btg", FBA_T }, + { PIC18_OPCODE_MOVWF, 0x6e00, 0x6fff, "movwf", FA_T }, + { PIC18_OPCODE_NEGF, 0x6c00, 0x6dff, "negf", FA_T }, + { PIC18_OPCODE_CLRF, 0x6a00, 0x6bff, "clrf", FA_T }, + { PIC18_OPCODE_SETF, 0x6800, 0x69ff, "setf", FA_T }, + { PIC18_OPCODE_TSTFSZ, 0x6600, 0x67ff, "tstfsz", FA_T }, + { PIC18_OPCODE_CPFSGT, 0x6400, 0x65ff, "cpfsgt", FA_T }, + { PIC18_OPCODE_CPFSEQ, 0x6200, 0x63ff, "cpfseq", FA_T }, + { PIC18_OPCODE_CPFSLT, 0x6000, 0x61ff, "cpfslt", FA_T }, + { PIC18_OPCODE_SUBWF, 0x5c00, 0x5fff, "subwf", FDA_T }, + { PIC18_OPCODE_SUBWFB, 0x5800, 0x5bff, "subwfb", FDA_T }, + { PIC18_OPCODE_SUBFWB, 0x5400, 0x57ff, "subfwb", FDA_T }, + { PIC18_OPCODE_MOVF, 0x5000, 0x53ff, "movf", FDA_T }, + { PIC18_OPCODE_DCFSNZ, 0x4c00, 0x4fff, "dcfsnz", FDA_T }, + { PIC18_OPCODE_INFSNZ, 0x4800, 0x4bff, "infsnz", FDA_T }, + { PIC18_OPCODE_RLNCF, 0x4400, 0x47ff, "rlncf", FDA_T }, + { PIC18_OPCODE_RRNCF, 0x4000, 0x43ff, "rrncf", FDA_T }, + { PIC18_OPCODE_INCFSZ, 0x3c00, 0x3fff, "incfsz", FDA_T }, + { PIC18_OPCODE_SWAPF, 0x3800, 0x3bff, "swapf", FDA_T }, + { PIC18_OPCODE_RLCF, 0x3400, 0x37ff, "rlcf", FDA_T }, + { PIC18_OPCODE_RRCF, 0x3000, 0x33ff, "rrcf", FDA_T }, + { PIC18_OPCODE_DECFSZ, 0x2c00, 0x2fff, "decfsz", FDA_T }, + { PIC18_OPCODE_INCF, 0x2800, 0x2bff, "incf", FDA_T }, + { PIC18_OPCODE_ADDWF, 0x2400, 0x27ff, "addwf", FDA_T }, + { PIC18_OPCODE_ADDWFC, 0x2000, 0x23ff, "addwfc", FDA_T }, + { PIC18_OPCODE_COMF, 0x1c00, 0x1fff, "comf", FDA_T }, + { PIC18_OPCODE_XORWF, 0x1800, 0x1bff, "xorwf", FDA_T }, + { PIC18_OPCODE_ANDWF, 0x1400, 0x17ff, "andwf", FDA_T }, + { PIC18_OPCODE_IORWF, 0x1000, 0x13ff, "iorwf", FDA_T }, + { PIC18_OPCODE_ADDLW, 0xf00, 0xfff, "addlw", K8_T }, + { PIC18_OPCODE_MOVLW, 0xe00, 0xeff, "movlw", K8_T }, + { PIC18_OPCODE_MULLW, 0xd00, 0xdff, "mullw", K8_T }, + { PIC18_OPCODE_RETLW, 0xc00, 0xcff, "retlw", K8_T }, + { PIC18_OPCODE_ANDLW, 0xb00, 0xbff, "andlw", K8_T }, + { PIC18_OPCODE_XORLW, 0xa00, 0xaff, "xorlw", K8_T }, + { PIC18_OPCODE_IORLW, 0x900, 0x9ff, "iorlw", K8_T }, + { PIC18_OPCODE_SUBLW, 0x800, 0x8ff, "sublw", K8_T }, + { PIC18_OPCODE_DECF, 0x400, 0x7ff, "decf", FDA_T }, + { PIC18_OPCODE_MULWF, 0x200, 0x3ff, "mulwf", FA_T }, + { PIC18_OPCODE_MOVLB, 0x100, 0x10f, "movlb", K4_T }, + { PIC18_OPCODE_RESET, 0xff, 0xff, "reset", NO_ARG }, + { PIC18_OPCODE_RETURN, 0x12, 0x13, "return", S_T }, + { PIC18_OPCODE_RETFIE, 0x10, 0x11, "retfie", S_T }, + { PIC18_OPCODE_TBLWTis, 0xf, 0xf, "tblwt+*", NO_ARG }, + { PIC18_OPCODE_TBLWTMsd, 0xe, 0xe, "tblwt*-", NO_ARG }, + { PIC18_OPCODE_TBLWTMsi, 0xd, 0xd, "tblwt*+", NO_ARG }, + { PIC18_OPCODE_TBLWTMs, 0xc, 0xc, "tblwt*", NO_ARG }, + { PIC18_OPCODE_TBLRDis, 0xb, 0xb, "tblrd+*", NO_ARG }, + { PIC18_OPCODE_TBLRDsd, 0xa, 0xa, "tblrd*-", NO_ARG }, + { PIC18_OPCODE_TBLRDsi, 0x9, 0x9, "tblrd*+", NO_ARG }, + { PIC18_OPCODE_TBLRDs, 0x8, 0x8, "tblrd*", NO_ARG }, + { PIC18_OPCODE_DAW, 0x7, 0x7, "daw", NO_ARG }, + { PIC18_OPCODE_POP, 0x6, 0x6, "pop", NO_ARG }, + { PIC18_OPCODE_PUSH, 0x5, 0x5, "push", NO_ARG }, + { PIC18_OPCODE_CLRWDT, 0x4, 0x4, "clrwdt", NO_ARG }, + { PIC18_OPCODE_SLEEP, 0x3, 0x3, "sleep", NO_ARG }, + { PIC18_OPCODE_NOP, 0x0, 0x0, "nop", NO_ARG }, +}; + +static const char *pic18_SFRs[] = { + [0xFFF - 0xF80] = "tosu", + [0xFFE - 0xF80] = "tosh", + [0xFFD - 0xF80] = "tosl", + [0xFFC - 0xF80] = "stkptr", + [0xFFB - 0xF80] = "pclatu", + [0xFFA - 0xF80] = "pclath", + [0xFF9 - 0xF80] = "pcl", + [0xFF8 - 0xF80] = "tblptru", + [0xFF7 - 0xF80] = "tblptrh", + [0xFF6 - 0xF80] = "tblptrl", + [0xFF5 - 0xF80] = "tablat", + [0xFF4 - 0xF80] = "prodh", + [0xFF3 - 0xF80] = "prodl", + [0xFF2 - 0xF80] = "intcon", + [0xFF1 - 0xF80] = "intcon2", + [0xFF0 - 0xF80] = "intcon3", + [0xFEF - 0xF80] = "indf0", + [0xFEE - 0xF80] = "postinc0", + [0xFED - 0xF80] = "postdec0", + [0xFEC - 0xF80] = "preinc0", + [0xFEB - 0xF80] = "plusw0", + [0xFEA - 0xF80] = "fsr0h", + [0xFE9 - 0xF80] = "fsr0l", + [0xFE8 - 0xF80] = "wreg", + [0xFE7 - 0xF80] = "indf1", + [0xFE6 - 0xF80] = "postinc1", + [0xFE5 - 0xF80] = "postdec1", + [0xFE4 - 0xF80] = "preinc1", + [0xFE3 - 0xF80] = "plusw1", + [0xFE2 - 0xF80] = "fsr1h", + [0xFE1 - 0xF80] = "fsr1l", + [0xFE0 - 0xF80] = "bsr", + [0xFDF - 0xF80] = "indf2", + [0xFDE - 0xF80] = "postinc2", + [0xFDD - 0xF80] = "postdec2", + [0xFDC - 0xF80] = "preinc2", + [0xFDB - 0xF80] = "plusw2", + [0xFDA - 0xF80] = "fsr2h", + [0xFD9 - 0xF80] = "fsr2l", + [0xFD8 - 0xF80] = "status", + [0xFD7 - 0xF80] = "tmr0h", + [0xFD6 - 0xF80] = "tmr0l", + [0xFD5 - 0xF80] = "t0con", + [0xFD4 - 0xF80] = "0xd4", + [0xFD3 - 0xF80] = "osccon", + [0xFD2 - 0xF80] = "lvdcon", + [0xFD1 - 0xF80] = "wdtcon", + [0xFD0 - 0xF80] = "rcon", + [0xFCF - 0xF80] = "tmr1h", + [0xFCE - 0xF80] = "tmr1l", + [0xFCD - 0xF80] = "t1con", + [0xFCC - 0xF80] = "tmr2", + [0xFCB - 0xF80] = "pr2", + [0xFCA - 0xF80] = "t2con", + [0xFC9 - 0xF80] = "sspbuf", + [0xFC8 - 0xF80] = "sspadd", + [0xFC7 - 0xF80] = "sspstat", + [0xFC6 - 0xF80] = "sspcon1", + [0xFC5 - 0xF80] = "sspcon2", + [0xFC4 - 0xF80] = "adresh", + [0xFC3 - 0xF80] = "adresl", + [0xFC2 - 0xF80] = "adcon0", + [0xFC1 - 0xF80] = "adcon1", + [0xFC0 - 0xF80] = "0xc0", + [0xFBF - 0xF80] = "ccpr1h", + [0xFBE - 0xF80] = "ccpr1l", + [0xFBD - 0xF80] = "ccp1con", + [0xFBC - 0xF80] = "ccpr2h", + [0xFBB - 0xF80] = "ccpr2l", + [0xFBA - 0xF80] = "ccp2con", + [0xFB9 - 0xF80] = "0xb9", + [0xFB8 - 0xF80] = "0xb8", + [0xFB7 - 0xF80] = "0xb7", + [0xFB6 - 0xF80] = "0xb6", + [0xFB5 - 0xF80] = "0xb5", + [0xFB4 - 0xF80] = "0xb4", + [0xFB3 - 0xF80] = "tmr3h", + [0xFB2 - 0xF80] = "tmr3l", + [0xFB1 - 0xF80] = "t3con", + [0xFB0 - 0xF80] = "0xb0", + [0xFAF - 0xF80] = "spbrg", + [0xFAE - 0xF80] = "rcreg", + [0xFAD - 0xF80] = "txreg", + [0xFAC - 0xF80] = "txsta", + [0xFAB - 0xF80] = "rcsta", + [0xFAA - 0xF80] = "0xaa", + [0xFA9 - 0xF80] = "0xa9", + [0xFA8 - 0xF80] = "0xa8", + [0xFA7 - 0xF80] = "0xa7", + [0xFA6 - 0xF80] = "0xa6", + [0xFA5 - 0xF80] = "0xa5", + [0xFA4 - 0xF80] = "0xa4", + [0xFA3 - 0xF80] = "0xa3", + [0xFA2 - 0xF80] = "ipr2", + [0xFA1 - 0xF80] = "pir2", + [0xFA0 - 0xF80] = "pie2", + [0xF9F - 0xF80] = "ipr1", + [0xF9E - 0xF80] = "pir1", + [0xF9D - 0xF80] = "pie1", + [0xF9C - 0xF80] = "0x9c", + [0xF9B - 0xF80] = "0x9b", + [0xF9A - 0xF80] = "0x9a", + [0xF99 - 0xF80] = "0x99", + [0xF98 - 0xF80] = "0x98", + [0xF97 - 0xF80] = "0x97", + [0xF96 - 0xF80] = "trise", + [0xF95 - 0xF80] = "trisd", + [0xF94 - 0xF80] = "trisc", + [0xF93 - 0xF80] = "trisb", + [0xF92 - 0xF80] = "trisa", + [0xF91 - 0xF80] = "0x91", + [0xF90 - 0xF80] = "0x90", + [0xF8F - 0xF80] = "0x8f", + [0xF8E - 0xF80] = "0x8e", + [0xF8D - 0xF80] = "late", + [0xF8C - 0xF80] = "latd", + [0xF8B - 0xF80] = "latc", + [0xF8A - 0xF80] = "latb", + [0xF89 - 0xF80] = "lata", + [0xF88 - 0xF80] = "0x88", + [0xF87 - 0xF80] = "0x87", + [0xF86 - 0xF80] = "0x86", + [0xF85 - 0xF80] = "0x85", + [0xF84 - 0xF80] = "porte", + [0xF83 - 0xF80] = "portd", + [0xF82 - 0xF80] = "portc", + [0xF81 - 0xF80] = "portb", + [0xF80 - 0xF80] = "porta", +}; + +static const char *pic18_GPRs[] = { + "0x00", + "0x01", + "0x02", + "0x03", + "0x04", + "0x05", + "0x06", + "0x07", + "0x08", + "0x09", + "0x0a", + "0x0b", + "0x0c", + "0x0d", + "0x0e", + "0x0f", + "0x10", + "0x11", + "0x12", + "0x13", + "0x14", + "0x15", + "0x16", + "0x17", + "0x18", + "0x19", + "0x1a", + "0x1b", + "0x1c", + "0x1d", + "0x1e", + "0x1f", + "0x20", + "0x21", + "0x22", + "0x23", + "0x24", + "0x25", + "0x26", + "0x27", + "0x28", + "0x29", + "0x2a", + "0x2b", + "0x2c", + "0x2d", + "0x2e", + "0x2f", + "0x30", + "0x31", + "0x32", + "0x33", + "0x34", + "0x35", + "0x36", + "0x37", + "0x38", + "0x39", + "0x3a", + "0x3b", + "0x3c", + "0x3d", + "0x3e", + "0x3f", + "0x40", + "0x41", + "0x42", + "0x43", + "0x44", + "0x45", + "0x46", + "0x47", + "0x48", + "0x49", + "0x4a", + "0x4b", + "0x4c", + "0x4d", + "0x4e", + "0x4f", + "0x50", + "0x51", + "0x52", + "0x53", + "0x54", + "0x55", + "0x56", + "0x57", + "0x58", + "0x59", + "0x5a", + "0x5b", + "0x5c", + "0x5d", + "0x5e", + "0x5f", + "0x60", + "0x61", + "0x62", + "0x63", + "0x64", + "0x65", + "0x66", + "0x67", + "0x68", + "0x69", + "0x6a", + "0x6b", + "0x6c", + "0x6d", + "0x6e", + "0x6f", + "0x70", + "0x71", + "0x72", + "0x73", + "0x74", + "0x75", + "0x76", + "0x77", + "0x78", + "0x79", + "0x7a", + "0x7b", + "0x7c", + "0x7d", + "0x7e", + "0x7f" +}; + +const char *pic18_regname(size_t index) { + if (index <= 0xff && index >= 0x80) { + return pic18_SFRs[index - 0x80]; + } + if (index < 0x80) { + return pic18_GPRs[index]; + } + rz_warn_if_reached(); + return NULL; +} + +const char *pic18_regname_extra(size_t index) { + if (index <= 0xff) { + return pic18_regname(index); + } + if (index >= 0xf80 && index <= 0xfff) { + return pic18_regname(index % 0x100); + } + return NULL; +} + +#define STATUS_BIT_IMPL(DECL, X) \ + ut8 pic18_##X(const char *name) { \ + for (int i = 0; i < RZ_ARRAY_SIZE(DECL); ++i) { \ + if (RZ_STR_EQ(name, DECL[i])) { \ + return i; \ + } \ + } \ + return 0xff; \ + } + +static const char *status_bits[] = { + "c", + "dc", + "z", + "ov", + "n" +}; + +static const char *rcon_bits[] = { + "bor", + "por", + "pd", + "to", + "ri", + NULL, + "lwrt", + "ipen", +}; + +static const char *intcon_bits[] = { + "brif", + "int0if", + "tmr0if", + "brie", + "int0ie", + "tmr0ie", + "peie", + "gie", +}; + +STATUS_BIT_IMPL(status_bits, status); +STATUS_BIT_IMPL(rcon_bits, rcon); +ut8 pic18_intcon(const char *name) { + for (int i = 0; i < RZ_ARRAY_SIZE(intcon_bits); ++i) { + if (RZ_STR_EQ(name, intcon_bits[i])) { + return i; + } + } + if (RZ_STR_EQ(name, "gieh")) { + return 7; + } + if (RZ_STR_EQ(name, "giel")) { + return 6; + } + return 0xff; +} + +static const Pic18OpDesc *pic18_get_op_desc(ut16 word) { + for (Pic18OpDesc *desc = (Pic18OpDesc *)pic18_ops; + desc - pic18_ops < RZ_ARRAY_SIZE(pic18_ops); + desc++) { + if (desc->opmin == (desc->opmin & word) && desc->opmax == (desc->opmax | word)) { + return desc; + } + } + return NULL; +} + +bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len) { +#define check_len(x) \ + if (len < x) { \ + op->code = PIC18_OPCODE_INVALID; \ + return false; \ + } \ + op->size = x; + + op->addr = addr; + check_len(2); + ut16 word = rz_read_le16(buff); + const Pic18OpDesc *desc = pic18_get_op_desc(word); + if (!desc) { + return false; + } + + op->code = desc->code; + op->mnemonic = desc->name; + op->args_kind = desc->optype; + + switch (op->args_kind) { + case N8_T: + op->n = word & 0xff; + break; + case K8_T: + op->k = word & 0xff; + break; + case FDA_T: + op->f = word & 0xff; + op->d = (word >> 9) & 1; + op->a = (word >> 8) & 1; + break; + case FA_T: + op->f = word & 0xff; + op->a = (word >> 8) & 1; + break; + case FBA_T: + op->f = word & 0xff; + op->a = (word >> 8) & 1; + op->b = (word >> 9) & 0x7; + break; + case N11_T: + op->n = word & 0x7ff; + break; + case K4_T: + op->k = word & 0xf; + break; + case S_T: + op->s = word & 0x1; + break; +#define check_dword_inst \ + check_len(4); \ + ut32 dword = rz_read_le32(buff); \ + if (dword >> 28 != 0xf) { \ + return false; \ + } + + case K20S_T: { + check_dword_inst; + op->k = (dword & 0xff) | ((dword >> 16 & 0xfff) << 8); + op->s = (dword >> 8) & 0x1; + break; + } + case K20_T: { + check_dword_inst; + op->k = (dword & 0xff) | ((dword >> 16 & 0xfff) << 8); + break; + } + case SD_T: { + check_dword_inst; + op->s = dword & 0xfff; + op->d = (dword >> 16) & 0xfff; + break; + } + case FK_T: { + check_dword_inst; + op->f = (dword >> 4) & 0x3; + op->k = (dword & 0xf) << 8 | ((dword >> 16) & 0xff); + break; + } + default: + break; + } + + switch (op->args_kind) { + case NO_ARG: + default: + break; + case N8_T: + case N11_T: + rz_strf(op->operands, "0x%x", op->n); + break; + case K4_T: + case K8_T: + rz_strf(op->operands, "0x%x", op->k); + break; + case K20_T: + rz_strf(op->operands, "0x%x", op->k << 1); + break; + case FDA_T: + rz_strf(op->operands, "%s, %d, %d", pic18_regname(op->f), op->d, op->a); + break; + case FA_T: + rz_strf(op->operands, "%s, %d", pic18_regname(op->f), op->a); + break; + case FBA_T: + rz_strf(op->operands, "%s, %d, %d", pic18_regname(op->f), op->b, op->a); + break; + case K20S_T: + rz_strf(op->operands, "0x%x, %d", op->k << 1, op->s); + break; + case SD_T: { + const char *rs = pic18_regname_extra(op->s); + const char *rd = pic18_regname_extra(op->d); + if (rs && rd) { + rz_strf(op->operands, "%s, %s", rs, rd); + } else if (rs) { + rz_strf(op->operands, "%s, 0x%x", rs, op->d); + } else if (rd) { + rz_strf(op->operands, "0x%x, %s", op->s, rd); + } else { + rz_strf(op->operands, "0x%x, 0x%x", op->s, op->d); + } + break; + } + case S_T: + rz_strf(op->operands, "%d", op->s); + break; + case FK_T: { + rz_strf(op->operands, "%s, %d", fsr[op->f], op->k); + break; + } + } + + return true; +} + +int pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int blen) { + asm_op->size = 2; + Pic18Op op = { 0 }; + if (!pic18_disasm_op(&op, a->pc, b, blen) || + op.code == PIC18_OPCODE_INVALID) { + rz_asm_op_set_asm(asm_op, "invalid"); + return -1; + } + asm_op->size = op.size; + if (RZ_STR_ISEMPTY(op.operands)) { + rz_asm_op_set_asm(asm_op, op.mnemonic); + } else { + rz_asm_op_setf_asm(asm_op, "%s %s", op.mnemonic, op.operands); + } + return asm_op->size; +} diff --git a/librz/arch/isa/pic/pic18.h b/librz/arch/isa/pic/pic18.h new file mode 100644 index 00000000000..fcada62d806 --- /dev/null +++ b/librz/arch/isa/pic/pic18.h @@ -0,0 +1,157 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef PIC_PIC18_H +#define PIC_PIC18_H + +#include +#include "pic.h" + +static inline bool is_pic18(const char *x) { + return RZ_STR_EQ(x, "highend") || + RZ_STR_EQ(x, "pic") || + RZ_STR_EQ(x, "pic18"); +} + +typedef enum { + PIC18_OPCODE_ADDLW, + PIC18_OPCODE_ADDWF, + PIC18_OPCODE_ADDWFC, + PIC18_OPCODE_ANDWF, + PIC18_OPCODE_ANDLW, + + PIC18_OPCODE_BCF, + PIC18_OPCODE_BSF, + PIC18_OPCODE_BTG, + PIC18_OPCODE_BTFSC, + PIC18_OPCODE_BTFSS, + PIC18_OPCODE_BNN, + PIC18_OPCODE_BN, + PIC18_OPCODE_BNOV, + PIC18_OPCODE_BOV, + PIC18_OPCODE_BNC, + PIC18_OPCODE_BC, + PIC18_OPCODE_BNZ, + PIC18_OPCODE_BZ, + PIC18_OPCODE_BRA, + + PIC18_OPCODE_COMF, + PIC18_OPCODE_CALL, + PIC18_OPCODE_CLRWDT, + PIC18_OPCODE_CLRF, + PIC18_OPCODE_CPFSGT, + PIC18_OPCODE_CPFSEQ, + PIC18_OPCODE_CPFSLT, + + PIC18_OPCODE_DAW, + PIC18_OPCODE_DECF, + PIC18_OPCODE_DECFSZ, + PIC18_OPCODE_DCFSNZ, + + PIC18_OPCODE_GOTO, + + PIC18_OPCODE_IORWF, + PIC18_OPCODE_INFSNZ, + PIC18_OPCODE_INCF, + PIC18_OPCODE_INCFSZ, + PIC18_OPCODE_IORLW, + + PIC18_OPCODE_LFSR, + + PIC18_OPCODE_MOVF, + PIC18_OPCODE_MOVWF, + PIC18_OPCODE_MULWF, + PIC18_OPCODE_MOVLB, + PIC18_OPCODE_MOVFF, + PIC18_OPCODE_MOVLW, + PIC18_OPCODE_MULLW, + + PIC18_OPCODE_NOP, + PIC18_OPCODE_NEGF, + + PIC18_OPCODE_POP, + PIC18_OPCODE_PUSH, + + PIC18_OPCODE_RETURN, + PIC18_OPCODE_RETFIE, + PIC18_OPCODE_RLNCF, + PIC18_OPCODE_RRNCF, + PIC18_OPCODE_RLCF, + PIC18_OPCODE_RRCF, + PIC18_OPCODE_RCALL, + PIC18_OPCODE_RESET, + PIC18_OPCODE_RETLW, + + PIC18_OPCODE_SLEEP, + PIC18_OPCODE_SETF, + PIC18_OPCODE_SUBWF, + PIC18_OPCODE_SUBWFB, + PIC18_OPCODE_SUBFWB, + PIC18_OPCODE_SWAPF, + PIC18_OPCODE_SUBLW, + + PIC18_OPCODE_TBLRDs, + PIC18_OPCODE_TBLRDis, + PIC18_OPCODE_TBLRDsd, + PIC18_OPCODE_TBLRDsi, + PIC18_OPCODE_TBLWTMs, + PIC18_OPCODE_TBLWTis, + PIC18_OPCODE_TBLWTMsd, + PIC18_OPCODE_TBLWTMsi, + PIC18_OPCODE_TSTFSZ, + + PIC18_OPCODE_XORWF, + PIC18_OPCODE_XORLW, + + PIC18_OPCODE_INVALID +} Pic18Opcode; + +typedef enum { + NO_ARG, + FDA_T, + SD_T, + FBA_T, + K4_T, + K8_T, + K20_T, + K20S_T, + S_T, + N8_T, + N11_T, + FA_T, + FK_T, +} Pic18ArgsKind; + +typedef struct { + ut64 addr; + Pic18Opcode code; + const char *mnemonic; + char operands[32]; + ut8 size; + Pic18ArgsKind args_kind; + struct { + ut32 k : 20; + ut16 n : 11; + ut16 d; + ut16 s; + ut8 f; + ut8 a : 1; + ut8 b : 3; + }; +} Pic18Op; + +const char *pic18_regname(size_t index); +const char *pic18_regname_extra(size_t index); +ut8 pic18_status(const char *name); +ut8 pic18_rcon(const char *name); +ut8 pic18_intcon(const char *name); +bool pic18_disasm_op(Pic18Op *op, ut64 addr, const ut8 *buff, ut64 len); +int pic18_disassemble(RzAsm *a, RzAsmOp *asm_op, const ut8 *b, int l); + +int pic18_op(RzAnalysis *analysis, RzAnalysisOp *aop, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask); +char *pic18_get_reg_profile(RzAnalysis *esil); +RzAnalysisILConfig *pic18_il_config(RZ_NONNULL RzAnalysis *analysis); + +#endif // PIC_PIC18_H diff --git a/librz/arch/isa/pic/pic18_analysis.c b/librz/arch/isa/pic/pic18_analysis.c new file mode 100644 index 00000000000..28558dec955 --- /dev/null +++ b/librz/arch/isa/pic/pic18_analysis.c @@ -0,0 +1,382 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +#include "pic18.h" +#include "pic18_esil.inc" + +typedef struct { + enum { + ILOpEff_None, + ILOpEff_PostDec, + ILOpEff_PostInc, + ILOpEff_PreInc, + } tag; + char fsr[8]; +} ILOpEff; + +typedef struct { + const Pic18Op *op; + const HtSU *mm; + RzVector /**/ effs; +} Pic18ILContext; + +#include "pic18_il.inc" + +static void pic18_cond_branch(RzAnalysisOp *aop, Pic18Op *op) { + aop->type = RZ_ANALYSIS_OP_TYPE_CJMP; + aop->jump = op->addr + 2 + 2 * op->n; + aop->fail = op->addr + aop->size; + aop->cycles = 2; +} + +int pic18_op( + RzAnalysis *analysis, RzAnalysisOp *aop, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + + aop->size = 2; + Pic18Op op = { 0 }; + if (!pic18_disasm_op(&op, addr, buf, len)) { + goto err; + } + aop->size = op.size; + switch (op.code) { + case PIC18_OPCODE_CALL: + case PIC18_OPCODE_RCALL: + aop->type = RZ_ANALYSIS_OP_TYPE_CALL; + break; + case PIC18_OPCODE_BRA: // bra + aop->type = RZ_ANALYSIS_OP_TYPE_JMP; + aop->cycles = 2; + aop->jump = addr + 2 + 2 * (*(ut16 *)buf & 0x7ff); + break; + case PIC18_OPCODE_MOVFF: // movff + aop->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; + case PIC18_OPCODE_BTFSC: // btfsc + case PIC18_OPCODE_BTFSS: // btfss + aop->type = RZ_ANALYSIS_OP_TYPE_CJMP; + break; + case PIC18_OPCODE_BCF: // bcf + case PIC18_OPCODE_BSF: // bsf + case PIC18_OPCODE_BTG: // btg + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_BZ: // bz + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BNZ: // bnz + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BNC: // bnc + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BOV: // bov + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BNOV: // bnov + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BN: // bn + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BNN: // bnn + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_BC: // bc + pic18_cond_branch(aop, &op); + break; + case PIC18_OPCODE_GOTO: // goto + aop->cycles = 2; + aop->jump = op.k; + aop->type = RZ_ANALYSIS_OP_TYPE_JMP; + break; + case PIC18_OPCODE_ADDLW: // addlw + aop->type = RZ_ANALYSIS_OP_TYPE_ADD; + aop->cycles = 1; + break; + case PIC18_OPCODE_MOVLW: // movlw + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + aop->cycles = 1; + break; + case PIC18_OPCODE_MULLW: // mullw + aop->type = RZ_ANALYSIS_OP_TYPE_MUL; + aop->cycles = 1; + break; + case PIC18_OPCODE_RETLW: // retlw + aop->type = RZ_ANALYSIS_OP_TYPE_RET; + aop->cycles = 2; + break; + case PIC18_OPCODE_ANDLW: // andlw + aop->type = RZ_ANALYSIS_OP_TYPE_AND; + aop->cycles = 1; + break; + case PIC18_OPCODE_XORLW: // xorlw + aop->type = RZ_ANALYSIS_OP_TYPE_XOR; + aop->cycles = 1; + break; + case PIC18_OPCODE_IORLW: // iorlw + aop->type = RZ_ANALYSIS_OP_TYPE_OR; + aop->cycles = 1; + break; + case PIC18_OPCODE_SUBLW: // sublw + aop->type = RZ_ANALYSIS_OP_TYPE_SUB; + aop->cycles = 1; + break; + case PIC18_OPCODE_LFSR: // lfsr + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + break; + case PIC18_OPCODE_SUBWF: // subwf + case PIC18_OPCODE_SUBFWB: // subwfb + case PIC18_OPCODE_SUBWFB: // subfwb + case PIC18_OPCODE_DCFSNZ: // dcfsnz + case PIC18_OPCODE_DECFSZ: // decfsz + case PIC18_OPCODE_DECF: // decf + aop->type = RZ_ANALYSIS_OP_TYPE_SUB; + break; + case PIC18_OPCODE_MOVF: // movf + aop->type = RZ_ANALYSIS_OP_TYPE_MOV; + break; + case PIC18_OPCODE_INFSNZ: // infsnz + case PIC18_OPCODE_INCFSZ: // incfsz + case PIC18_OPCODE_INCF: // incf + case PIC18_OPCODE_ADDWFC: // addwfc + aop->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case PIC18_OPCODE_ADDWF: // addwf + aop->cycles = 1; + aop->type = RZ_ANALYSIS_OP_TYPE_ADD; + break; + case PIC18_OPCODE_RLNCF: // rlncf + case PIC18_OPCODE_RLCF: // rlcf + aop->type = RZ_ANALYSIS_OP_TYPE_ROL; + break; + case PIC18_OPCODE_RRNCF: // rrncf + case PIC18_OPCODE_RRCF: // rrcf + aop->type = RZ_ANALYSIS_OP_TYPE_ROR; + break; + case PIC18_OPCODE_SWAPF: // swapf + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_COMF: // comf + aop->type = RZ_ANALYSIS_OP_TYPE_CPL; + break; + case PIC18_OPCODE_XORWF: // xorwf + aop->type = RZ_ANALYSIS_OP_TYPE_XOR; + break; + case PIC18_OPCODE_ANDWF: // andwf + aop->type = RZ_ANALYSIS_OP_TYPE_AND; + break; + case PIC18_OPCODE_IORWF: // iorwf + aop->type = RZ_ANALYSIS_OP_TYPE_OR; + break; + case PIC18_OPCODE_MOVWF: // movwf + aop->type = RZ_ANALYSIS_OP_TYPE_STORE; + break; + case PIC18_OPCODE_NEGF: // negf + case PIC18_OPCODE_CLRF: // clrf + case PIC18_OPCODE_SETF: // setf + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_TSTFSZ: // tstfsz + aop->type = RZ_ANALYSIS_OP_TYPE_CJMP; + break; + case PIC18_OPCODE_CPFSGT: // cpfsgt + case PIC18_OPCODE_CPFSEQ: // cpfseq + case PIC18_OPCODE_CPFSLT: // cpfslt + aop->type = RZ_ANALYSIS_OP_TYPE_CMP; + break; + case PIC18_OPCODE_MULWF: // mulwf + aop->type = RZ_ANALYSIS_OP_TYPE_MUL; + break; + case PIC18_OPCODE_MOVLB: // movlb + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + aop->cycles = 1; + break; + case PIC18_OPCODE_RESET: // reset + case PIC18_OPCODE_DAW: // daw + // case CLWDT // clwdt + case PIC18_OPCODE_SLEEP: // sleep + aop->type = RZ_ANALYSIS_OP_TYPE_UNK; + break; + case PIC18_OPCODE_RETURN: // return + aop->type = RZ_ANALYSIS_OP_TYPE_RET; + aop->cycles = 2; + break; + case PIC18_OPCODE_RETFIE: // retfie + aop->type = RZ_ANALYSIS_OP_TYPE_RET; + break; + case PIC18_OPCODE_TBLWTMs: // tblwt + case PIC18_OPCODE_TBLWTMsi: // tblwt + case PIC18_OPCODE_TBLWTis: // tblwt + case PIC18_OPCODE_TBLWTMsd: // tblwt + aop->type = RZ_ANALYSIS_OP_TYPE_LOAD; + break; + case PIC18_OPCODE_TBLRDis: // tblrd + case PIC18_OPCODE_TBLRDs: // tblrd + case PIC18_OPCODE_TBLRDsi: // tblrd + case PIC18_OPCODE_TBLRDsd: // tblrd + aop->type = RZ_ANALYSIS_OP_TYPE_STORE; + break; + case PIC18_OPCODE_POP: // pop + aop->type = RZ_ANALYSIS_OP_TYPE_POP; + break; + case PIC18_OPCODE_PUSH: // push + aop->type = RZ_ANALYSIS_OP_TYPE_PUSH; + break; + case PIC18_OPCODE_NOP: // nop + aop->type = RZ_ANALYSIS_OP_TYPE_NOP; + aop->cycles = 1; + break; + default: + goto err; + } + + if (mask & RZ_ANALYSIS_OP_MASK_ESIL) { + pic18_esil(aop, &op, addr, buf); + } + + if (mask & RZ_ANALYSIS_OP_MASK_IL) { + Pic18ILContext ctx = { + .op = &op, + .mm = ((PicContext *)analysis->plugin_data)->pic18_mm, + }; + rz_vector_init(&ctx.effs, sizeof(ILOpEff), NULL, NULL); + aop->il_op = pic18_il_op_finally(&ctx); + rz_vector_fini(&ctx.effs); + } + + if (mask & RZ_ANALYSIS_OP_MASK_DISASM) { + aop->mnemonic = rz_str_newf("%s%s%s", op.mnemonic, RZ_STR_ISEMPTY(op.operands) ? "" : " ", op.operands); + } + + return aop->size; +err: + aop->type = RZ_ANALYSIS_OP_TYPE_ILL; + return aop->size; +} + +char *pic18_get_reg_profile(RzAnalysis *esil) { + const char *p = + "#pc lives in nowhere actually\n" + "=PC pc\n" + "=SP tos\n" + "=A0 porta\n" + "=A1 portb\n" + "gpr pc .32 0 0\n" + "gpr pcl .8 0 0\n" + "gpr pclath .8 1 0\n" + "gpr pclatu .8 2 0\n" + "#bsr max is 0b111\n" + "gpr bsr .8 4 0\n" + "#tos doesn't exist\n" + "#general rule of thumb any register of size >8 bits has no existence\n" + "gpr tos .32 5 0\n" + "gpr tosl .8 5 0\n" + "gpr tosh .8 6 0\n" + "gpr tosu .8 7 0\n" + + "gpr indf0 .16 9 0\n" + "gpr fsr0 .12 9 0\n" + "gpr fsr0l .8 9 0\n" + "gpr fsr0h .8 10 0\n" + "gpr indf1 .16 11 0\n" + "gpr fsr1 .12 11 0\n" + "gpr fsr1l .8 11 0\n" + "gpr fsr1h .8 12 0\n" + "gpr indf2 .16 13 0\n" + "gpr fsr2 .12 13 0\n" + "gpr frs2l .8 13 0\n" + "gpr fsr2h .8 14 0\n" + "gpr tblptr .22 15 0\n" + "gpr tblptrl .8 15 0\n" + "gpr tblptrh .8 16 0\n" + "gpr tblptru .8 17 0\n" + "gpr rcon .8 18 0\n" + "gpr memcon .8 19 0\n" + "gpr intcon .8 20 0\n" + "gpr intcon2 .8 21 0\n" + "gpr intcon3 .8 22 0\n" + "gpr pie1 .8 23 0\n" + "gpr porta .7 29 0\n" + "gpr trisa .8 30 0\n" + "gpr portb .8 33 0\n" + "gpr tisb .8 34 0\n" + "gpr latb .8 35 0\n" + "gpr portc .8 36 0\n" + "gpr trisc .8 37 0\n" + "gpr latc .8 38 0\n" + "gpr portd .8 39 0\n" + "gpr trisd .8 40 0\n" + "gpr latd .8 41 0\n" + "gpr pspcon .8 42 0\n" + "gpr porte .8 43 0\n" + "gpr trise .8 44 0\n" + "gpr late .8 45 0\n" + "gpr t0con .8 46 0\n" + "gpr t1con .8 47 0\n" + "gpr t2con .8 48 0\n" + "gpr tmr1h .8 50 0\n" + "gpr tmr0h .8 51 0\n" + "gpr tmr1l .8 52 0\n" + "gpr tmr2 .8 53 0\n" + "gpr pr2 .8 54 0\n" + "gpr ccpr1h .8 55 0\n" + "gpr postinc2 .8 56 0\n" + "gpr ccpr1l .8 57 0\n" + "gpr postdec2 .8 58 0\n" + "gpr ccp1con .8 59 0\n" + "gpr preinc2 .8 60 0\n" + "gpr ccpr2h .8 61 0\n" + "gpr plusw2 .8 62 0\n" + "gpr ccpr2l .8 63 0\n" + "gpr ccp2con .8 64 0\n" + "gpr status .8 65 0\n" + "flg c .1 .520 0\n" + "flg dc .1 .521 0\n" + "flg z .1 .522 0\n" + "flg ov .1 .523 0\n" + "flg n .1 .524 0\n" + "gpr prod .16 66 0\n" + "gpr prodl .8 66 0\n" + "gpr prodh .8 67 0\n" + "gpr osccon .8 68 0\n" + "gpr tmr3h .8 69 0\n" + "gpr lvdcon .8 70 0\n" + "gpr tmr3l .8 71 0\n" + "gpr wdtcon .8 72 0\n" + "gpr t3con .8 73 0\n" + "gpr spbrg .8 74 0\n" + "gpr postinc0 .8 75 0\n" + "gpr rcreg .8 76 0\n" + "gpr postdec0 .8 77 0\n" + "gpr txreg .8 78 0\n" + "gpr preinc0 .8 79 0\n" + "gpr txsta .8 80 0\n" + "gpr plusw0 .8 81 0\n" + "gpr rcsta .8 82 0\n" + "gpr sspbuf .8 83 0\n" + "gpr wreg .8 84 0\n" + "gpr sspadd .8 85 0\n" + "gpr sspstat .8 86 0\n" + "gpr postinc1 .8 87 0\n" + "gpr sspcon1 .8 88 0\n" + "gpr postdec1 .8 89 0\n" + "gpr sspcon2 .8 90 0\n" + "gpr preinc1 .8 91 0\n" + "gpr adresh .8 92 0\n" + "gpr plusw1 .8 93 0\n" + "gpr adresl .8 94 0\n" + "gpr adcon0 .8 95 0\n" + "#stkprt max is 0b11111\n" + "gpr stkptr .8 96 0\n" + "gpr tblat .8 14 0\n" + "gpr _sram .8 98 0\n" + "gpr _stack .8 99 0\n" + "gpr _skip .8 100 0\n" + "gpr wregs .8 101 0\n" + "gpr statuss .8 102 0\n" + "gpr bsrs .8 103 0\n"; + return strdup(p); +} diff --git a/librz/arch/isa/pic/pic18_esil.inc b/librz/arch/isa/pic/pic18_esil.inc new file mode 100644 index 00000000000..63c198f8399 --- /dev/null +++ b/librz/arch/isa/pic/pic18_esil.inc @@ -0,0 +1,80 @@ +// SPDX-FileCopyrightText: 2015-2018 oddcoder +// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r +// SPDX-FileCopyrightText: 2015-2018 courk +// SPDX-License-Identifier: LGPL-3.0-only + +static void pic18_cond_branch_esil(RzAnalysisOp *aop, ut64 addr, const ut8 *buf, char *flag) { + rz_strbuf_setf(&aop->esil, "%s,?,{,0x%" PFMT64x ",pc,=,}", flag, aop->jump); +} + +static void pic18_esil( + RzAnalysisOp *aop, Pic18Op *op, ut64 addr, const ut8 *buf) { + switch (op->code) { + case PIC18_OPCODE_BRA: // bra + rz_strbuf_setf(&aop->esil, "0x%" PFMT64x ",pc,=", aop->jump); + break; + case PIC18_OPCODE_BZ: // bz + pic18_cond_branch_esil(aop, addr, buf, "z"); + break; + case PIC18_OPCODE_BNZ: // bnz + pic18_cond_branch_esil(aop, addr, buf, "z,!"); + break; + case PIC18_OPCODE_BNC: // bnc + pic18_cond_branch_esil(aop, addr, buf, "c,!"); + break; + case PIC18_OPCODE_BOV: // bov + pic18_cond_branch_esil(aop, addr, buf, "ov"); + break; + case PIC18_OPCODE_BNOV: // bnov + pic18_cond_branch_esil(aop, addr, buf, "ov,!"); + break; + case PIC18_OPCODE_BN: // bn + pic18_cond_branch_esil(aop, addr, buf, "n"); + break; + case PIC18_OPCODE_BNN: // bnn + pic18_cond_branch_esil(aop, addr, buf, "n,!"); + break; + case PIC18_OPCODE_BC: // bc + pic18_cond_branch_esil(aop, addr, buf, "c"); + break; + case PIC18_OPCODE_GOTO: // goto + rz_strbuf_setf(&aop->esil, "0x%" PFMT64x ",pc,=", aop->jump); + break; + case PIC18_OPCODE_ADDLW: // addlw + // TODO add support for dc flag + rz_strbuf_setf(&aop->esil, "0x%x,wreg,+=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_MOVLW: // movlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_MULLW: // mullw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,*,prod,=", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_RETLW: // retlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,=,tos,pc,=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_ANDLW: // andlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,&=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_XORLW: // xorlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_IORLW: // iorlw + rz_strbuf_setf(&aop->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_SUBLW: // sublw + // TODO add support for dc flag + rz_strbuf_setf(&aop->esil, "wreg,0x%x,-,wreg,=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); + break; + case PIC18_OPCODE_MOVLB: // movlb + rz_strbuf_setf(&aop->esil, "0x%x,bsr,=,", *(ut16 *)buf & 0xf); + break; + case PIC18_OPCODE_RETURN: // return + rz_strbuf_setf(&aop->esil, "tos,pc,=,"); + break; + case PIC18_OPCODE_NOP: // nop + rz_strbuf_setf(&aop->esil, ","); + break; + default: break; + } +} \ No newline at end of file diff --git a/librz/arch/isa/pic/pic18_il.inc b/librz/arch/isa/pic/pic18_il.inc new file mode 100644 index 00000000000..855774c262b --- /dev/null +++ b/librz/arch/isa/pic/pic18_il.inc @@ -0,0 +1,682 @@ +// SPDX-FileCopyrightText: 2024 billow +// SPDX-License-Identifier: LGPL-3.0-only + +#include +#include +#include "pic_il.inc" + +#define U24(x) UN(24, x) +static RzILOpPure *varg_mm(Pic18ILContext *ctx, const char *v, ut8 bank); +static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank); + +static void pic18_append_eff(Pic18ILContext *ctx, const ILOpEff *eff) { + ILOpEff *i; + rz_vector_foreach (&ctx->effs, i) { + if (i->tag == eff->tag && RZ_STR_EQ(i->fsr, eff->fsr)) { + break; + } + } + rz_vector_push(&ctx->effs, (void *)eff); +} + +static RzILOpPure *pic18_reg_addr(Pic18ILContext *ctx, const char *v, ut8 bank) { + if (RZ_STR_ISEMPTY(v)) { + return NULL; + } + + ILOpEff eff = { 0 }; + if (rz_str_startswith(v, "indf")) { + long n = strtol(v + 4, NULL, 0); + rz_strf(eff.fsr, "fsr%ld", n); + } + if (rz_str_startswith(v, "postdec")) { + long n = strtol(v + 7, NULL, 0); + rz_strf(eff.fsr, "fsr%ld", n); + eff.tag = ILOpEff_PostDec; + pic18_append_eff(ctx, &eff); + } + if (rz_str_startswith(v, "postinc")) { + long n = strtol(v + 7, NULL, 0); + rz_strf(eff.fsr, "fsr%ld", n); + eff.tag = ILOpEff_PostInc; + pic18_append_eff(ctx, &eff); + } + if (rz_str_startswith(v, "predec")) { + long n = strtol(v + 6, NULL, 0); + rz_strf(eff.fsr, "fsr%ld", n); + eff.tag = ILOpEff_PreInc; + pic18_append_eff(ctx, &eff); + } + if (rz_str_startswith(v, "plusw")) { + long n = strtol(v + 5, NULL, 0); + rz_strf(eff.fsr, "fsr%ld", n); + return UNSIGNED(24, ADD(varg_mm(ctx, eff.fsr, bank), UNSIGNED(16, varg_mm(ctx, "wreg", bank)))); + } + if (eff.fsr[0]) { + return UNSIGNED(24, varg_mm(ctx, eff.fsr, bank)); + } + + bool f = false; + ut64 adr = ht_su_find((HtSU *)ctx->mm, v, &f); + if (f) { + return U24(adr + bank * 0x100); + } + return NULL; +} + +static RzILOpPure *varg_hl(Pic18ILContext *ctx, const char *v, ut8 bank) { + char h[8]; + char l[8]; + rz_strf(h, "%sh", v); + rz_strf(l, "%sl", v); + return APPEND(varg_mm(ctx, h, bank), varg_mm(ctx, l, bank)); +} +static RzILOpEffect *setg_hl(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank) { + char h[8]; + char l[8]; + rz_strf(h, "%sh", v); + rz_strf(l, "%sl", v); + return SEQ3( + SETL("__x", x), + setg_mm(ctx, h, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(8))), bank), + setg_mm(ctx, l, UNSIGNED(8, VARL("__x")), bank)); +} +static RzILOpPure *varg_uhl(Pic18ILContext *ctx, const char *v, ut8 bank) { + char u[8]; + rz_strf(u, "%su", v); + return APPEND(varg_mm(ctx, u, bank), varg_hl(ctx, v, bank)); +} +static RzILOpEffect *setg_uhl(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank) { + char u[8]; + rz_strf(u, "%su", v); + return SEQ3( + SETL("__x", x), + setg_mm(ctx, u, UNSIGNED(8, SHIFTR0(VARL("__x"), U8(16))), bank), + setg_hl(ctx, v, VARL("__x"), bank)); +} + +#define PIC18_STATUS_BIT_GET(X) \ + { \ + ut8 b = pic18_##X(v); \ + if (b != 0xff) { \ + return bit_get(varg_mm(ctx, #X, bank), b); \ + } \ + } +#define PIC18_STATUS_BIT_SET(X) \ + { \ + ut8 b = pic18_##X(v); \ + if (b != 0xff) { \ + return setg_mm(ctx, #X, bit_set1(varg_mm(ctx, #X, bank), b, x), bank); \ + } \ + } + +/** + * \see https://ww1.microchip.com/downloads/en/DeviceDoc/39500a.pdf + * 7.7.6 Indirect Addressing, INDF, and FSR Registers + * Each FSR register has an INDF register plus four addresses associated with it. The same INDFn, + * and FSRnH:FSRnL registers are used, but depending on the INDFn address selected, the + * FSRnH:FSRnL registers may be modified. + * When a data access is done to the one of the five INDFn locations, the address selected will configure the FSRn register to: + * • Do nothing to FSRn after an indirect access (no change) - INDFn + * • Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn + * • Auto-increment FSRn after an indirect access (post-increment) - POSTINCn + * • Auto-increment FSRn before an indirect access (pre-increment) - PREINCn + * • Use the value in the WREG register as an offset to FSRn. Do not modify the value of the + * WREG or the FSRn register after an indirect access (no change) - PLUSWn + */ + +#define IS_FSR(x) (RZ_STR_EQ(x, "fsr0") || RZ_STR_EQ(x, "fsr1") || RZ_STR_EQ(x, "fsr2")) +static RzILOpPure *varg_mm(Pic18ILContext *ctx, const char *v, ut8 bank) { + if (RZ_STR_ISEMPTY(v)) { + rz_warn_if_reached(); + return NULL; + } + RzILOpPure *adr = pic18_reg_addr(ctx, v, bank); + if (adr) { + return LOAD(adr); + } + + PIC18_STATUS_BIT_GET(status); + PIC18_STATUS_BIT_GET(rcon); + PIC18_STATUS_BIT_GET(intcon); + + if (RZ_STR_EQ(v, "tblptr") || RZ_STR_EQ(v, "tos")) { + return varg_uhl(ctx, v, bank); + } + if (IS_FSR(v)) { + return varg_hl(ctx, v, bank); + } + return VARG(v); +} +static RzILOpEffect *setg_mm(Pic18ILContext *ctx, const char *v, RzILOpPure *x, ut8 bank) { + if (RZ_STR_ISEMPTY(v)) { + rz_warn_if_reached(); + return NULL; + } + RzILOpPure *adr = pic18_reg_addr(ctx, v, bank); + if (adr) { + return STORE(adr, x); + } + + PIC18_STATUS_BIT_SET(status); + PIC18_STATUS_BIT_SET(rcon); + PIC18_STATUS_BIT_SET(intcon); + + if (RZ_STR_EQ(v, "tblptr") || RZ_STR_EQ(v, "tos")) { + return setg_uhl(ctx, v, x, bank); + } + if (IS_FSR(v)) { + return setg_hl(ctx, v, x, bank); + } + return SETG(v, x); +} + +#undef VARG +#undef SETG +#define VARG(x) varg_mm(ctx, x, 0) +#define SETG(v, x) setg_mm(ctx, v, x, 0) + +#define K (ctx->op->k) +#define D (ctx->op->d) +#define F (ctx->op->f) +#define B (ctx->op->b) +#define N (ctx->op->n) +#define PC (ctx->op->addr) + +#define RW "wreg" +#define VRW (VARG(RW)) +#define RF pic18_regname(F) +#define VRF (VARG(pic18_regname(F))) +#define RWF (D ? pic18_regname(F) : RW) +#define VRWF (VARG(RWF)) + +#define VPC (UN(24, PC)) +#define RC "c" +#define VRC VARG(RC) +#define RN "n" +#define VRN VARG(RN) +#define ROV "ov" +#define VROV VARG(ROV) +#define RZ "z" +#define VRZ VARG(RZ) +#define RS "s" +#define VRS VARG(RS) + +/** + * The `d` bit selects the destination for the operation. + * If `d` is 1; the result is stored back in the File Register `f`. + * If `d` is 0; the result is stored in the WREG Register. + * + * The `a` bit selects which bank is accessed for the operation. + * If `a` is 1; the bank specified by the BSR Register is used. + * If `a` is 0; the access bank is used. + */ +static RzILOpEffect *set_dest(Pic18ILContext *ctx, RzILOpPure *x) { + const char *fsr = ctx->op->d ? pic18_regname(F) : RW; + if (ctx->op->a) { + RzILOpPure *adr = pic18_reg_addr(ctx, fsr, 0); + if (adr != NULL) { + return STORE( + ADD(MUL(UNSIGNED(24, LOGAND(VARG("bsr"), U8(0x0f))), UN(24, 0x100)), adr), + x); + } + return NULL; + } + return SETG(fsr, x); +} + +/** + * bit 4: N: Negative bit + * This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative, (ALU MSb = 1). + * 1 = Result was negative + * 0 = Result was positive + * + * bit 3: OV: Overflow bit + * This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit7) to change state. + * 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) + * 0 = No overflow occurred + * + * bit 2: Z: Zero bit + * 1 = The result of an arithmetic or logic operation is zero + * 0 = The result of an arithmetic or logic operation is not zero + * + * bit 1: DC: Digit carry/borrow bit + * For ADDWF, ADDLW, SUBLW, and SUBWF instructions + * 1 = A carry-out from the 4th low order bit of the result occurred + * 0 = No carry-out from the 4th low order bit of the result + * Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded + * with either the bit4 or bit3 of the source register. + * + * bit 0: C: Carry/borrow bit + * For ADDWF, ADDLW, SUBLW, and SUBWF instructions + * 1 = A carry-out from the most significant bit of the result occurred + * 0 = No carry-out from the most significant bit of the result occurred + * Note: For borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded + * with either the high or low order bit of the source register. + */ + +static RzILOpEffect *status_add(Pic18ILContext *ctx, RzILOpPure *a, RzILOpPure *b, RzILOpPure *res, RzILOpPure *curry) { + return SEQ5( + SETG("c", CHECK_CARRY(a, b, res)), + SETG("dc", CHECK_DIGIT_CARRY(DUP(a), DUP(b), DUP(res))), + SETG("z", IS_ZERO(DUP(res))), + SETG("ov", CHECK_OVERFLOW(DUP(a), DUP(b), DUP(res))), + SETG("n", MSB(DUP(res)))); +} + +static RzILOpEffect *status_sub(Pic18ILContext *ctx, RzILOpPure *a, RzILOpPure *b, RzILOpPure *res, RzILOpPure *curry) { + return SEQ5( + SETG("c", CHECK_BORROW(a, b, res)), + SETG("dc", CHECK_DIGIT_BORROW(DUP(a), DUP(b), DUP(res))), + SETG("z", IS_ZERO(DUP(res))), + SETG("ov", CHECK_OVERFLOW(DUP(a), DUP(b), DUP(res))), + SETG("n", MSB(DUP(res)))); +} + +static RzILOpEffect *status_res(Pic18ILContext *ctx, RzILOpPure *res) { + return SEQ2( + SETG("z", IS_ZERO(res)), + SETG("n", MSB(DUP(res)))); +} + +static RzILOpEffect *set_dest_status(Pic18ILContext *ctx, RzILOpPure *x) { + return SEQ3( + SETL("__res", x), + status_res(ctx, VARL("__res")), + set_dest(ctx, VARL("__res"))); +} + +static RzILOpPure *complement_1(RzILOpPure *x) { + return NEG(x); +} + +static RzILOpPure *complement_2(RzILOpPure *x) { + return ADD(U8(1), NEG(x)); +} + +static RzILOpPure *decimal_adjust(Pic18ILContext *ctx, RzILOpPure *x) { + return LET( + "_x03", UNSIGNED(4, x), + LET( + "_x47", UNSIGNED(4, SHIFTR0(DUP(x), U8(4))), + APPEND( + ITE(OR(UGT(VARLP("_x47"), UN(4, 9)), VARG("c")), + ADD(VARLP("_x47"), UN(4, 6)), + VARLP("_x47")), + ITE(OR(UGT(VARLP("_x03"), UN(4, 9)), VARG("dc")), + ADD(VARLP("_x03"), UN(4, 6)), + VARLP("_x03"))))); +} + +#define SET_DST_RES (dst ? SETG(dst, VARL("__res")) : set_dest(ctx, VARL("__res"))) + +static RzILOpEffect *op_add(Pic18ILContext *ctx, const char *dst, + RzILOpPure *a, RzILOpPure *b, RzILOpPure *curry) { + return SEQ3( + SETL("__res", ADD(a, curry ? ADD(b, curry) : b)), + status_add(ctx, DUP(a), DUP(b), VARL("__res"), curry ? DUP(curry) : NULL), + SET_DST_RES); +} + +static RzILOpEffect *op_sub(Pic18ILContext *ctx, const char *dst, + RzILOpPure *a, RzILOpPure *b, RzILOpPure *curry) { + return SEQ3( + SETL("__res", SUB(a, curry ? ADD(b, curry) : b)), + status_sub(ctx, DUP(a), DUP(b), VARL("__res"), curry ? DUP(curry) : NULL), + SET_DST_RES); +} + +static RzILOpEffect *op_branch(Pic18ILContext *ctx, RzILOpPure *condition) { + st8 n = (st8)((ut8)ctx->op->n); + RzILOpEffect *jmp = JMP(UN(24, PC + 2 + 2 * n)); + return condition ? BRANCH(condition, jmp, NOP()) + : jmp; +} + +static RzILOpEffect *load_shadows_opt(Pic18ILContext *ctx) { + return ctx->op->s ? SEQ3( + SETG("wregs", VRW), + SETG("statuss", VARG("status")), + SETG("bsrs", VARG("bsr"))) + : NOP(); +} + +static RzILOpEffect *op_call(Pic18ILContext *ctx) { + return SEQ3( + SETG("tos", UN(24, PC + 4)), + load_shadows_opt(ctx), + JMP(UN(24, K << 1))); +} + +static RzILOpEffect *op_and(Pic18ILContext *ctx, const char *dst, + RzILOpPure *a, RzILOpPure *b) { + return SEQ3( + SETL("__res", LOGAND(a, b)), + status_res(ctx, VARL("__res")), + SET_DST_RES); +} + +static RzILOpEffect *op_skip_if(Pic18ILContext *ctx, RzILOpPure *condition) { + return BRANCH(condition, SETG("_skip", U8(1)), NOP()); +} + +static RzILOpEffect *set_prod16(Pic18ILContext *ctx, RzILOpPure *res) { + return SEQ3( + SETL("__res", res), + SETG("prodh", UNSIGNED(8, SHIFTR0(VARL("__res"), U8(8)))), + SETG("prodl", UNSIGNED(8, VARL("__res")))); +} + +static RzILOpEffect *op_pop(Pic18ILContext *ctx) { + return SEQ2( + SETG("stkptr", SUB(VARG("stkptr"), U8(4))), + SETG("tos", LOADW(24, UNSIGNED(24, ADD(VARG("_stack"), VARG("stkptr")))))); +} + +static RzILOpEffect *op_pop_jmp(Pic18ILContext *ctx) { + return SEQ3( + SETL("_pc", VARG("tos")), + op_pop(ctx), + JMP(VARL("_pc"))); +} + +static RzILOpEffect *op_push(Pic18ILContext *ctx, RzILOpPure *x) { + return SEQ3( + SETG("stkptr", ADD(VARG("stkptr"), U8(4))), + STOREW(UNSIGNED(24, ADD(VARG("_stack"), VARG("stkptr"))), x), + SETG("tos", DUP(x))); +} + +static RzILOpEffect *op_lfsr(Pic18ILContext *ctx) { + ut8 lo = (ut8)ctx->op->k; + ut8 hi = (ut8)ctx->op->k >> 8; + char regl[8]; + char regh[8]; + rz_strf(regl, "fsr%dl", ctx->op->f); + rz_strf(regh, "fsr%dh", ctx->op->f); + return SEQ2( + SETG(regl, U8(lo)), + SETG(regh, U8(hi))); +} + +static RzILOpEffect *pic18_il_op(Pic18ILContext *ctx) { + switch (ctx->op->code) { + case PIC18_OPCODE_ADDLW: return op_add(ctx, RW, VRW, U8(K), NULL); + case PIC18_OPCODE_ADDWF: return op_add(ctx, NULL, VRW, VRF, NULL); + case PIC18_OPCODE_ADDWFC: return op_add(ctx, NULL, VRW, VRF, BOOL_TO_BV(VRC, 8)); + case PIC18_OPCODE_ANDLW: return op_and(ctx, RW, VRW, U8(K)); + case PIC18_OPCODE_ANDWF: return op_and(ctx, NULL, VRW, VRF); + case PIC18_OPCODE_BC: return op_branch(ctx, VRC); + case PIC18_OPCODE_BN: return op_branch(ctx, VRN); + case PIC18_OPCODE_BOV: return op_branch(ctx, VROV); + case PIC18_OPCODE_BZ: return op_branch(ctx, VRZ); + case PIC18_OPCODE_BNC: return op_branch(ctx, INV(VRC)); + case PIC18_OPCODE_BNN: return op_branch(ctx, INV(VRN)); + case PIC18_OPCODE_BNOV: return op_branch(ctx, INV(VROV)); + case PIC18_OPCODE_BNZ: return op_branch(ctx, INV(VRZ)); + case PIC18_OPCODE_BRA: return op_branch(ctx, NULL); + + case PIC18_OPCODE_BCF: return regbit_set(RF, B, 0); + case PIC18_OPCODE_BSF: return regbit_set(RF, B, 1); + case PIC18_OPCODE_BTG: return regbit_set1(RF, B, INV(bit_get(VRF, B))); + case PIC18_OPCODE_BTFSC: return op_skip_if(ctx, BITN(VRF, B)); + case PIC18_OPCODE_BTFSS: return op_skip_if(ctx, bit_get(VRF, B)); + + case PIC18_OPCODE_CALL: return op_call(ctx); + case PIC18_OPCODE_CLRF: return SEQ2(SETG(RF, U8(0)), SETG("z", IL_TRUE)); + case PIC18_OPCODE_CLRWDT: + return NOP(); + // return SEQ4( + // SETG("wdt", U8(0)), + // SETG("wdtps", IL_FALSE), + // SETG("to", IL_TRUE), + // SETG("pd", IL_TRUE)); + case PIC18_OPCODE_SLEEP: + return NOP(); + // return SEQ4( + // SETG("wdt", U8(0)), + // SETG("wdtps", IL_FALSE), + // SETG("to", IL_TRUE), + // SETG("pd", IL_FALSE)); + case PIC18_OPCODE_COMF: return set_dest_status(ctx, complement_1(VRF)); + case PIC18_OPCODE_CPFSEQ: return op_skip_if(ctx, EQ(VRW, VRF)); + case PIC18_OPCODE_CPFSGT: return op_skip_if(ctx, UGT(VRF, VRW)); + case PIC18_OPCODE_CPFSLT: return op_skip_if(ctx, ULT(VRF, VRW)); + case PIC18_OPCODE_DAW: + return SEQ3( + SETL("__res", decimal_adjust(ctx, VRW)), + SETG("c", IL_FALSE), // TODO: status C + SETG(RW, VARL("__res"))); + case PIC18_OPCODE_DECF: + return SEQ3( + SETL("__res", SUB(VRF, U8(1))), + status_sub(ctx, VRF, U8(1), VARL("__res"), NULL), + set_dest(ctx, VARL("__res"))); + case PIC18_OPCODE_DECFSZ: + return SEQ3( + SETL("__res", SUB(VRF, U8(1))), + set_dest(ctx, VARL("__res")), + op_skip_if(ctx, IS_ZERO(VARL("__res")))); + case PIC18_OPCODE_DCFSNZ: + return SEQ3( + SETL("__res", SUB(VRF, U8(1))), + set_dest(ctx, VARL("__res")), + op_skip_if(ctx, NON_ZERO(VARL("__res")))); + case PIC18_OPCODE_GOTO: return JMP(UN(24, (ut32)K << 1)); + case PIC18_OPCODE_INCF: + return SEQ3( + SETL("__res", ADD(VRF, U8(1))), + status_add(ctx, VRF, U8(1), VARL("__res"), NULL), + set_dest(ctx, VARL("__res"))); + case PIC18_OPCODE_INCFSZ: + return SEQ3( + SETL("__res", ADD(VRF, U8(1))), + set_dest(ctx, VARL("__res")), + op_skip_if(ctx, IS_ZERO(VARL("__res")))); + case PIC18_OPCODE_INFSNZ: + return SEQ3( + SETL("__res", ADD(VRF, U8(1))), + set_dest(ctx, VARL("__res")), + op_skip_if(ctx, NON_ZERO(VARL("__res")))); + case PIC18_OPCODE_IORWF: + return set_dest_status(ctx, LOGOR(VRW, VRF)); + case PIC18_OPCODE_IORLW: + return SEQ2( + SETG(RW, LOGOR(VRW, U8(K))), + status_res(ctx, VRW)); + case PIC18_OPCODE_LFSR: return op_lfsr(ctx); + case PIC18_OPCODE_MOVF: + return set_dest_status(ctx, VRF); + case PIC18_OPCODE_MOVFF: { + const char *rs = pic18_regname_extra(ctx->op->s); + const char *rd = pic18_regname_extra(ctx->op->d); + if (rs && rd) { + return setg_mm(ctx, rd, + varg_mm(ctx, rs, 0), + 0); + } else if (rs) { + return STORE(U24(ctx->op->d), + varg_mm(ctx, rs, 0)); + } else if (rd) { + return setg_mm(ctx, rd, + LOAD(U24(ctx->op->s)), + 0); + } else { + return STORE(U24(ctx->op->d), + LOAD(U24(ctx->op->s))); + } + } + case PIC18_OPCODE_MOVLB: + return SETG("bsr", LOGOR(U8(K), LOGAND(VARG("bsr"), U8(0xf0)))); + case PIC18_OPCODE_MOVLW: + return SETG(RW, U8(K)); + case PIC18_OPCODE_MOVWF: + return SETG(RF, VRW); + case PIC18_OPCODE_MULLW: + return set_prod16(ctx, MUL(UNSIGNED(16, VRW), U16(K))); + case PIC18_OPCODE_MULWF: + return set_prod16(ctx, MUL(UNSIGNED(16, VRW), UNSIGNED(16, VRF))); + case PIC18_OPCODE_NOP: return NOP(); + case PIC18_OPCODE_NEGF: return SETG(RF, complement_2(VRF)); + case PIC18_OPCODE_POP: return op_pop(ctx); + case PIC18_OPCODE_PUSH: return op_push(ctx, UN(24, PC)); + case PIC18_OPCODE_RCALL: + return SEQ2( + op_push(ctx, UN(24, PC + 2)), + JMP(UN(24, PC + 2 + 2 * N))); + case PIC18_OPCODE_RESET: return NOP(); + case PIC18_OPCODE_RETFIE: + return SEQ3( + BRANCH( + INV(VARG("ipen")), + SETG("gie", IL_TRUE), + BRANCH( + VARG("gieh"), + SETG("giel", IL_TRUE), + SETG("gieh", IL_TRUE))), + load_shadows_opt(ctx), + op_pop_jmp(ctx)); + case PIC18_OPCODE_RETLW: + return SEQ2( + SETG(RW, U8(K)), + op_pop_jmp(ctx)); + case PIC18_OPCODE_RETURN: + return SEQ2( + load_shadows_opt(ctx), + op_pop_jmp(ctx)); + case PIC18_OPCODE_RLNCF: + return set_dest_status(ctx, LET("_x", VRF, LOGOR(SHIFTL0(VARLP("_x"), U8(7)), BOOL_TO_BV(MSB(VARLP("_x")), 8)))); + case PIC18_OPCODE_RRNCF: + return set_dest_status(ctx, LET("_x", VRF, LOGOR(SHIFTR0(VARLP("_x"), U8(7)), BOOL_TO_BV(LSB(VARLP("_x")), 8)))); + case PIC18_OPCODE_RLCF: + return SEQ3( + SETL("_x", VRF), + SETG("c", MSB(VARL("_x"))), + set_dest_status(ctx, LOGOR(SHIFTL0(VARL("_x"), U8(7)), BOOL_TO_BV(VRC, 8)))); + case PIC18_OPCODE_RRCF: + return SEQ3( + SETL("_x", VRF), + SETG("c", LSB(VARL("_x"))), + set_dest_status(ctx, LOGOR(SHIFTR0(VARL("_x"), U8(7)), BOOL_TO_BV(VRC, 8)))); + case PIC18_OPCODE_SETF: + return SETG(RF, U8(0xff)); + case PIC18_OPCODE_SUBFWB: return op_sub(ctx, NULL, VRW, VRF, BOOL_TO_BV(VRC, 8)); + case PIC18_OPCODE_SUBLW: return op_sub(ctx, RW, U8(K), VRW, NULL); + case PIC18_OPCODE_SUBWF: return op_sub(ctx, NULL, VRF, VRW, NULL); + case PIC18_OPCODE_SUBWFB: return op_sub(ctx, NULL, VRF, VRW, BOOL_TO_BV(VRC, 8)); + case PIC18_OPCODE_SWAPF: + return set_dest(ctx, APPEND(UNSIGNED(4, VRF), UNSIGNED(4, SHIFTR0(VRF, U8(4))))); + + case PIC18_OPCODE_TBLRDs: + return SETG("tablat", LOAD(VARG("tblptr"))); + case PIC18_OPCODE_TBLRDis: + return SEQ2( + SETG("tblptr", ADD(VARG("tblptr"), UN(24, 1))), + SETG("tablat", LOAD(VARG("tblptr")))); + case PIC18_OPCODE_TBLRDsd: + return SEQ2( + SETG("tablat", LOAD(VARG("tblptr"))), + SETG("tblptr", SUB(VARG("tblptr"), UN(24, 1)))); + case PIC18_OPCODE_TBLRDsi: + return SEQ2( + SETG("tablat", LOAD(VARG("tblptr"))), + SETG("tblptr", ADD(VARG("tblptr"), UN(24, 1)))); + case PIC18_OPCODE_TBLWTMs: + return STORE(VARG("tblptr"), VARG("tablat")); + case PIC18_OPCODE_TBLWTis: + return SEQ2( + SETG("tblptr", ADD(VARG("tblptr"), UN(24, 1))), + STORE(VARG("tblptr"), VARG("tablat"))); + case PIC18_OPCODE_TBLWTMsd: + return SEQ2( + STORE(VARG("tblptr"), VARG("tablat")), + SETG("tblptr", SUB(VARG("tblptr"), UN(24, 1)))); + case PIC18_OPCODE_TBLWTMsi: + return SEQ2( + STORE(VARG("tblptr"), VARG("tablat")), + SETG("tblptr", ADD(VARG("tblptr"), UN(24, 1)))); + case PIC18_OPCODE_TSTFSZ: + return op_skip_if(ctx, IS_ZERO(VRF)); + case PIC18_OPCODE_XORWF: + return set_dest_status(ctx, LOGXOR(VRW, VRF)); + case PIC18_OPCODE_XORLW: + return SEQ2( + SETG(RW, LOGXOR(VRW, VRF)), + status_res(ctx, VRW)); + case PIC18_OPCODE_INVALID: break; + } + return NULL; +} + +static RzILOpEffect *pic18_il_op_finally(Pic18ILContext *ctx) { + RzILOpEffect *op = pic18_il_op(ctx); + ILOpEff *eff; + rz_vector_foreach (&ctx->effs, eff) { + switch (eff->tag) { + case ILOpEff_None: break; + case ILOpEff_PostDec: + op = SEQ2( + op, + SETG(eff->fsr, SUB(VARG(eff->fsr), U16(1)))); + break; + case ILOpEff_PostInc: + op = SEQ2( + op, + SETG(eff->fsr, ADD(VARG(eff->fsr), U16(1)))); + break; + case ILOpEff_PreInc: + op = SEQ2( + SETG(eff->fsr, ADD(VARG(eff->fsr), U16(1))), + op); + break; + } + } + return BRANCH(NON_ZERO(VARG("_skip")), + SETG("_skip", U8(0)), + op); +} + +#undef K +#undef D +#undef F +#undef B +#undef N +#undef PC + +#undef RW +#undef VRW +#undef RF +#undef VRF +#undef RWF +#undef VRWF +#undef VPC +#undef RC +#undef VRC +#undef RN +#undef VRN +#undef ROV +#undef VROV +#undef RZ +#undef VRZ +#undef RS +#undef VRS + +static const char *pic18_reg_bindings[] = { + "pc", + "wregs", + "statuss", + "bsrs", + "_sram", + "_stack", + "_skip", + NULL +}; + +RzAnalysisILConfig *pic18_il_config( + RZ_NONNULL RzAnalysis *analysis) { + RzAnalysisILConfig *cfg = rz_analysis_il_config_new(24, false, 24); + cfg->reg_bindings = pic18_reg_bindings; + return cfg; +} + +#include diff --git a/librz/arch/isa/pic/pic_baseline.c b/librz/arch/isa/pic/pic_baseline.c deleted file mode 100644 index c91050a8ba5..00000000000 --- a/librz/arch/isa/pic/pic_baseline.c +++ /dev/null @@ -1,254 +0,0 @@ -// SPDX-FileCopyrightText: 2018 thestr4ng3r -// SPDX-License-Identifier: LGPL-3.0-only - -#include "pic_baseline.h" - -static const PicBaselineOpInfo pic_baseline_op_info[PIC_BASELINE_OPCODE_INVALID] = { - { "nop", PIC_BASELINE_OP_ARGS_NONE }, - { "option", PIC_BASELINE_OP_ARGS_NONE }, - { "sleep", PIC_BASELINE_OP_ARGS_NONE }, - { "clrwdt", PIC_BASELINE_OP_ARGS_NONE }, - { "tris", PIC_BASELINE_OP_ARGS_3F }, - { "movlb", PIC_BASELINE_OP_ARGS_3K }, - { "return", PIC_BASELINE_OP_ARGS_NONE }, - { "retfie", PIC_BASELINE_OP_ARGS_NONE }, - { "movwf", PIC_BASELINE_OP_ARGS_5F }, - { "clrf", PIC_BASELINE_OP_ARGS_5F }, - { "clrw", PIC_BASELINE_OP_ARGS_NONE }, - { "subwf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "decf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "iorwf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "andwf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "xorwf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "andwf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "movf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "comf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "incf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "decfsz", PIC_BASELINE_OP_ARGS_1D_5F }, - { "rrf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "rlf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "swapf", PIC_BASELINE_OP_ARGS_1D_5F }, - { "incfsz", PIC_BASELINE_OP_ARGS_1D_5F }, - { "bcf", PIC_BASELINE_OP_ARGS_3B_5F }, - { "bsf", PIC_BASELINE_OP_ARGS_3B_5F }, - { "btfsc", PIC_BASELINE_OP_ARGS_3B_5F }, - { "btfss", PIC_BASELINE_OP_ARGS_3B_5F }, - { "retlw", PIC_BASELINE_OP_ARGS_8K }, - { "call", PIC_BASELINE_OP_ARGS_8K }, - { "goto", PIC_BASELINE_OP_ARGS_9K }, - { "movlw", PIC_BASELINE_OP_ARGS_8K }, - { "iorlw", PIC_BASELINE_OP_ARGS_8K }, - { "andlw", PIC_BASELINE_OP_ARGS_8K }, - { "xorlw", PIC_BASELINE_OP_ARGS_8K } -}; - -PicBaselineOpcode pic_baseline_get_opcode(ut16 instr) { - if (instr & 0xf000) { - return PIC_BASELINE_OPCODE_INVALID; - } - - switch ((instr >> 6) & 0x3f) { // first 6 bits - case 0x7: // 0b000111 - return PIC_BASELINE_OPCODE_ADDWF; - case 0x5: // 0b000101 - return PIC_BASELINE_OPCODE_ANDWF; - case 0x1: // 0b000001 - if (instr & (1 << 5)) { - return PIC_BASELINE_OPCODE_CLRF; - } - if ((instr & 0x1f) == 0) { // last 5 bits - return PIC_BASELINE_OPCODE_CLRW; - } - return PIC_BASELINE_OPCODE_INVALID; - case 0x9: // 0b001001 - return PIC_BASELINE_OPCODE_COMF; - case 0x3: // 0b000011 - return PIC_BASELINE_OPCODE_DECF; - case 0xb: // 0b001011 - return PIC_BASELINE_OPCODE_DECFSZ; - case 0xa: // 0b001010 - return PIC_BASELINE_OPCODE_INCF; - case 0xf: // 0b001111 - return PIC_BASELINE_OPCODE_INCFSZ; - case 0x4: // 0b000100 - return PIC_BASELINE_OPCODE_IORWF; - case 0x8: // 0b001000 - return PIC_BASELINE_OPCODE_MOVF; - case 0x0: - if (instr & (1 << 5)) { - return PIC_BASELINE_OPCODE_MOVWF; - } else { - switch (instr & 0x1f) { // last 5 bits - case 0x0: // 0b00000 - return PIC_BASELINE_OPCODE_NOP; - case 0x4: // 0b00100 - return PIC_BASELINE_OPCODE_CLRWDT; - case 0x2: // 0b00010 - return PIC_BASELINE_OPCODE_OPTION; - case 0x3: // 0b00011 - return PIC_BASELINE_OPCODE_SLEEP; - case 0x1: // 0b00001 - case 0x5: // 0b00101 - case 0x6: // 0b00110 - case 0x7: // 0b00111 - return PIC_BASELINE_OPCODE_TRIS; - case 0x10: // 0b10000 - case 0x11: // 0b10001 - case 0x12: // 0b10010 - case 0x13: // 0b10011 - case 0x14: // 0b10100 - case 0x15: // 0b10101 - case 0x16: // 0b10110 - case 0x17: // 0b10111 - return PIC_BASELINE_OPCODE_MOVLB; - case 0x1e: // 0b11110 - return PIC_BASELINE_OPCODE_RETURN; - case 0x1f: // 0b11111 - return PIC_BASELINE_OPCODE_RETFIE; - default: - return PIC_BASELINE_OPCODE_INVALID; - } - } - case 0xd: // 0b001101 - return PIC_BASELINE_OPCODE_RLF; - case 0xc: // 0b001100 - return PIC_BASELINE_OPCODE_RRF; - case 0x2: // 0b000010 - return PIC_BASELINE_OPCODE_SUBWF; - case 0xe: // 0b001110 - return PIC_BASELINE_OPCODE_SWAPF; - case 0x6: // 0b000110 - return PIC_BASELINE_OPCODE_XORWF; - case 0x10: // 0b010000 - case 0x11: // 0b010001 - case 0x12: // 0b010010 - case 0x13: // 0b010011 - return PIC_BASELINE_OPCODE_BCF; - case 0x14: // 0b010100 - case 0x15: // 0b010101 - case 0x16: // 0b010110 - case 0x17: // 0b010111 - return PIC_BASELINE_OPCODE_BSF; - case 0x18: // 0b011000 - case 0x19: // 0b011001 - case 0x1a: // 0b011010 - case 0x1b: // 0b011011 - return PIC_BASELINE_OPCODE_BTFSC; - case 0x1c: // 0b011100 - case 0x1d: // 0b011101 - case 0x1e: // 0b011110 - case 0x1f: // 0b011111 - return PIC_BASELINE_OPCODE_BTFSS; - case 0x38: // 0b111000 - case 0x39: // 0b111001 - case 0x3a: // 0b111010 - case 0x3b: // 0b111011 - return PIC_BASELINE_OPCODE_ANDLW; - case 0x24: // 0b100100 - case 0x25: // 0b100101 - case 0x26: // 0b100110 - case 0x27: // 0b100111 - return PIC_BASELINE_OPCODE_CALL; - case 0x28: // 0b101000 - case 0x29: // 0b101001 - case 0x2a: // 0b101010 - case 0x2b: // 0b101011 - case 0x2c: // 0b101100 - case 0x2d: // 0b101101 - case 0x2e: // 0b101110 - case 0x2f: // 0b101111 - return PIC_BASELINE_OPCODE_GOTO; - case 0x34: // 0b110100 - case 0x35: // 0b110101 - case 0x36: // 0b110110 - case 0x37: // 0b110111 - return PIC_BASELINE_OPCODE_IORLW; - case 0x30: // 0b110000 - case 0x31: // 0b110001 - case 0x32: // 0b110010 - case 0x33: // 0b110011 - return PIC_BASELINE_OPCODE_MOVLW; - case 0x20: // 0b100000 - case 0x21: // 0b100001 - case 0x22: // 0b100010 - case 0x23: // 0b100011 - return PIC_BASELINE_OPCODE_RETLW; - case 0x3c: // 0b111100 - case 0x3d: // 0b111101 - case 0x3e: // 0b111110 - case 0x3f: // 0b111111 - return PIC_BASELINE_OPCODE_XORLW; - default: - return PIC_BASELINE_OPCODE_INVALID; - } -} - -const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode) { - if (opcode >= PIC_BASELINE_OPCODE_INVALID) { - return NULL; - } - return &pic_baseline_op_info[opcode]; -} - -int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l) { -#define EMIT_INVALID \ - { \ - op->size = 1; \ - rz_asm_op_set_asm(op, "invalid"); \ - return 1; \ - } - if (!b || l < 2) { - EMIT_INVALID - } - - ut16 instr = rz_read_le16(b); - PicBaselineOpcode opcode = pic_baseline_get_opcode(instr); - if (opcode == PIC_BASELINE_OPCODE_INVALID) { - EMIT_INVALID - } - - const PicBaselineOpInfo *op_info = pic_baseline_get_op_info(opcode); - if (!op_info) { - EMIT_INVALID - } - -#undef EMIT_INVALID - - op->size = 2; - switch (op_info->args) { - case PIC_BASELINE_OP_ARGS_NONE: - rz_asm_op_set_asm(op, op_info->mnemonic); - break; - case PIC_BASELINE_OP_ARGS_2F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_2F_MASK_F); - break; - case PIC_BASELINE_OP_ARGS_3F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3F_MASK_F); - break; - case PIC_BASELINE_OP_ARGS_3K: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3K_MASK_K); - break; - case PIC_BASELINE_OP_ARGS_1D_5F: - rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_F, - (instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_D) >> 5 ? 'f' : 'w'); - break; - case PIC_BASELINE_OP_ARGS_5F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_5F_MASK_F); - break; - case PIC_BASELINE_OP_ARGS_3B_5F: - rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_F, - (instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_B) >> 5); - break; - case PIC_BASELINE_OP_ARGS_8K: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_8K_MASK_K); - break; - case PIC_BASELINE_OP_ARGS_9K: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_9K_MASK_K); - break; - default: - rz_asm_op_set_asm(op, "invalid"); - break; - } - - return op->size; -} diff --git a/librz/arch/isa/pic/pic_baseline.h b/librz/arch/isa/pic/pic_baseline.h deleted file mode 100644 index a662dd593ec..00000000000 --- a/librz/arch/isa/pic/pic_baseline.h +++ /dev/null @@ -1,82 +0,0 @@ -// SPDX-FileCopyrightText: 2018 thestr4ng3r -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef PIC_BASELINE_H -#define PIC_BASELINE_H - -#include -#include - -typedef enum { - PIC_BASELINE_OP_ARGS_NONE = 0, - PIC_BASELINE_OP_ARGS_2F, - PIC_BASELINE_OP_ARGS_3F, - PIC_BASELINE_OP_ARGS_3K, - PIC_BASELINE_OP_ARGS_1D_5F, - PIC_BASELINE_OP_ARGS_5F, - PIC_BASELINE_OP_ARGS_3B_5F, - PIC_BASELINE_OP_ARGS_8K, - PIC_BASELINE_OP_ARGS_9K -} PicBaselineOpArgs; - -#define PIC_BASELINE_OP_ARGS_2F_MASK_F 0x3 -#define PIC_BASELINE_OP_ARGS_3F_MASK_F 0x7 -#define PIC_BASELINE_OP_ARGS_3K_MASK_K 0x7 -#define PIC_BASELINE_OP_ARGS_1D_5F_MASK_D (1 << 5) -#define PIC_BASELINE_OP_ARGS_1D_5F_MASK_F 0x1f -#define PIC_BASELINE_OP_ARGS_5F_MASK_F 0x1f -#define PIC_BASELINE_OP_ARGS_3B_5F_MASK_B (0x7 << 5) -#define PIC_BASELINE_OP_ARGS_3B_5F_MASK_F 0x1f -#define PIC_BASELINE_OP_ARGS_8K_MASK_K 0xff -#define PIC_BASELINE_OP_ARGS_9K_MASK_K 0x1ff - -typedef struct _pic_baseline_op { - const char *mnemonic; - PicBaselineOpArgs args; -} PicBaselineOpInfo; - -typedef enum { - PIC_BASELINE_OPCODE_NOP = 0, - PIC_BASELINE_OPCODE_OPTION, - PIC_BASELINE_OPCODE_SLEEP, - PIC_BASELINE_OPCODE_CLRWDT, - PIC_BASELINE_OPCODE_TRIS, - PIC_BASELINE_OPCODE_MOVLB, - PIC_BASELINE_OPCODE_RETURN, - PIC_BASELINE_OPCODE_RETFIE, - PIC_BASELINE_OPCODE_MOVWF, - PIC_BASELINE_OPCODE_CLRF, - PIC_BASELINE_OPCODE_CLRW, - PIC_BASELINE_OPCODE_SUBWF, - PIC_BASELINE_OPCODE_DECF, - PIC_BASELINE_OPCODE_IORWF, - PIC_BASELINE_OPCODE_ANDWF, - PIC_BASELINE_OPCODE_XORWF, - PIC_BASELINE_OPCODE_ADDWF, - PIC_BASELINE_OPCODE_MOVF, - PIC_BASELINE_OPCODE_COMF, - PIC_BASELINE_OPCODE_INCF, - PIC_BASELINE_OPCODE_DECFSZ, - PIC_BASELINE_OPCODE_RRF, - PIC_BASELINE_OPCODE_RLF, - PIC_BASELINE_OPCODE_SWAPF, - PIC_BASELINE_OPCODE_INCFSZ, - PIC_BASELINE_OPCODE_BCF, - PIC_BASELINE_OPCODE_BSF, - PIC_BASELINE_OPCODE_BTFSC, - PIC_BASELINE_OPCODE_BTFSS, - PIC_BASELINE_OPCODE_RETLW, - PIC_BASELINE_OPCODE_CALL, - PIC_BASELINE_OPCODE_GOTO, - PIC_BASELINE_OPCODE_MOVLW, - PIC_BASELINE_OPCODE_IORLW, - PIC_BASELINE_OPCODE_ANDLW, - PIC_BASELINE_OPCODE_XORLW, - PIC_BASELINE_OPCODE_INVALID -} PicBaselineOpcode; - -PicBaselineOpcode pic_baseline_get_opcode(ut16 instr); -const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode); -int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l); - -#endif // PIC_BASELINE_H diff --git a/librz/arch/isa/pic/pic_il.inc b/librz/arch/isa/pic/pic_il.inc new file mode 100644 index 00000000000..228f186a521 --- /dev/null +++ b/librz/arch/isa/pic/pic_il.inc @@ -0,0 +1,36 @@ +// SPDX-FileCopyrightText: 2023 Siddharth Mishra +// SPDX-FileCopyrightText: 2024 Billow +// SPDX-License-Identifier: LGPL-3.0-only + +static inline RzILOpPure *pure_slice(RzILOpPure *x, ut8 l, ut8 r) { + rz_return_val_if_fail(l < r, NULL); + return UNSIGNED(r - l, SHIFTR0(x, U16(l))); +} + +#define BITN(x, n) IS_ZERO(UNSIGNED(1, SHIFTR0(x, U32(n)))) +// overflow is not used in status register but just keeping this for future "maybe" use +#define CHECK_OVERFLOW(x, y, res) AND(XOR(MSB(x), MSB(res)), XOR(MSB(y), MSB(DUP(res)))) +#define CHECK_CARRY(x, y, res) OR(AND(MSB(x), MSB(y)), AND(OR(MSB(DUP(x)), MSB(DUP(y))), INV(MSB(res)))) +#define CHECK_BORROW(x, y, res) OR(OR(AND(INV(MSB(x)), MSB(y)), AND(INV(MSB(DUP(x))), MSB(res))), AND(MSB(DUP(x)), AND(MSB(DUP(y)), MSB(DUP(res))))) +#define CHECK_DIGIT_CARRY(x, y, res) OR(AND(BITN(x, 3), BITN(y, 3)), AND(OR(BITN(DUP(x), 3), BITN(DUP(y), 3)), INV(BITN(res, 3)))) +#define CHECK_DIGIT_BORROW(x, y, res) OR( \ + OR(AND(INV(BITN(x, 3)), BITN(y, 3)), AND(INV(BITN(DUP(x), 3)), BITN(res, 3))), \ + AND(BITN(DUP(x), 3), AND(BITN(DUP(y), 3), BITN(DUP(res), 3)))) + +static inline RzILOpPure *bit_set(RzILOpPure *v, ut32 b, bool x) { + if (x) { + return LOGOR(v, U8(1 << b)); + } + return LOGAND(v, U8(~(1 << b))); +} + +static inline RzILOpPure *bit_set1(RzILOpPure *v, ut32 b, RzILOpBool *x) { + return ITE(x, LOGOR(v, U8(1 << b)), LOGAND(DUP(v), U8(~(1 << b)))); +} + +static inline RzILOpPure *bit_get(RzILOpPure *v, ut32 b) { + return NON_ZERO(LOGAND(v, U8(1 << b))); +} + +#define regbit_set(reg, b, x) SETG(reg, bit_set(VARG(reg), b, x)) +#define regbit_set1(reg, b, x) SETG(reg, bit_set1(VARG(reg), b, x)) diff --git a/librz/arch/isa/pic/pic_midrange.c b/librz/arch/isa/pic/pic_midrange.c deleted file mode 100644 index f9eb62ee917..00000000000 --- a/librz/arch/isa/pic/pic_midrange.c +++ /dev/null @@ -1,249 +0,0 @@ -// SPDX-FileCopyrightText: 2018 courk -// SPDX-License-Identifier: LGPL-3.0-only - -#include "pic_midrange.h" - -static const PicMidrangeOpInfo - pic_midrange_op_info[PIC_MIDRANGE_OPCODE_INVALID] = { - { "nop", PIC_MIDRANGE_OP_ARGS_NONE }, - { "return", PIC_MIDRANGE_OP_ARGS_NONE }, - { "retfie", PIC_MIDRANGE_OP_ARGS_NONE }, - { "option", PIC_MIDRANGE_OP_ARGS_NONE }, - { "sleep", PIC_MIDRANGE_OP_ARGS_NONE }, - { "clrwdt", PIC_MIDRANGE_OP_ARGS_NONE }, - { "tris", PIC_MIDRANGE_OP_ARGS_2F }, - { "movwf", PIC_MIDRANGE_OP_ARGS_7F }, - { "clr", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "subwf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "decf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "iorwf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "andwf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "xorwf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "addwf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "movf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "comf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "incf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "decfsz", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "rrf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "rlf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "swapf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "incfsz", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "bcf", PIC_MIDRANGE_OP_ARGS_3B_7F }, - { "bsf", PIC_MIDRANGE_OP_ARGS_3B_7F }, - { "btfsc", PIC_MIDRANGE_OP_ARGS_3B_7F }, - { "btfss", PIC_MIDRANGE_OP_ARGS_3B_7F }, - { "call", PIC_MIDRANGE_OP_ARGS_11K }, - { "goto", PIC_MIDRANGE_OP_ARGS_11K }, - { "movlw", PIC_MIDRANGE_OP_ARGS_8K }, - { "retlw", PIC_MIDRANGE_OP_ARGS_8K }, - { "iorlw", PIC_MIDRANGE_OP_ARGS_8K }, - { "andlw", PIC_MIDRANGE_OP_ARGS_8K }, - { "xorlw", PIC_MIDRANGE_OP_ARGS_8K }, - { "sublw", PIC_MIDRANGE_OP_ARGS_8K }, - { "addlw", PIC_MIDRANGE_OP_ARGS_8K }, - { "reset", PIC_MIDRANGE_OP_ARGS_NONE }, - { "callw", PIC_MIDRANGE_OP_ARGS_NONE }, - { "brw", PIC_MIDRANGE_OP_ARGS_NONE }, - { "moviw", PIC_MIDRANGE_OP_ARGS_1N_2M }, - { "movwi", PIC_MIDRANGE_OP_ARGS_1N_2M }, - { "movlb", PIC_MIDRANGE_OP_ARGS_4K }, - { "lslf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "lsrf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "asrf", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "subwfb", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "addwfc", PIC_MIDRANGE_OP_ARGS_1D_7F }, - { "addfsr", PIC_MIDRANGE_OP_ARGS_1N_6K }, - { "movlp", PIC_MIDRANGE_OP_ARGS_7F }, - { "bra", PIC_MIDRANGE_OP_ARGS_9K }, - { "moviw", PIC_MIDRANGE_OP_ARGS_1N_6K }, - { "movwi", PIC_MIDRANGE_OP_ARGS_1N_6K } - }; - -static const char *PicMidrangeFsrOps[] = { "++FSR%d", "--FSR%d", "FSR%d++", - "FSR%d--" }; - -PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr) { - if (instr & (1 << 14)) { - return PIC_MIDRANGE_OPCODE_INVALID; - } - - switch (instr >> 11) { // 3 first MSB bits - case 0x4: return PIC_MIDRANGE_OPCODE_CALL; - case 0x5: return PIC_MIDRANGE_OPCODE_GOTO; - } - - switch (instr >> 10) { // 4 first MSB bits - case 0x4: return PIC_MIDRANGE_OPCODE_BCF; - case 0x5: return PIC_MIDRANGE_OPCODE_BSF; - case 0x6: return PIC_MIDRANGE_OPCODE_BTFSC; - case 0x7: return PIC_MIDRANGE_OPCODE_BTFSS; - } - - switch (instr >> 9) { // 5 first MSB bits - case 0x19: return PIC_MIDRANGE_OPCODE_BRA; - } - - switch (instr >> 8) { // 6 first MSB bits - case 0x1: return PIC_MIDRANGE_OPCODE_CLR; - case 0x2: return PIC_MIDRANGE_OPCODE_SUBWF; - case 0x3: return PIC_MIDRANGE_OPCODE_DECF; - case 0x4: return PIC_MIDRANGE_OPCODE_IORWF; - case 0x5: return PIC_MIDRANGE_OPCODE_ANDWF; - case 0x6: return PIC_MIDRANGE_OPCODE_XORWF; - case 0x7: return PIC_MIDRANGE_OPCODE_ADDWF; - case 0x8: return PIC_MIDRANGE_OPCODE_MOVF; - case 0x9: return PIC_MIDRANGE_OPCODE_COMF; - case 0xa: return PIC_MIDRANGE_OPCODE_INCF; - case 0xb: return PIC_MIDRANGE_OPCODE_DECFSZ; - case 0xc: return PIC_MIDRANGE_OPCODE_RRF; - case 0xd: return PIC_MIDRANGE_OPCODE_RLF; - case 0xe: return PIC_MIDRANGE_OPCODE_SWAPF; - case 0xf: return PIC_MIDRANGE_OPCODE_INCFSZ; - case 0x38: return PIC_MIDRANGE_OPCODE_IORLW; - case 0x39: return PIC_MIDRANGE_OPCODE_ANDLW; - case 0x3a: return PIC_MIDRANGE_OPCODE_XORLW; - case 0x30: return PIC_MIDRANGE_OPCODE_MOVLW; - case 0x34: return PIC_MIDRANGE_OPCODE_RETLW; - case 0x3c: return PIC_MIDRANGE_OPCODE_SUBLW; - case 0x3e: return PIC_MIDRANGE_OPCODE_ADDLW; - case 0x35: return PIC_MIDRANGE_OPCODE_LSLF; - case 0x36: return PIC_MIDRANGE_OPCODE_LSRF; - case 0x37: return PIC_MIDRANGE_OPCODE_ASRF; - case 0x3b: return PIC_MIDRANGE_OPCODE_SUBWFB; - case 0x3d: return PIC_MIDRANGE_OPCODE_ADDWFC; - } - - switch (instr >> 7) { // 7 first MSB bits - case 0x1: return PIC_MIDRANGE_OPCODE_MOVWF; - case 0x62: return PIC_MIDRANGE_OPCODE_ADDFSR; - case 0x63: return PIC_MIDRANGE_OPCODE_MOVLP; - case 0x7e: return PIC_MIDRANGE_OPCODE_MOVIW_2; - case 0x7f: return PIC_MIDRANGE_OPCODE_MOVWI_2; - } - - switch (instr >> 5) { // 9 first MSB bits - case 0x1: return PIC_MIDRANGE_OPCODE_MOVLB; - } - - switch (instr >> 3) { // 11 first MSB bits - case 0x2: return PIC_MIDRANGE_OPCODE_MOVIW_1; - case 0x3: return PIC_MIDRANGE_OPCODE_MOVWI_1; - } - - switch (instr >> 2) { // 12 first MSB bits - case 0x19: return PIC_MIDRANGE_OPCODE_TRIS; - } - - switch (instr) { - case 0x0: return PIC_MIDRANGE_OPCODE_NOP; - case 0x1: return PIC_MIDRANGE_OPCODE_RESET; - case 0xa: return PIC_MIDRANGE_OPCODE_CALLW; - case 0xb: return PIC_MIDRANGE_OPCODE_BRW; - case 0x8: return PIC_MIDRANGE_OPCODE_RETURN; - case 0x9: return PIC_MIDRANGE_OPCODE_RETFIE; - case 0x62: return PIC_MIDRANGE_OPCODE_OPTION; - case 0x63: return PIC_MIDRANGE_OPCODE_SLEEP; - case 0x64: return PIC_MIDRANGE_OPCODE_CLRWDT; - } - - return PIC_MIDRANGE_OPCODE_INVALID; -} - -const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode) { - if (opcode >= PIC_MIDRANGE_OPCODE_INVALID) { - return NULL; - } - return &pic_midrange_op_info[opcode]; -} - -int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l) { - char fsr_op[6]; - st16 branch; - -#define EMIT_INVALID \ - { \ - op->size = 2; \ - rz_asm_op_set_asm(op, "invalid"); \ - return 1; \ - } - if (!b || l < 2) { - EMIT_INVALID - } - - ut16 instr = rz_read_le16(b); - PicMidrangeOpcode opcode = pic_midrange_get_opcode(instr); - if (opcode == PIC_MIDRANGE_OPCODE_INVALID) { - EMIT_INVALID - } - - const PicMidrangeOpInfo *op_info = pic_midrange_get_op_info(opcode); - if (!op_info) { - EMIT_INVALID - } - -#undef EMIT_INVALID - - op->size = 2; - - switch (op_info->args) { - case PIC_MIDRANGE_OP_ARGS_NONE: - rz_asm_op_set_asm(op, op_info->mnemonic); - break; - case PIC_MIDRANGE_OP_ARGS_2F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F); - break; - case PIC_MIDRANGE_OP_ARGS_7F: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F); - break; - case PIC_MIDRANGE_OP_ARGS_1D_7F: - rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic, - instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F, - (instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D) >> 7 ? 'f' : 'w'); - break; - case PIC_MIDRANGE_OP_ARGS_1N_6K: - if (opcode == PIC_MIDRANGE_OPCODE_ADDFSR) { - rz_asm_op_setf_asm(op, "%s FSR%d, 0x%x", op_info->mnemonic, - (instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> - 6, - instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K); - } else { - rz_asm_op_setf_asm(op, "%s 0x%x[FSR%d]", op_info->mnemonic, - instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K, - (instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> 6); - } - break; - case PIC_MIDRANGE_OP_ARGS_3B_7F: - rz_asm_op_setf_asm(op, "%s 0x%x, %d", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F, - (instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B) >> 7); - break; - case PIC_MIDRANGE_OP_ARGS_4K: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K); - break; - case PIC_MIDRANGE_OP_ARGS_8K: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K); - break; - case PIC_MIDRANGE_OP_ARGS_9K: - branch = (instr & PIC_MIDRANGE_OP_ARGS_9K_MASK_K); - branch |= ((branch & 0x100) ? 0xfe00 : 0); - rz_asm_op_setf_asm(op, "%s %s0x%x", - op_info->mnemonic, branch < 0 ? "-" : "", - branch < 0 ? -branch : branch); - break; - case PIC_MIDRANGE_OP_ARGS_11K: - rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K); - break; - case PIC_MIDRANGE_OP_ARGS_1N_2M: - snprintf( - fsr_op, sizeof(fsr_op), - PicMidrangeFsrOps[instr & - PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M], - (instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N) >> 2); - rz_asm_op_setf_asm(op, "%s %s", op_info->mnemonic, fsr_op); - break; - default: - rz_asm_op_set_asm(op, "invalid"); - break; - } - - return op->size; -} diff --git a/librz/arch/isa/pic/pic_midrange.h b/librz/arch/isa/pic/pic_midrange.h deleted file mode 100644 index 7384fda67e9..00000000000 --- a/librz/arch/isa/pic/pic_midrange.h +++ /dev/null @@ -1,104 +0,0 @@ -// SPDX-FileCopyrightText: 2018 courk -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef PIC_MIDRANGE_H -#define PIC_MIDRANGE_H - -#include -#include - -typedef enum { - PIC_MIDRANGE_OP_ARGS_NONE = 0, - PIC_MIDRANGE_OP_ARGS_2F, - PIC_MIDRANGE_OP_ARGS_7F, - PIC_MIDRANGE_OP_ARGS_1D_7F, - PIC_MIDRANGE_OP_ARGS_1N_6K, - PIC_MIDRANGE_OP_ARGS_3B_7F, - PIC_MIDRANGE_OP_ARGS_4K, - PIC_MIDRANGE_OP_ARGS_8K, - PIC_MIDRANGE_OP_ARGS_9K, - PIC_MIDRANGE_OP_ARGS_11K, - PIC_MIDRANGE_OP_ARGS_1N_2M -} PicMidrangeOpArgs; - -#define PIC_MIDRANGE_OP_ARGS_2F_MASK_F 0x3 -#define PIC_MIDRANGE_OP_ARGS_7F_MASK_F 0x7f -#define PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D (1 << 7) -#define PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F 0x7f -#define PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N (1 << 6) -#define PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K 0x3f -#define PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B (0x7 << 7) -#define PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F 0x7f -#define PIC_MIDRANGE_OP_ARGS_4K_MASK_K 0xf -#define PIC_MIDRANGE_OP_ARGS_8K_MASK_K 0xff -#define PIC_MIDRANGE_OP_ARGS_9K_MASK_K 0x1ff -#define PIC_MIDRANGE_OP_ARGS_11K_MASK_K 0x7ff -#define PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N (1 << 2) -#define PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M 0x3 - -typedef struct _pic_midrange_op { - const char *mnemonic; - PicMidrangeOpArgs args; -} PicMidrangeOpInfo; - -typedef enum { - PIC_MIDRANGE_OPCODE_NOP = 0, - PIC_MIDRANGE_OPCODE_RETURN, - PIC_MIDRANGE_OPCODE_RETFIE, - PIC_MIDRANGE_OPCODE_OPTION, - PIC_MIDRANGE_OPCODE_SLEEP, - PIC_MIDRANGE_OPCODE_CLRWDT, - PIC_MIDRANGE_OPCODE_TRIS, - PIC_MIDRANGE_OPCODE_MOVWF, - PIC_MIDRANGE_OPCODE_CLR, - PIC_MIDRANGE_OPCODE_SUBWF, - PIC_MIDRANGE_OPCODE_DECF, - PIC_MIDRANGE_OPCODE_IORWF, - PIC_MIDRANGE_OPCODE_ANDWF, - PIC_MIDRANGE_OPCODE_XORWF, - PIC_MIDRANGE_OPCODE_ADDWF, - PIC_MIDRANGE_OPCODE_MOVF, - PIC_MIDRANGE_OPCODE_COMF, - PIC_MIDRANGE_OPCODE_INCF, - PIC_MIDRANGE_OPCODE_DECFSZ, - PIC_MIDRANGE_OPCODE_RRF, - PIC_MIDRANGE_OPCODE_RLF, - PIC_MIDRANGE_OPCODE_SWAPF, - PIC_MIDRANGE_OPCODE_INCFSZ, - PIC_MIDRANGE_OPCODE_BCF, - PIC_MIDRANGE_OPCODE_BSF, - PIC_MIDRANGE_OPCODE_BTFSC, - PIC_MIDRANGE_OPCODE_BTFSS, - PIC_MIDRANGE_OPCODE_CALL, - PIC_MIDRANGE_OPCODE_GOTO, - PIC_MIDRANGE_OPCODE_MOVLW, - PIC_MIDRANGE_OPCODE_RETLW, - PIC_MIDRANGE_OPCODE_IORLW, - PIC_MIDRANGE_OPCODE_ANDLW, - PIC_MIDRANGE_OPCODE_XORLW, - PIC_MIDRANGE_OPCODE_SUBLW, - PIC_MIDRANGE_OPCODE_ADDLW, - PIC_MIDRANGE_OPCODE_RESET, - PIC_MIDRANGE_OPCODE_CALLW, - PIC_MIDRANGE_OPCODE_BRW, - PIC_MIDRANGE_OPCODE_MOVIW_1, - PIC_MIDRANGE_OPCODE_MOVWI_1, - PIC_MIDRANGE_OPCODE_MOVLB, - PIC_MIDRANGE_OPCODE_LSLF, - PIC_MIDRANGE_OPCODE_LSRF, - PIC_MIDRANGE_OPCODE_ASRF, - PIC_MIDRANGE_OPCODE_SUBWFB, - PIC_MIDRANGE_OPCODE_ADDWFC, - PIC_MIDRANGE_OPCODE_ADDFSR, - PIC_MIDRANGE_OPCODE_MOVLP, - PIC_MIDRANGE_OPCODE_BRA, - PIC_MIDRANGE_OPCODE_MOVIW_2, - PIC_MIDRANGE_OPCODE_MOVWI_2, - PIC_MIDRANGE_OPCODE_INVALID -} PicMidrangeOpcode; - -PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr); -const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode); -int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l); - -#endif // PIC_MIDRANGE_H diff --git a/librz/arch/isa/pic/pic_pic18.c b/librz/arch/isa/pic/pic_pic18.c deleted file mode 100644 index 7c19fe4872d..00000000000 --- a/librz/arch/isa/pic/pic_pic18.c +++ /dev/null @@ -1,221 +0,0 @@ -// SPDX-FileCopyrightText: 2015-2018 oddcoder -// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r -// SPDX-License-Identifier: LGPL-3.0-only - -#include - -#include "pic_pic18.h" - -// PIC18CXXX instruction set - -// instruction classification according to the argument types -#define NO_ARG 0 -#define DAF_T 1 -#define F32_T 2 -#define BAF_T 3 -#define K_T 4 -#define N_T 5 -#define CALL_T 6 -#define NEX_T 7 -#define AF_T 8 -#define GOTO_T 9 -#define SHK_T 10 -#define S_T 11 -#define LFSR_T 12 - -static char *fsr[] = { "fsr0", "fsr1", "fsr2", "reserved" }; - -static struct { - ut16 opmin; - ut16 opmax; - char *name; - ut8 optype; - // and some magical hocus pocus ;) -} ops[] = { - { 0xf000, 0xffff, "nop", NO_ARG }, - { 0xef00, 0xefff, "goto", GOTO_T }, - { 0xee00, 0xee3f, "lfsr", LFSR_T }, - { 0xec00, 0xedff, "call", CALL_T }, - { 0xe700, 0xe7ff, "bnn", N_T }, - { 0xe600, 0xe6ff, "bn", N_T }, - { 0xe500, 0xe5ff, "bnov", N_T }, - { 0xe400, 0xe4ff, "bov", N_T }, - { 0xe300, 0xe3ff, "bnc", N_T }, - { 0xe200, 0xe2ff, "bc", N_T }, - { 0xe100, 0xe1ff, "bnz", N_T }, - { 0xe000, 0xe0ff, "bz", N_T }, - { 0xd800, 0xdfff, "rcall", NEX_T }, - { 0xd000, 0xd7ff, "bra", NEX_T }, - { 0xc000, 0xcfff, "movff", F32_T }, - { 0xb000, 0xbfff, "btfsc", BAF_T }, - { 0xa000, 0xafff, "btfss", BAF_T }, - { 0x9000, 0x9fff, "bcf", BAF_T }, - { 0x8000, 0x8fff, "bsf", BAF_T }, - { 0x7000, 0x7fff, "btg", BAF_T }, - { 0x6e00, 0x6fff, "movwf", AF_T }, - { 0x6c00, 0x6dff, "negf", AF_T }, - { 0x6a00, 0x6bff, "clrf", AF_T }, - { 0x6800, 0x69ff, "setf", AF_T }, - { 0x6600, 0x67ff, "tstfsz", AF_T }, - { 0x6400, 0x65ff, "cpfsgt", AF_T }, - { 0x6200, 0x63ff, "cpfseq", AF_T }, - { 0x6000, 0x61ff, "cpfslt", AF_T }, - { 0x5c00, 0x5fff, "subwf", DAF_T }, - { 0x5800, 0x5bff, "subwfb", DAF_T }, - { 0x5400, 0x57ff, "subfwb", DAF_T }, - { 0x5000, 0x53ff, "movf", DAF_T }, - { 0x4c00, 0x4fff, "dcfsnz", DAF_T }, - { 0x4800, 0x4bff, "infsnz", DAF_T }, - { 0x4400, 0x47ff, "rlncf", DAF_T }, - { 0x4000, 0x43ff, "rrncf", DAF_T }, - { 0x3c00, 0x3fff, "incfsz", DAF_T }, - { 0x3800, 0x3bff, "swapf", DAF_T }, - { 0x3400, 0x37ff, "rlcf", DAF_T }, - { 0x3000, 0x33ff, "rrcf", DAF_T }, - { 0x2c00, 0x2fff, "decfsz", DAF_T }, - { 0x2800, 0x2bff, "incf", DAF_T }, - { 0x2400, 0x27ff, "addwf", DAF_T }, - { 0x2000, 0x23ff, "addwfc", DAF_T }, - { 0x1c00, 0x1fff, "comf", DAF_T }, - { 0x1800, 0x1bff, "xorwf", DAF_T }, - { 0x1400, 0x17ff, "andwf", DAF_T }, - { 0x1000, 0x13ff, "iorwf", DAF_T }, - { 0xf00, 0xfff, "addlw", K_T }, - { 0xe00, 0xeff, "movlw", K_T }, - { 0xd00, 0xdff, "mullw", K_T }, - { 0xc00, 0xcff, "retlw", K_T }, - { 0xb00, 0xbff, "andlw", K_T }, - { 0xa00, 0xaff, "xorlw", K_T }, - { 0x900, 0x9ff, "iorlw", K_T }, - { 0x800, 0x8ff, "sublw", K_T }, - { 0x400, 0x7ff, "decf", DAF_T }, - { 0x200, 0x3ff, "mulwf", AF_T }, - { 0x100, 0x10f, "movlb", SHK_T }, - { 0xff, 0xff, "reset", NO_ARG }, - { 0x12, 0x13, "return", S_T }, - { 0x10, 0x11, "retfie", S_T }, - { 0xf, 0xf, "tblwt+*", NO_ARG }, - { 0xe, 0xe, "tblwt*-", NO_ARG }, - { 0xd, 0xd, "tblwt*+", NO_ARG }, - { 0xc, 0xc, "tblwt*", NO_ARG }, - { 0xb, 0xb, "tblrd+*", NO_ARG }, - { 0xa, 0xa, "tblrd*-", NO_ARG }, - { 0x9, 0x9, "tblrd*+", NO_ARG }, - { 0x8, 0x8, "tblrd*", NO_ARG }, - { 0x7, 0x7, "daw", NO_ARG }, - { 0x6, 0x6, "pop", NO_ARG }, - { 0x5, 0x5, "push", NO_ARG }, - { 0x4, 0x4, "clrwdt", NO_ARG }, - { 0x3, 0x3, "sleep", NO_ARG }, - { 0x0, 0x0, "nop", NO_ARG }, - { 0x0, 0xffff, "invalid", NO_ARG }, -}; - -int pic_pic18_disassemble(RzAsmOp *op, const ut8 *b, int blen) { - int i; - if (blen < 2) { // well noone loves reading bitstream of size zero or 1 !! - rz_asm_op_set_asm(op, "invalid"); - op->size = blen; - return -1; - } - ut16 instr = rz_read_le16(b); // instruction - // if still redundant code is reported think of this of instr=0x - - for (i = 0; ops[i].opmin != (ops[i].opmin & instr) || ops[i].opmax != (ops[i].opmax | instr); i++) { - ; - } - if (ops[i].opmin == 0 && ops[i].opmax == 0xffff) { - rz_asm_op_set_asm(op, ops[i].name); - op->size = 2; - return -1; - } - op->size = 2; - switch (ops[i].optype) { - case NO_ARG: - rz_asm_op_set_asm(op, ops[i].name); - break; - case N_T: - case K_T: - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xff); - break; - case DAF_T: - rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 1, (instr >> 8) & 1); - break; - case AF_T: - rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name, instr & 0xff, (instr >> 8) & 1); - break; - case BAF_T: - rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 0x7, (instr >> 8) & 0x1); - break; - case NEX_T: - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0x7ff); - break; - case CALL_T: - if (blen < 4) { - return -1; - } - op->size = 4; - { - ut32 dword_instr = rz_read_le32(b); - // I dont even know how the bits are arranged but it works !!! - //`the wierdness of little endianess` - if (dword_instr >> 28 != 0xf) { - return -1; - } - rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name, - (dword_instr & 0xff) | (dword_instr >> 8 & 0xfff00), (dword_instr >> 8) & 0x1); - } - break; - case GOTO_T: - if (blen < 4) { - return -1; - } - { - op->size = 4; - ut32 dword_instr = rz_read_le32(b); - if (dword_instr >> 28 != 0xf) { - return -1; - } - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, - ((dword_instr & 0xff) | ((dword_instr & 0xfff0000) >> 8)) * 2); - } - break; - case F32_T: - if (blen < 4) { - return -1; - } - op->size = 4; - { - ut32 dword_instr = rz_read_le32(b); - if (dword_instr >> 28 != 0xf) { - return -1; - } - rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", ops[i].name, - dword_instr & 0xfff, (dword_instr >> 16) & 0xfff); - } - break; - case SHK_T: - rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xf); - break; - case S_T: - rz_asm_op_setf_asm(op, "%s %d", ops[i].name, instr & 0x1); - break; - case LFSR_T: { - if (blen < 4) { - return -1; - } - op->size = 4; - ut32 dword_instr = rz_read_le32(b); - if (dword_instr >> 28 != 0xf) { - return -1; - } - ut8 reg_n = (dword_instr >> 4) & 0x3; - rz_asm_op_setf_asm(op, "%s %s, %d", ops[i].name, fsr[reg_n], - (dword_instr & 0xf) << 8 | ((dword_instr >> 16) & 0xff)); - break; - } - default: - rz_asm_op_set_asm(op, "unknown args"); - }; - return op->size; -} diff --git a/librz/arch/isa/pic/pic_pic18.h b/librz/arch/isa/pic/pic_pic18.h deleted file mode 100644 index ca17c8402b3..00000000000 --- a/librz/arch/isa/pic/pic_pic18.h +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-FileCopyrightText: 2015-2018 oddcoder -// SPDX-FileCopyrightText: 2015-2018 thestr4ng3r -// SPDX-License-Identifier: LGPL-3.0-only - -#ifndef PIC_PIC18_H -#define PIC_PIC18_H - -#include - -int pic_pic18_disassemble(RzAsmOp *op, const ut8 *b, int l); - -#endif // PIC_PIC18_H diff --git a/librz/arch/meson.build b/librz/arch/meson.build index 5ac1fee5f14..e367c4def16 100644 --- a/librz/arch/meson.build +++ b/librz/arch/meson.build @@ -220,9 +220,11 @@ arch_isa_sources = [ 'isa/mips/mips_assembler.c', 'isa/msp430/msp430_disas.c', 'isa/or1k/or1k_disas.c', - 'isa/pic/pic_baseline.c', - 'isa/pic/pic_midrange.c', - 'isa/pic/pic_pic18.c', + 'isa/pic/pic14.c', + 'isa/pic/pic16.c', + 'isa/pic/pic18.c', + 'isa/pic/pic16_analysis.c', + 'isa/pic/pic18_analysis.c', 'isa/ppc/libps/libps.c', 'isa/ppc/libvle/vle.c', 'isa/ppc/ppc_il.c', diff --git a/librz/arch/p/analysis/analysis_pic.c b/librz/arch/p/analysis/analysis_pic.c index d27497ef10c..cf4664ccec6 100644 --- a/librz/arch/p/analysis/analysis_pic.c +++ b/librz/arch/p/analysis/analysis_pic.c @@ -5,663 +5,8 @@ #include #include -#include - -#include "pic/pic_midrange.h" - -typedef struct _pic_midrange_op_args_val { - ut16 f; - ut16 k; - ut8 d; - ut8 m; - ut8 n; - ut8 b; -} PicMidrangeOpArgsVal; - -typedef void (*pic_midrange_inst_handler_t)(RzAnalysis *analysis, RzAnalysisOp *op, - ut64 addr, - PicMidrangeOpArgsVal *args); - -typedef struct _pic_midrange_op_analysis_info { - PicMidrangeOpcode opcode; - PicMidrangeOpArgs args; - pic_midrange_inst_handler_t handler; -} PicMidrangeOpAnalInfo; - -#define INST_HANDLER(OPCODE_NAME) \ - void _inst__##OPCODE_NAME(RzAnalysis *analysis, RzAnalysisOp *op, \ - ut64 addr, \ - PicMidrangeOpArgsVal *args) -#define INST_DECL(NAME, ARGS) \ - { \ - PIC_MIDRANGE_OPCODE_##NAME, PIC_MIDRANGE_OP_ARGS_##ARGS, \ - _inst__##NAME \ - } - -#define e(frag) rz_strbuf_append(&op->esil, frag) -#define ef(frag, ...) rz_strbuf_appendf(&op->esil, frag, __VA_ARGS__) - -#define PIC_MIDRANGE_ESIL_SRAM_START (1 << 16) -#define PIC_MIDRANGE_ESIL_CSTACK_TOP ((1 << 16) + (1 << 12)) - -#define PIC_MIDRANGE_ESIL_BSR_ADDR "bsr,0x80,*,0x%x,+,_sram,+" - -#define PIC_MIDRANGE_ESIL_OPTION_ADDR "0x95,_sram,+" - -#define PIC_MIDRANGE_ESIL_UPDATE_FLAGS \ - "$z,z,:=," \ - "7,$c,c,:=," \ - "4,$c,dc,:=," - -#define PIC_MIDRANGE_ESIL_LW_OP(O) \ - "0x%x,wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_FWF_OP(O) \ - "wreg," PIC_MIDRANGE_ESIL_BSR_ADDR "," #O \ - "=[1]," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_WWF_OP(O) \ - PIC_MIDRANGE_ESIL_BSR_ADDR \ - ",[1]," \ - "wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_FWF_OP_C(O) \ - "c,wreg," \ - "+," PIC_MIDRANGE_ESIL_BSR_ADDR "," #O \ - "=[1]," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -#define PIC_MIDRANGE_ESIL_WWF_OP_C(O) \ - "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1]," #O "," \ - "wreg," #O "=," PIC_MIDRANGE_ESIL_UPDATE_FLAGS - -INST_HANDLER(NOP) {} - -INST_HANDLER(RETFIE) { - op->type = RZ_ANALYSIS_OP_TYPE_RET; -} - -INST_HANDLER(OPTION) { - op->type = RZ_ANALYSIS_OP_TYPE_STORE; -} - -INST_HANDLER(TRIS) { - op->type = RZ_ANALYSIS_OP_TYPE_STORE; -} - -INST_HANDLER(RETURN) { - op->type = RZ_ANALYSIS_OP_TYPE_RET; - e("0x1f,stkptr,==,$z,?{,BREAK,},"); - e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); - e("0x01,stkptr,-=,"); - e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); -} - -INST_HANDLER(CALL) { - ut64 pclath; - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); - op->jump = 2 * (((pclath & 0x78) << 8) + args->k); - ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); - e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x01,stkptr,+=,"); - ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); -} - -INST_HANDLER(GOTO) { - ut64 pclath; - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - rz_analysis_esil_reg_read(analysis->esil, "pclath", &pclath, NULL); - op->jump = 2 * (((pclath & 0x78) << 8) + args->k); - ef("8,pclath,0x78,&,<<,0x%x,+,2,*,pc,=,", args->k); -} - -INST_HANDLER(BCF) { - ut8 mask = ~(1 << args->b); - ef(PIC_MIDRANGE_ESIL_BSR_ADDR - ",[1],0x%x,&," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", - args->f, mask, args->f); -} - -INST_HANDLER(BSF) { - ut8 mask = (1 << args->b); - ef(PIC_MIDRANGE_ESIL_BSR_ADDR - ",[1],0x%x,|," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", - args->f, mask, args->f); -} - -INST_HANDLER(BTFSC) { - ut8 mask = (1 << args->b); - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],0x%x,&,!,?{,0x%" PFMT64x ",pc,=,},", - args->f, mask, op->jump); -} - -INST_HANDLER(BTFSS) { - ut8 mask = (1 << args->b); - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],0x%x,&,?{,0x%" PFMT64x ",pc,=,},", args->f, - mask, op->jump); -} - -INST_HANDLER(BRA) { - st16 branch = args->k; - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - branch |= ((branch & 0x100) ? 0xfe00 : 0); - op->jump = addr + 2 * (branch + 1); - ef("%s0x%x,1,+,2,*,pc,+=,", branch < 0 ? "-" : "", - branch < 0 ? -branch : branch); -} - -INST_HANDLER(BRW) { - ut64 wreg; - op->type = RZ_ANALYSIS_OP_TYPE_UJMP; - rz_analysis_esil_reg_read(analysis->esil, "wreg", &wreg, NULL); - op->jump = addr + 2 * (wreg + 1); - e("wreg,1,+,2,*,pc,+=,"); -} - -INST_HANDLER(CLR) { - if (args->d) { - ef("0x00," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); - } else { - e("0x00,wreg,=,"); - } - e("1,z,=,"); -} - -INST_HANDLER(SUBWF) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(-), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(-), args->f); - e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); - } -} - -INST_HANDLER(DECFSZ) { - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",-=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],-,wreg,=,", - args->f); - } - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, - op->jump); -} - -INST_HANDLER(INCFSZ) { - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 4; - op->fail = addr + 2; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",+=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],+,wreg,=,", - args->f); - } - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],!,?{,0x%" PFMT64x ",pc,=,},", args->f, - op->jump); -} - -INST_HANDLER(INCF) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",+=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],+,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(DECF) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - if (args->d) { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",-=[1],", args->f); - } else { - ef("0x01," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],-,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(IORWF) { - op->type = RZ_ANALYSIS_OP_TYPE_OR; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(|), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(|), args->f); - } -} - -INST_HANDLER(ANDWF) { - op->type = RZ_ANALYSIS_OP_TYPE_AND; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(&), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(&), args->f); - } -} - -INST_HANDLER(XORWF) { - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(^), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(^), args->f); - } -} - -INST_HANDLER(ADDWF) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP(+), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP(+), args->f); - } -} - -INST_HANDLER(SUBLW) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - ef(PIC_MIDRANGE_ESIL_LW_OP(-), args->k); -} - -INST_HANDLER(ADDLW) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - ef(PIC_MIDRANGE_ESIL_LW_OP(+), args->k); -} - -INST_HANDLER(IORLW) { - op->type = RZ_ANALYSIS_OP_TYPE_OR; - ef(PIC_MIDRANGE_ESIL_LW_OP(|), args->k); -} - -INST_HANDLER(ANDLW) { - op->type = RZ_ANALYSIS_OP_TYPE_AND; - ef(PIC_MIDRANGE_ESIL_LW_OP(&), args->k); -} - -INST_HANDLER(XORLW) { - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - ef(PIC_MIDRANGE_ESIL_LW_OP(^), args->k); -} - -INST_HANDLER(MOVLW) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - ef("0x%x,wreg,=,", args->k); -} - -INST_HANDLER(RETLW) { - op->type = RZ_ANALYSIS_OP_TYPE_RET; - ef("0x%x,wreg,=,", args->k); - e("0x1f,stkptr,==,$z,?{,BREAK,},"); - e("_stack,stkptr,2,*,+,[2],2,*,pc,=,"); - e("0x01,stkptr,-=,"); - e("0xff,stkptr,==,$z,?{,0x1f,stkptr,=,},"); -} - -INST_HANDLER(MOVLP) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - ef("0x%x,pclath,=,", args->f); -} - -INST_HANDLER(MOVLB) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - ef("0x%x,bsr,=,", args->k); -} - -INST_HANDLER(CALLW) { - op->type = RZ_ANALYSIS_OP_TYPE_UCALL; - e("8,pclath,<<,0x%x,+,wreg,2,*,pc,=,"); - e("0x1f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x0f,stkptr,==,$z,?{,0xff,stkptr,=,},"); - e("0x01,stkptr,+=,"); - ef("0x%" PFMT64x ",_stack,stkptr,2,*,+,=[2],", (addr + 2) / 2); -} - -INST_HANDLER(MOVWF) { - op->type = RZ_ANALYSIS_OP_TYPE_STORE; - ef("wreg," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); -} - -INST_HANDLER(MOVF) { - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_BSR_ADDR - ",[1]," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", - args->f, args->f); - } else { - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],wreg,=,", args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(SWAPF) { - ef("4," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,0x0f,&,", args->f); - ef("4," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,0xf0,&,", args->f); - e("|,"); - ef(PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); -} - -INST_HANDLER(LSLF) { - op->type = RZ_ANALYSIS_OP_TYPE_SHL; - ef("7," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,c,=,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",<<=[1],", args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(LSRF) { - op->type = RZ_ANALYSIS_OP_TYPE_SHR; - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",>>=[1],", args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,wreg,=,", - args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(ASRF) { - op->type = RZ_ANALYSIS_OP_TYPE_SHR; - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,c,=,", args->f); - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,", args->f); - ef("0x80," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,", args->f); - if (args->d) { - ef("|," PIC_MIDRANGE_ESIL_BSR_ADDR ",=[1],", args->f); - } else { - e("|,wreg,=,"); - } - e("$z,z,:=,"); -} - -INST_HANDLER(RRF) { - op->type = RZ_ANALYSIS_OP_TYPE_ROR; - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],&,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",>>=[1]," - "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",|=[1],", - args->f, args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,wreg,=," - "c,wreg,|=[1],", - args->f); - } - e("c,=,"); -} - -INST_HANDLER(RLF) { - op->type = RZ_ANALYSIS_OP_TYPE_ROL; - ef("7," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],>>,", args->f); - if (args->d) { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",<<=[1]," - "c," PIC_MIDRANGE_ESIL_BSR_ADDR ",|=[1],", - args->f, args->f); - } else { - ef("1," PIC_MIDRANGE_ESIL_BSR_ADDR ",[1],<<,wreg,=," - "c,wreg,|=[1],", - args->f); - } - e("c,=,"); -} - -INST_HANDLER(COMF) { - if (args->d) { - ef("0xff," PIC_MIDRANGE_ESIL_BSR_ADDR ",^=[1],", args->f); - } else { - ef("0xff," PIC_MIDRANGE_ESIL_BSR_ADDR ",^,wreg,=,", args->f); - } - e("$z,z,:=,"); -} - -INST_HANDLER(RESET) { - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->jump = 0; - e("0x0,pc,=,"); - e("0x1f,stkptr,=,"); -} - -INST_HANDLER(ADDFSR) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->n == 0) { - ef("0x%x,fsr0l,+=,", args->k); - e("7,$c,?{,0x01,fsr0h,+=,},"); - } else { - ef("0x%x,fsr1l,+=,", args->k); - e("7,$c,?{,0x01,fsr1h,+=,},"); - } -} - -INST_HANDLER(CLRWDT) { - e("1,to,=,"); - e("1,pd,=,"); -} - -INST_HANDLER(SLEEP) { - e("1,to,=,"); - e("0,pd,=,"); -} - -INST_HANDLER(SUBWFB) { - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - e("c,!=,"); - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP_C(-), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP_C(-), args->f); - e("wreg,0x00,-,wreg,=,c,!=,dc,!=,"); - } -} - -INST_HANDLER(ADDWFC) { - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - if (args->d) { - ef(PIC_MIDRANGE_ESIL_FWF_OP_C(+), args->f); - } else { - ef(PIC_MIDRANGE_ESIL_WWF_OP_C(+), args->f); - } -} - -INST_HANDLER(MOVIW_1) { - if (args->n == 0) { - if (!(args->m & 2)) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - e("indf0,wreg,=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } else { - if (!(args->m & 2)) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - e("indf1,wreg,=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("7,$c%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } -} - -INST_HANDLER(MOVWI_1) { - if (args->n == 0) { - if (!(args->m & 2)) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - e("wreg,indf0=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr0l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7%s,fsr0h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } else { - if (!(args->m & 2)) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7,fsr1h,%s,", (args->m & 1) ? ",!" : ""); - } - e("wreg,indf1=,"); - e("$z,z,:=,"); - if (args->m & 2) { - ef("1,fsr1l,%s=,", (args->m & 1) ? "-" : "+"); - ef("$c7%s,fsr1h,%s,", (args->m & 1) ? ",!" : "", - (args->m & 1) ? "-" : "+"); - } - } -} - -INST_HANDLER(MOVIW_2) { - if (args->n == 0) { - e("fsr0l,8,fsr0h,<<,+,"); - } else { - e("fsr1l,8,fsr1h,<<,+,"); - } - ef("0x%x,+,[1],wreg,=,", args->k); -} - -INST_HANDLER(MOVWI_2) { - e("wreg,"); - if (args->n == 0) { - e("fsr0l,8,fsr0h,<<,+,"); - } else { - e("fsr1l,8,fsr1h,<<,+,"); - } - e("=[1],"); -} - -#define PIC_MIDRANGE_OPINFO_LEN 52 -static const PicMidrangeOpAnalInfo pic_midrange_op_analysis_info[PIC_MIDRANGE_OPINFO_LEN] = { - INST_DECL(NOP, NONE), INST_DECL(RETURN, NONE), - INST_DECL(RETFIE, NONE), INST_DECL(OPTION, NONE), - INST_DECL(SLEEP, NONE), INST_DECL(CLRWDT, NONE), - INST_DECL(TRIS, 2F), INST_DECL(MOVWF, 7F), - INST_DECL(CLR, 1D_7F), INST_DECL(SUBWF, 1D_7F), - INST_DECL(DECF, 1D_7F), INST_DECL(IORWF, 1D_7F), - INST_DECL(ANDWF, 1D_7F), INST_DECL(XORWF, 1D_7F), - INST_DECL(ADDWF, 1D_7F), INST_DECL(MOVF, 1D_7F), - INST_DECL(COMF, 1D_7F), INST_DECL(INCF, 1D_7F), - INST_DECL(DECFSZ, 1D_7F), INST_DECL(RRF, 1D_7F), - INST_DECL(RLF, 1D_7F), INST_DECL(SWAPF, 1D_7F), - INST_DECL(INCFSZ, 1D_7F), INST_DECL(BCF, 3B_7F), - INST_DECL(BSF, 3B_7F), INST_DECL(BTFSC, 3B_7F), - INST_DECL(BTFSS, 3B_7F), INST_DECL(CALL, 11K), - INST_DECL(GOTO, 11K), INST_DECL(MOVLW, 8K), - INST_DECL(RETLW, 8K), INST_DECL(IORLW, 8K), - INST_DECL(ANDLW, 8K), INST_DECL(XORLW, 8K), - INST_DECL(SUBLW, 8K), INST_DECL(ADDLW, 8K), - INST_DECL(RESET, NONE), INST_DECL(CALLW, NONE), - INST_DECL(BRW, NONE), INST_DECL(MOVIW_1, 1N_2M), - INST_DECL(MOVWI_1, 1N_2M), INST_DECL(MOVLB, 4K), - INST_DECL(LSLF, 1D_7F), INST_DECL(LSRF, 1D_7F), - INST_DECL(ASRF, 1D_7F), INST_DECL(SUBWFB, 1D_7F), - INST_DECL(ADDWFC, 1D_7F), INST_DECL(ADDFSR, 1N_6K), - INST_DECL(MOVLP, 7F), INST_DECL(BRA, 9K), - INST_DECL(MOVIW_2, 1N_6K), INST_DECL(MOVWI_2, 1N_6K) -}; - -static void analysis_pic_midrange_extract_args(ut16 instr, - PicMidrangeOpArgs args, - PicMidrangeOpArgsVal *args_val) { - - memset(args_val, 0, sizeof(PicMidrangeOpArgsVal)); - - switch (args) { - case PIC_MIDRANGE_OP_ARGS_NONE: return; - case PIC_MIDRANGE_OP_ARGS_2F: - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F; - return; - case PIC_MIDRANGE_OP_ARGS_7F: - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F; - return; - case PIC_MIDRANGE_OP_ARGS_1D_7F: - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F; - args_val->d = - (instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D) >> 7; - return; - case PIC_MIDRANGE_OP_ARGS_1N_6K: - args_val->n = - (instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> 6; - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_3B_7F: - args_val->b = - (instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B) >> 7; - args_val->f = instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F; - return; - case PIC_MIDRANGE_OP_ARGS_4K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_8K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_9K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_9K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_11K: - args_val->k = instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K; - return; - case PIC_MIDRANGE_OP_ARGS_1N_2M: - args_val->n = - (instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N) >> 2; - args_val->m = instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M; - return; - } -} - -static RzIODesc *mem_sram = 0; -static RzIODesc *mem_stack = 0; - -static RzIODesc *cpu_memory_map(RzIOBind *iob, RzIODesc *desc, ut32 addr, - ut32 size) { - char *mstr = rz_str_newf("malloc://%d", size); - if (desc && iob->fd_get_name(iob->io, desc->fd)) { - iob->fd_remap(iob->io, desc->fd, addr); - } else { - desc = iob->open_at(iob->io, mstr, RZ_PERM_RW, 0, addr, NULL); - } - free(mstr); - return desc; -} - -static bool pic_midrange_reg_write(RzReg *reg, const char *regname, ut32 num) { - if (reg) { - RzRegItem *item = rz_reg_get(reg, regname, RZ_REG_TYPE_GPR); - if (item) { - rz_reg_set_value(reg, item, num); - return true; - } - } - return false; -} - -typedef struct { - bool init_done; -} PicContext; +#include "../isa/pic/pic18.h" +#include "../isa/pic/pic16.h" static bool pic_init(void **user) { PicContext *ctx = RZ_NEW0(PicContext); @@ -669,541 +14,85 @@ static bool pic_init(void **user) { return false; } ctx->init_done = false; + ctx->pic18_mm = ht_su_new(HT_STR_CONST); + for (int i = 0; i < 0x80; ++i) { + const char *regname = pic18_regname(i); + ht_su_insert(ctx->pic18_mm, regname, i); + } + for (int i = 0x80; i < 0x100; ++i) { + const char *regname = pic18_regname(i); + ht_su_insert(ctx->pic18_mm, regname, i + 0xf00); + } *user = ctx; return true; } -static void analysis_pic_midrange_malloc(RzAnalysis *analysis, bool force) { - PicContext *ctx = (PicContext *)analysis->plugin_data; - - if (!ctx->init_done || force) { - // Allocate memory as needed. - // We assume that code is already allocated with firmware - // image - mem_sram = - cpu_memory_map(&analysis->iob, mem_sram, - PIC_MIDRANGE_ESIL_SRAM_START, 0x1000); - mem_stack = - cpu_memory_map(&analysis->iob, mem_stack, - PIC_MIDRANGE_ESIL_CSTACK_TOP, 0x20); - - pic_midrange_reg_write(analysis->reg, "_sram", - PIC_MIDRANGE_ESIL_SRAM_START); - pic_midrange_reg_write(analysis->reg, "_stack", - PIC_MIDRANGE_ESIL_CSTACK_TOP); - pic_midrange_reg_write(analysis->reg, "stkptr", 0x1f); - - ctx->init_done = true; +static bool pic_fini(void *user) { + PicContext *ctx = (PicContext *)user; + if (ctx) { + ht_su_free(ctx->pic18_mm); + RZ_FREE(ctx); } + return true; } -static int analysis_pic_midrange_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, - const ut8 *buf, int len) { - - ut16 instr; - int i; - - analysis_pic_midrange_malloc(analysis, false); - - if (!buf || len < 2) { - op->type = RZ_ANALYSIS_OP_TYPE_ILL; - return op->size; +static int analysis_pic_op( + RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, + const ut8 *buf, int len, RzAnalysisOpMask mask) { + if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) { + return pic18_op(analysis, op, addr, buf, len, mask); } - instr = rz_read_le16(buf); - - // Default op params - op->size = 2; - op->cycles = 1; - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - - PicMidrangeOpcode opcode = pic_midrange_get_opcode(instr); - PicMidrangeOpArgsVal args_val; - - for (i = 0; i < PIC_MIDRANGE_OPINFO_LEN; i++) { - if (pic_midrange_op_analysis_info[i].opcode == opcode) { - analysis_pic_midrange_extract_args( - instr, pic_midrange_op_analysis_info[i].args, - &args_val); - pic_midrange_op_analysis_info[i].handler(analysis, op, addr, - &args_val); - break; - } + if (is_pic14_or_pic16(analysis->cpu)) { + return pic16_op(analysis, op, addr, buf, len, mask); } - - return op->size; -} - -static void pic18_cond_branch(RzAnalysisOp *op, ut64 addr, const ut8 *buf, char *flag) { - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - op->jump = addr + 2 + 2 * (*(ut16 *)buf & 0xff); - op->fail = addr + op->size; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "%s,?,{,0x%" PFMT64x ",pc,=,}", flag, op->jump); + return -1; } -static int analysis_pic_pic18_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len) { - // TODO code should be refactored and broken into smaller chunks!! - // TODO complete the esil emitter - if (len < 2) { - op->size = len; - goto beach; // pancake style :P - } - op->size = 2; - ut16 b = *(ut16 *)buf; - ut32 dword_instr = 0; - memcpy(&dword_instr, buf, RZ_MIN(sizeof(dword_instr), len)); - switch (b >> 9) { - case 0x76: // call - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - return op->size; - }; - switch (b >> 11) { // NEX_T - case 0x1b: // rcall - op->type = RZ_ANALYSIS_OP_TYPE_CALL; - return op->size; - case 0x1a: // bra - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - op->cycles = 2; - op->jump = addr + 2 + 2 * (*(ut16 *)buf & 0x7ff); - rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",pc,=", op->jump); - return op->size; +static char *analysis_pic_get_reg_profile(RzAnalysis *analysis) { + if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) { + return pic18_get_reg_profile(analysis); } - switch (b >> 12) { // NOP,movff,BAF_T - case 0xf: // nop - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - op->cycles = 1; - rz_strbuf_setf(&op->esil, ","); - return op->size; - case 0xc: // movff - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->type = RZ_ANALYSIS_OP_TYPE_MOV; - return op->size; - case 0xb: // btfsc - case 0xa: // btfss - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - return op->size; - case 0x9: // bcf - case 0x8: // bsf - case 0x7: // btg - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - }; - switch (b >> 8) { // GOTO_T,N_T,K_T - case 0xe0: // bz - pic18_cond_branch(op, addr, buf, "z"); - return op->size; - case 0xe1: // bnz - pic18_cond_branch(op, addr, buf, "z,!"); - return op->size; - case 0xe3: // bnc - pic18_cond_branch(op, addr, buf, "c,!"); - return op->size; - case 0xe4: // bov - pic18_cond_branch(op, addr, buf, "ov"); - return op->size; - case 0xe5: // bnov - pic18_cond_branch(op, addr, buf, "ov,!"); - return op->size; - case 0xe6: // bn - pic18_cond_branch(op, addr, buf, "n"); - return op->size; - case 0xe7: // bnn - pic18_cond_branch(op, addr, buf, "n,!"); - return op->size; - case 0xe2: // bc - pic18_cond_branch(op, addr, buf, "c"); - return op->size; - case 0xef: // goto - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->cycles = 2; - op->jump = ((dword_instr & 0xff) | ((dword_instr & 0xfff0000) >> 8)) * 2; - rz_strbuf_setf(&op->esil, "0x%" PFMT64x ",pc,=", op->jump); - op->type = RZ_ANALYSIS_OP_TYPE_JMP; - return op->size; - case 0xf: // addlw - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - op->cycles = 1; - // TODO add support for dc flag - rz_strbuf_setf(&op->esil, "0x%x,wreg,+=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xe: // movlw - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xd: // mullw - op->type = RZ_ANALYSIS_OP_TYPE_MUL; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,*,prod,=", *(ut16 *)buf & 0xff); - return op->size; - case 0xc: // retlw - op->type = RZ_ANALYSIS_OP_TYPE_RET; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "0x%x,wreg,=,tos,pc,=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xb: // andlw - op->type = RZ_ANALYSIS_OP_TYPE_AND; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,&=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0xa: // xorlw - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0x9: // iorlw - op->type = RZ_ANALYSIS_OP_TYPE_OR; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,wreg,^=,$z,z,:=,7,$s,n,:=,", *(ut16 *)buf & 0xff); - return op->size; - case 0x8: // sublw - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - op->cycles = 1; - // TODO add support for dc flag - rz_strbuf_setf(&op->esil, "wreg,0x%x,-,wreg,=,$z,z,:=,7,$s,n,:=,7,$c,c,:=,7,$o,ov,:=,", *(ut16 *)buf & 0xff); - return op->size; - }; - - switch (b >> 6) { // LFSR - case 0x3b8: // lfsr - if (len < 4) { - goto beach; - } - if (dword_instr >> 28 != 0xf) { - goto beach; - } - op->size = 4; - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - return op->size; - }; - switch (b >> 10) { // DAF_T - case 0x17: // subwf - case 0x16: // subwfb - case 0x15: // subfwb - case 0x13: // dcfsnz - case 0xb: // decfsz - case 0x1: // decf - op->type = RZ_ANALYSIS_OP_TYPE_SUB; - return op->size; - case 0x14: // movf - op->type = RZ_ANALYSIS_OP_TYPE_MOV; - return op->size; - case 0x12: // infsnz - case 0xf: // incfsz - case 0xa: // incf - case 0x8: // addwfc - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - return op->size; - case 0x9: // addwf - op->cycles = 1; - op->type = RZ_ANALYSIS_OP_TYPE_ADD; - return op->size; - case 0x11: // rlncf - case 0xd: // rlcf - op->type = RZ_ANALYSIS_OP_TYPE_ROL; - return op->size; - case 0x10: // rrncf - case 0xc: // rrcf - op->type = RZ_ANALYSIS_OP_TYPE_ROR; - return op->size; - case 0xe: // swapf - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - case 0x7: // comf - op->type = RZ_ANALYSIS_OP_TYPE_CPL; - return op->size; - case 0x6: // xorwf - op->type = RZ_ANALYSIS_OP_TYPE_XOR; - return op->size; - case 0x5: // andwf - op->type = RZ_ANALYSIS_OP_TYPE_AND; - return op->size; - case 0x4: // iorwf - op->type = RZ_ANALYSIS_OP_TYPE_OR; - return op->size; - }; - switch (b >> 9) { // AF_T - case 0x37: // movwf - op->type = RZ_ANALYSIS_OP_TYPE_STORE; - return op->size; - case 0x36: // negf - case 0x35: // clrf - case 0x34: // setf - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - case 0x33: // tstfsz - op->type = RZ_ANALYSIS_OP_TYPE_CJMP; - return op->size; - case 0x32: // cpfsgt - case 0x31: // cpfseq - case 0x30: // cpfslt - op->type = RZ_ANALYSIS_OP_TYPE_CMP; - return op->size; - case 0x1: // mulwf - op->type = RZ_ANALYSIS_OP_TYPE_MUL; - return op->size; - }; - switch (b >> 4) { - case 0x10: // movlb - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - op->cycles = 1; - rz_strbuf_setf(&op->esil, "0x%x,bsr,=,", *(ut16 *)buf & 0xf); - return op->size; - }; - switch (b) { - case 0xff: // reset - case 0x7: // daw - case 0x4: // clwdt - case 0x3: // sleep - op->type = RZ_ANALYSIS_OP_TYPE_UNK; - return op->size; - case 0x13: // return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "tos,pc,=,"); - return op->size; - case 0x12: // return - op->type = RZ_ANALYSIS_OP_TYPE_RET; - op->cycles = 2; - rz_strbuf_setf(&op->esil, "tos,pc,="); - return op->size; - case 0x11: // retfie - case 0x10: // retfie - op->type = RZ_ANALYSIS_OP_TYPE_RET; - return op->size; - case 0xf: // tblwt - case 0xe: // tblwt - case 0xd: // tblwt - case 0xc: // tblwt - op->type = RZ_ANALYSIS_OP_TYPE_LOAD; - return op->size; - case 0xb: // tblrd - case 0xa: // tblrd - case 0x9: // tblrd - case 0x8: // tblrd - op->type = RZ_ANALYSIS_OP_TYPE_STORE; - return op->size; - case 0x6: // pop - op->type = RZ_ANALYSIS_OP_TYPE_POP; - return op->size; - case 0x5: // push - op->type = RZ_ANALYSIS_OP_TYPE_PUSH; - return op->size; - case 0x0: // nop - op->type = RZ_ANALYSIS_OP_TYPE_NOP; - op->cycles = 1; - rz_strbuf_setf(&op->esil, ","); - return op->size; - }; -beach: - op->type = RZ_ANALYSIS_OP_TYPE_ILL; - return op->size; -} - -static char *analysis_pic_midrange_get_reg_profile(RzAnalysis *esil) { - const char *p = - "=PC pc\n" - "=SP stkptr\n" - "=A0 porta\n" - "=A1 portb\n" - "gpr indf0 .8 0 0\n" - "gpr indf1 .8 1 0\n" - "gpr pcl .8 2 0\n" - "gpr status .8 3 0\n" - "flg c .1 3.0 0\n" - "flg dc .1 3.1 0\n" - "flg z .1 3.2 0\n" - "flg pd .1 3.3 0\n" - "flg to .1 3.4 0\n" - "gpr fsr0l .8 4 0\n" - "gpr fsr0h .8 5 0\n" - "gpr fsr1l .8 6 0\n" - "gpr fsr1h .8 7 0\n" - "gpr bsr .8 8 0\n" - "gpr wreg .8 9 0\n" - "gpr pclath .8 10 0\n" - "gpr intcon .8 11 0\n" - "gpr pc .16 12 0\n" - "gpr stkptr .8 14 0\n" - "gpr _sram .32 15 0\n" - "gpr _stack .32 19 0\n"; - return strdup(p); -} - -static char *analysis_pic_pic18_get_reg_profile(RzAnalysis *esil) { - const char *p = - "#pc lives in nowhere actually" - "=PC pc\n" - "=SP tos\n" - "=A0 porta\n" - "=A1 portb\n" - "gpr pc .32 0 0\n" - "gpr pcl .8 0 0\n" - "gpr pclath .8 1 0\n" - "gpr pclatu .8 2 0\n" - "#bsr max is 0b111\n" - "gpr bsr .8 4 0\n" - "#tos doesn't exist\n" - "#general rule of thumb any register of size >8 bits has no existence\n" - "gpr tos .32 5 0\n" - "gpr tosl .8 5 0\n" - "gpr tosh .8 6 0\n" - "gpr tosu .8 7 0\n" - - "gpr indf0 .16 9 0\n" - "gpr fsr0 .12 9 0\n" - "gpr fsr0l .8 9 0\n" - "gpr fsr0h .8 10 0\n" - "gpr indf1 .16 11 0\n" - "gpr fsr1 .12 11 0\n" - "gpr fsr1l .8 11 0\n" - "gpr fsr1h .8 12 0\n" - "gpr indf2 .16 13 0\n" - "gpr fsr2 .12 13 0\n" - "gpr frs2l .8 13 0\n" - "gpr fsr2h .8 14 0\n" - "gpr tblptr .22 15 0\n" - "gpr tblptrl .8 15 0\n" - "gpr tblptrh .8 16 0\n" - "gpr tblptru .8 17 0\n" - "gpr rcon .8 18 0\n" - "gpr memcon .8 19 0\n" - "gpr intcon .8 20 0\n" - "gpr intcon2 .8 21 0\n" - "gpr intcon3 .8 22 0\n" - "gpr pie1 .8 23 0\n" - "gpr porta .7 29 0\n" - "gpr trisa .8 30 0\n" - "gpr portb .8 33 0\n" - "gpr tisb .8 34 0\n" - "gpr latb .8 35 0\n" - "gpr portc .8 36 0\n" - "gpr trisc .8 37 0\n" - "gpr latc .8 38 0\n" - "gpr portd .8 39 0\n" - "gpr trisd .8 40 0\n" - "gpr latd .8 41 0\n" - "gpr pspcon .8 42 0\n" - "gpr porte .8 43 0\n" - "gpr trise .8 44 0\n" - "gpr late .8 45 0\n" - "gpr t0con .8 46 0\n" - "gpr t1con .8 47 0\n" - "gpr t2con .8 48 0\n" - "gpr tmr1h .8 50 0\n" - "gpr tmr0h .8 51 0\n" - "gpr tmr1l .8 52 0\n" - "gpr tmr2 .8 53 0\n" - "gpr pr2 .8 54 0\n" - "gpr ccpr1h .8 55 0\n" - "gpr postinc2 .8 56 0\n" - "gpr ccpr1l .8 57 0\n" - "gpr postdec2 .8 58 0\n" - "gpr ccp1con .8 59 0\n" - "gpr preinc2 .8 60 0\n" - "gpr ccpr2h .8 61 0\n" - "gpr plusw2 .8 62 0\n" - "gpr ccpr2l .8 63 0\n" - "gpr ccp2con .8 64 0\n" - "gpr status .8 65 0\n" - "flg c .1 .520 0\n" - "flg dc .1 .521 0\n" - "flg z .1 .522 0\n" - "flg ov .1 .523 0\n" - "flg n .1 .524 0\n" - "gpr prod .16 66 0\n" - "gpr prodl .8 66 0\n" - "gpr prodh .8 67 0\n" - "gpr osccon .8 68 0\n" - "gpr tmr3h .8 69 0\n" - "gpr lvdcon .8 70 0\n" - "gpr tmr3l .8 71 0\n" - "gpr wdtcon .8 72 0\n" - "gpr t3con .8 73 0\n" - "gpr spbrg .8 74 0\n" - "gpr postinc0 .8 75 0\n" - "gpr rcreg .8 76 0\n" - "gpr postdec0 .8 77 0\n" - "gpr txreg .8 78 0\n" - "gpr preinc0 .8 79 0\n" - "gpr txsta .8 80 0\n" - "gpr plusw0 .8 81 0\n" - "gpr rcsta .8 82 0\n" - "gpr sspbuf .8 83 0\n" - "gpr wreg .8 84 0\n" - "gpr sspadd .8 85 0\n" - "gpr sspstat .8 86 0\n" - "gpr postinc1 .8 87 0\n" - "gpr sspcon1 .8 88 0\n" - "gpr postdec1 .8 89 0\n" - "gpr sspcon2 .8 90 0\n" - "gpr preinc1 .8 91 0\n" - "gpr adresh .8 92 0\n" - "gpr plusw1 .8 93 0\n" - "gpr adresl .8 94 0\n" - "gpr adcon0 .8 95 0\n" - "#stkprt max is 0b11111\n" - "gpr stkptr .8 96 0\n" - "gpr tablat .8 14 0\n"; - - return strdup(p); -} - -static int analysis_pic_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { - if (analysis->cpu && strcasecmp(analysis->cpu, "baseline") == 0) { - // TODO: implement - return -1; + if (is_pic14_or_pic16(analysis->cpu)) { + return pic16_get_reg_profile(analysis); } - if (analysis->cpu && strcasecmp(analysis->cpu, "midrange") == 0) { - return analysis_pic_midrange_op(analysis, op, addr, buf, len); - } - if (analysis->cpu && strcasecmp(analysis->cpu, "pic18") == 0) { - return analysis_pic_pic18_op(analysis, op, addr, buf, len); - } - return -1; + return NULL; } -static char *analysis_pic_get_reg_profile(RzAnalysis *analysis) { - if (analysis->cpu && strcasecmp(analysis->cpu, "baseline") == 0) { - // TODO: We are using the midrange profile as the baseline - return analysis_pic_midrange_get_reg_profile(analysis); +static RzAnalysisILConfig *pic_il_config(RzAnalysis *analysis) { + if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) { + return pic18_il_config(analysis); } - if (analysis->cpu && strcasecmp(analysis->cpu, "midrange") == 0) { - return analysis_pic_midrange_get_reg_profile(analysis); - } - if (analysis->cpu && strcasecmp(analysis->cpu, "pic18") == 0) { - return analysis_pic_pic18_get_reg_profile(analysis); + if (is_pic14_or_pic16(analysis->cpu)) { + return pic16_il_config(analysis); } return NULL; } -static bool pic_fini(void *user) { - PicContext *ctx = (PicContext *)user; - if (ctx) { - RZ_FREE(ctx); +static int pic_archinfo(RzAnalysis *analysis, RzAnalysisInfoType query) { + if (RZ_STR_ISEMPTY(analysis->cpu) || is_pic18(analysis->cpu)) { + switch (query) { + case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2; + case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 4; + case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 2; + case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: return 4; + case RZ_ANALYSIS_ARCHINFO_CAN_USE_POINTERS: return 1; + default: return -1; + } } - return true; + + if (is_pic14_or_pic16(analysis->cpu)) { + switch (query) { + case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2; + case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: return 2; + case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 1; + case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: return 1; + case RZ_ANALYSIS_ARCHINFO_CAN_USE_POINTERS: return 1; + default: return -1; + } + } + return -1; } RzAnalysisPlugin rz_analysis_plugin_pic = { @@ -1215,6 +104,8 @@ RzAnalysisPlugin rz_analysis_plugin_pic = { .op = &analysis_pic_op, .init = pic_init, .fini = pic_fini, + .il_config = pic_il_config, .get_reg_profile = &analysis_pic_get_reg_profile, - .esil = true + .esil = true, + .archinfo = pic_archinfo }; diff --git a/librz/arch/p/asm/asm_pic.c b/librz/arch/p/asm/asm_pic.c index ffe38be12d1..682f0f1dabf 100644 --- a/librz/arch/p/asm/asm_pic.c +++ b/librz/arch/p/asm/asm_pic.c @@ -5,18 +5,18 @@ #include #include -#include "pic/pic_baseline.h" -#include "pic/pic_pic18.h" -#include "pic/pic_midrange.h" +#include "pic/pic14.h" +#include "pic/pic18.h" +#include "pic/pic16.h" static int asm_pic_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { int res = -1; - if (a->cpu && strcasecmp(a->cpu, "baseline") == 0) { - res = pic_baseline_disassemble(op, b, l); - } else if (a->cpu && strcasecmp(a->cpu, "midrange") == 0) { - res = pic_midrange_disassemble(op, b, l); - } else if (a->cpu && strcasecmp(a->cpu, "pic18") == 0) { - res = pic_pic18_disassemble(op, b, l); + if (a->cpu && is_pic14(a->cpu)) { + res = pic14_disassemble(a, op, b, l); + } else if (a->cpu && is_pic16(a->cpu)) { + res = pic16_disassemble(a, op, b, l); + } else if (a->cpu && is_pic18(a->cpu)) { + res = pic18_disassemble(a, op, b, l); } return op->size = res; } @@ -24,7 +24,7 @@ static int asm_pic_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) { RzAsmPlugin rz_asm_plugin_pic = { .name = "pic", .arch = "pic", - .cpus = "baseline,midrange,pic18", + .cpus = "pic18,pic16,pic14,highend,midrange,baseline", .bits = 8, .license = "LGPL3", .desc = "PIC disassembler", diff --git a/librz/bin/format/elf/elf_info.c b/librz/bin/format/elf/elf_info.c index 56bdff70aa5..ce84ab800cf 100644 --- a/librz/bin/format/elf/elf_info.c +++ b/librz/bin/format/elf/elf_info.c @@ -264,6 +264,7 @@ static const struct arch_translation arch_translation_table[] = { { EM_SPARCV9, "sparc" }, { EM_PPC, "ppc" }, { EM_PPC64, "ppc" }, + { EM_MCHP_PIC, "pic" }, { EM_PARISC, "hppa" }, { EM_PROPELLER, "propeller" }, { EM_MICROBLAZE, "microblaze.gnu" }, diff --git a/librz/core/cil.c b/librz/core/cil.c index f09a70a55a8..e1e03f6cdba 100644 --- a/librz/core/cil.c +++ b/librz/core/cil.c @@ -442,7 +442,9 @@ RZ_IPI void rz_core_analysis_esil_default(RzCore *core) { */ RZ_API void rz_core_analysis_il_reinit(RZ_NONNULL RzCore *core) { rz_return_if_fail(core); - rz_analysis_il_vm_setup(core->analysis); + if (!rz_analysis_il_vm_setup(core->analysis)) { + RZ_LOG_WARN("IL VM setup failed\n"); + } if (core->analysis->il_vm) { // initialize the program counter with the current offset rz_reg_set_value_by_role(core->analysis->reg, RZ_REG_NAME_PC, core->offset); diff --git a/test/db/analysis/pic b/test/db/analysis/pic index f932eab38d0..2f9108c0df1 100644 --- a/test/db/analysis/pic +++ b/test/db/analysis/pic @@ -27,6 +27,10 @@ pc = 0x0000 stkptr = 0x00 _sram = 0x00000000 _stack = 0x00000000 +tosl = 0x00 +tosh = 0x00 +tris = 0x00 +_bank = 0x00 =============== pic18 pc = 0x00000000 bsr = 0x00 @@ -106,5 +110,11 @@ plusw1 = 0x00 adresl = 0x00 adcon0 = 0x00 stkptr = 0x00 +_sram = 0x00 +_stack = 0x00 +_skip = 0x00 +wregs = 0x00 +statuss = 0x00 +bsrs = 0x00 EOF RUN diff --git a/test/db/asm/pic_pic16_8 b/test/db/asm/pic_pic16_8 new file mode 100644 index 00000000000..a24d123ed5a --- /dev/null +++ b/test/db/asm/pic_pic16_8 @@ -0,0 +1,415 @@ +d "addfsr FSR0, 0" 0031 0x000000 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x0))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0" 0031 0x00ff00 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x0))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x1" 0131 0x000000 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x1" 0131 0x00ff00 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x2" 0231 0x000000 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x2))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x2" 0231 0x00ff00 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x2))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x3" 0331 0x000000 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x3))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x3" 0331 0x00ff00 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x3))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addfsr FSR0, 0x4" 0431 0x000000 (seq (set __x (+ (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x4))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x)))) +d "addlw 0x0" 003e 0x000000 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (bv 8 0x0))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (bv 8 0x0)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addlw 0x0" 003e 0x00ff00 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (bv 8 0x0))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (bv 8 0x0)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addlw 0x1" 013e 0x000000 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (bv 8 0x1))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (bv 8 0x1)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addlw 0x1" 013e 0x00ff00 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (bv 8 0x1))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (bv 8 0x1)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! 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(is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addlw 0x4" 043e 0x000000 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (bv 8 0x4))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (bv 8 0x4)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! 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(msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addwf indf0, 0" 0007 0x00ff00 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _f (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set _res (+ (var _w) (var _f))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (var _f)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addwf indf1, 0" 0107 0x000000 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _f (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set _res (+ (var _w) (var _f))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (var _f)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addwf indf1, 0" 0107 0x00ff00 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _f (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set _res (+ (var _w) (var _f))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (var _f)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addwf pcl, 0" 0207 0x000000 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _f (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (var _f))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (var _f)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! 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(is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "addwf status, 0" 0307 0x000000 (seq (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _f (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (+ (var _w) (var _f))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _w)) (set status_y (var _f)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (var status_y))) (&& (|| (msb (var status_x)) (msb (var status_y))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var status_y) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb)))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res))) +d "andlw 0x0" 0039 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x0))) (store 0 (+ (bv 16 0x3) (cast 16 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0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "andwf status, 0" 0305 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* 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(var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "bcf indf0, 0" 0010 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (& (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0xfe))) +d "bcf indf0, 0" 0010 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (& (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0xfe))) +d "bcf indf1, 0" 0110 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (& (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0xfe))) +d "bcf indf1, 0" 0110 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (& (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0xfe))) +d "bcf pcl, 0" 0210 0x000000 (store 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfe))) +d "bcf pcl, 0" 0210 0x00ff00 (store 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfe))) +d "bcf status, 0" 0310 0x000000 (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfe))) +d "bcf status, 0" 0310 0x00ff00 (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfe))) +d "bcf fsr0l, 0" 0410 0x000000 (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (& (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfe))) +d "bra 0" 0032 0x000000 (jmp (bv 16 0x0)) +d "bra 0" 0032 0x00ff00 (jmp (bv 16 0xff00)) +d "bra 0x1" 0132 0x000000 (jmp (bv 16 0x1)) +d "bra 0x1" 0132 0x00ff00 (jmp (bv 16 0xff01)) +d "bra 0x2" 0232 0x000000 (jmp (bv 16 0x2)) +d "bra 0x2" 0232 0x00ff00 (jmp (bv 16 0xff02)) +d "bra 0x3" 0332 0x000000 (jmp (bv 16 0x3)) +d "bra 0x3" 0332 0x00ff00 (jmp (bv 16 0xff03)) +d "bra 0x4" 0432 0x000000 (jmp (bv 16 0x4)) +d "brw" 0b00 0x000000 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0x2) (bv 16 0x1) false))) +d "brw" 0b00 0x00ff00 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0xff02) (bv 16 0x1) false))) +d "brw" 0b40 0x000000 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0x2) (bv 16 0x1) false))) +d "brw" 0b40 0x00ff00 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0xff02) (bv 16 0x1) false))) +d "brw" 0b80 0x000000 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0x2) (bv 16 0x1) false))) +d "brw" 0b80 0x00ff00 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0xff02) (bv 16 0x1) false))) +d "brw" 0bc0 0x000000 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0x2) (bv 16 0x1) false))) +d "brw" 0bc0 0x00ff00 (jmp (+ (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (>> (bv 16 0xff02) (bv 16 0x1) false))) +d "bsf indf0, 0" 0014 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) +d "bsf indf0, 0" 0014 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) +d "bsf indf1, 0" 0114 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) +d "bsf indf1, 0" 0114 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) +d "bsf pcl, 0" 0214 0x000000 (store 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) +d "bsf pcl, 0" 0214 0x00ff00 (store 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) +d "bsf status, 0" 0314 0x000000 (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) +d "bsf status, 0" 0314 0x00ff00 (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) +d "bsf fsr0l, 0" 0414 0x000000 (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) +d "btfsc indf0, 0" 0018 0x000000 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) nop (jmp (bv 16 0x4))) +d "btfsc indf0, 0" 0018 0x00ff00 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) nop (jmp (bv 16 0xff04))) +d "btfsc indf1, 0" 0118 0x000000 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) nop (jmp (bv 16 0x4))) +d "btfsc indf1, 0" 0118 0x00ff00 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) nop (jmp (bv 16 0xff04))) +d "btfsc pcl, 0" 0218 0x000000 (branch (! (is_zero (& (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) nop (jmp (bv 16 0x4))) +d "btfsc pcl, 0" 0218 0x00ff00 (branch (! (is_zero (& (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) nop (jmp (bv 16 0xff04))) +d "btfsc status, 0" 0318 0x000000 (branch (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) nop (jmp (bv 16 0x4))) +d "btfsc status, 0" 0318 0x00ff00 (branch (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) nop (jmp (bv 16 0xff04))) +d "btfsc fsr0l, 0" 0418 0x000000 (branch (! (is_zero (& (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) nop (jmp (bv 16 0x4))) +d "btfss indf0, 0" 001c 0x000000 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) (jmp (bv 16 0x4)) nop) +d "btfss indf0, 0" 001c 0x00ff00 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) (jmp (bv 16 0xff04)) nop) +d "btfss indf1, 0" 011c 0x000000 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) (jmp (bv 16 0x4)) nop) +d "btfss indf1, 0" 011c 0x00ff00 (branch (! (is_zero (& (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1)))) (jmp (bv 16 0xff04)) nop) +d "btfss pcl, 0" 021c 0x000000 (branch (! (is_zero (& (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (jmp (bv 16 0x4)) nop) +d "btfss pcl, 0" 021c 0x00ff00 (branch (! (is_zero (& (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (jmp (bv 16 0xff04)) nop) +d "btfss status, 0" 031c 0x000000 (branch (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (jmp (bv 16 0x4)) nop) +d "btfss status, 0" 031c 0x00ff00 (branch (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (jmp (bv 16 0xff04)) nop) +d "btfss fsr0l, 0" 041c 0x000000 (branch (! (is_zero (& (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (jmp (bv 16 0x4)) nop) +d "call 0x0" 0020 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x0" 0020 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x1" 0120 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x1) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x1" 0120 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x1) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x2" 0220 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x2) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x2" 0220 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x2) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x3" 0320 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x3) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x3" 0320 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x3) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "call 0x4" 0420 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x4) (<< (cast 16 false (cast 1 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false)))) +d "callw" 0a00 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0a00 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0a40 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0a40 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0a80 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0a80 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0ac0 0x000000 (seq (set __tos (bv 16 0x2)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "callw" 0ac0 0x00ff00 (seq (set __tos (bv 16 0xff02)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (jmp (| (bv 16 0x0) (cast 16 false (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) +d "clrf indf0" 8001 0x000000 (seq (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 8 0x0)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* 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0x80)))))))) (jmp (bv 16 0xff04)) nop)) +d "decfsz pcl, 0" 020b 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (- (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0x4)) nop)) +d "decfsz pcl, 0" 020b 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (- (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0xff04)) nop)) +d "decfsz status, 0" 030b 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (- (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0x4)) nop)) +d "decfsz status, 0" 030b 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (- (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0xff04)) nop)) +d "decfsz fsr0l, 0" 040b 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (- (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0x4)) nop)) +d "goto 0x0" 0028 0x000000 (jmp (| (bv 16 0x0) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x0" 0028 0x00ff00 (jmp (| (bv 16 0x0) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x1" 0128 0x000000 (jmp (| (bv 16 0x1) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x1" 0128 0x00ff00 (jmp (| (bv 16 0x1) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x2" 0228 0x000000 (jmp (| (bv 16 0x2) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x2" 0228 0x00ff00 (jmp (| (bv 16 0x2) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x3" 0328 0x000000 (jmp (| (bv 16 0x3) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x3" 0328 0x00ff00 (jmp (| (bv 16 0x3) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "goto 0x4" 0428 0x000000 (jmp (| (bv 16 0x4) (<< (cast 16 false (cast 2 false (>> (load 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 16 0x3) false))) (bv 16 0xb) false))) +d "incf indf0, 0" 000a 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "incf indf0, 0" 000a 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "incf indf1, 0" 010a 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "incf indf1, 0" 010a 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 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16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "incf status, 0" 030a 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "incf status, 0" 030a 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 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(load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (jmp (bv 16 0x4)) nop)) +d "incfsz indf0, 0" 000f 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (branch (is_zero (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (jmp (bv 16 0xff04)) nop)) +d "incfsz indf1, 0" 010f 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (branch (is_zero (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (jmp (bv 16 0x4)) nop)) +d "incfsz indf1, 0" 010f 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (bv 8 0x1))) (branch (is_zero (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (jmp (bv 16 0xff04)) nop)) +d "incfsz pcl, 0" 020f 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0x4)) nop)) +d "incfsz pcl, 0" 020f 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0xff04)) nop)) +d "incfsz status, 0" 030f 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0x4)) nop)) +d "incfsz status, 0" 030f 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0xff04)) nop)) +d "incfsz fsr0l, 0" 040f 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (+ (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (branch (is_zero (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (jmp (bv 16 0x4)) nop)) +d "iorlw 0x0" 0038 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x0))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "iorlw 0x0" 0038 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x0))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "iorlw 0x1" 0138 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "iorlw 0x1" 0138 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (| (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 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(append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw FSR0--" 1300 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set __x (- (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "moviw ++FSR1" 1400 0x000000 (seq (set __x (+ (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (bv 16 0x1))) (store 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))) (cast 8 false (var __x))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "movlb 0x0" 2000 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x0" 2000 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x1" 2100 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x1)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x1" 2100 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x1)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x2" 2200 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x2)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x2" 2200 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x2)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x3" 2300 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x3)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x3" 2300 0x00ff00 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x3)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlb 0x4" 2400 0x000000 (seq (store 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x4)) (set _bank (& (load 0 (+ (bv 16 0x8) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1f)))) +d "movlp indf0" 8031 0x000000 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp indf0" 8031 0x00ff00 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp indf1" 8131 0x000000 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp indf1" 8131 0x00ff00 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp pcl" 8231 0x000000 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp pcl" 8231 0x00ff00 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp status" 8331 0x000000 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp status" 8331 0x00ff00 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlp fsr0l" 8431 0x000000 (store 0 (+ (bv 16 0xa) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlw 0x0" 0030 0x000000 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlw 0x0" 0030 0x00ff00 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x0)) +d "movlw 0x1" 0130 0x000000 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x1)) +d "movlw 0x1" 0130 0x00ff00 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x1)) +d "movlw 0x2" 0230 0x000000 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x2)) +d "movlw 0x2" 0230 0x00ff00 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x2)) +d "movlw 0x3" 0330 0x000000 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x3)) +d "movlw 0x3" 0330 0x00ff00 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x3)) +d "movlw 0x4" 0430 0x000000 (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (bv 8 0x4)) +d "movwf indf0" 8000 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf indf0" 8000 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf indf1" 8100 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf indf1" 8100 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf pcl" 8200 0x000000 (store 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf pcl" 8200 0x00ff00 (store 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf status" 8300 0x000000 (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf status" 8300 0x00ff00 (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwf fsr0l" 8400 0x000000 (store 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi ++FSR0" 1800 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi ++FSR0" 1800 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi --FSR0" 1900 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi --FSR0" 1900 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR0++" 1a00 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR0++" 1a00 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR0--" 1b00 0x000000 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi FSR0--" 1b00 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "movwi ++FSR1" 1c00 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "nop" 0000 0x000000 nop +d "nop" 0000 0x00ff00 nop +d "nop" 0040 0x000000 nop +d "nop" 0040 0x00ff00 nop +d "nop" 0080 0x000000 nop +d "nop" 0080 0x00ff00 nop +d "nop" 00c0 0x000000 nop +d "nop" 00c0 0x00ff00 nop +d "option" 6200 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 6200 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 6240 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 6240 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 6280 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 6280 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 62c0 0x000000 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "option" 62c0 0x00ff00 (store 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) +d "reset" 0100 0x000000 (seq nop (jmp (bv 16 0x0))) +d "reset" 0100 0x00ff00 (seq nop (jmp (bv 16 0x0))) +d "reset" 0140 0x000000 (seq nop (jmp (bv 16 0x0))) +d "reset" 0140 0x00ff00 (seq nop (jmp (bv 16 0x0))) +d "reset" 0180 0x000000 (seq nop (jmp (bv 16 0x0))) +d "reset" 0180 0x00ff00 (seq nop (jmp (bv 16 0x0))) +d "reset" 01c0 0x000000 (seq nop (jmp (bv 16 0x0))) +d "reset" 01c0 0x00ff00 (seq nop (jmp (bv 16 0x0))) +d "retfie" 0900 0x000000 (seq (set __tos (bv 16 0x0)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 0900 0x00ff00 (seq (set __tos (bv 16 0xff00)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 0940 0x000000 (seq (set __tos (bv 16 0x0)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 0940 0x00ff00 (seq (set __tos (bv 16 0xff00)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 0980 0x000000 (seq (set __tos (bv 16 0x0)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 0980 0x00ff00 (seq (set __tos (bv 16 0xff00)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 09c0 0x000000 (seq (set __tos (bv 16 0x0)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retfie" 09c0 0x00ff00 (seq (set __tos (bv 16 0xff00)) (store 0 (bv 16 0xfef) (cast 8 false (>> (var __tos) (bv 8 0x8) false))) (store 0 (bv 16 0xfee) (cast 8 false (var __tos))) (store 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite true (| (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x80)) (& (load 0 (+ (bv 16 0xb) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x7f))))) +d "retlw 0x0" 0034 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 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(is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "subwf status, 0" 0302 0x000000 (seq (set _f (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (- (var _f) (var _w))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _f)) (set status_y (var _w)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "subwf status, 0" 0302 0x00ff00 (seq (set _f (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (- (var _f) (var _w))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _f)) (set status_y (var _w)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb))))) +d "subwf fsr0l, 0" 0402 0x000000 (seq (set _f (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _w (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set _res (- (var _f) (var _w))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (set status_x (var _f)) (set status_y (var _w)) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! 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(is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80)))))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb)))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res))) +d "subwfb pcl, 0" 023b 0x000000 (seq (set _res (+ (- (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (ite (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb)))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res))) +d "subwfb pcl, 0" 023b 0x00ff00 (seq (set _res (+ (- (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (ite (! 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(is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb)))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res))) +d "subwfb status, 0" 033b 0x000000 (seq (set _res (+ (- (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (ite (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb)))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res))) +d "subwfb status, 0" 033b 0x00ff00 (seq (set _res (+ (- (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (ite (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var status_res) (bv 32 0x3) false))))))) (set _z (is_zero (var status_res))) (set _status (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (var _z) (| (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0x4)) (& (ite (var _dc) (| (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0x2)) (& (ite (var _c) (| (var _status) (bv 8 0x1)) (& (var _status) (bv 8 0xfe))) (bv 8 0xfd))) (bv 8 0xfb)))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res))) +d "subwfb fsr0l, 0" 043b 0x000000 (seq (set _res (+ (- (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (ite (! (is_zero (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (set status_x (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_y (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (set status_res (var _res)) (set _c (|| (&& (msb (var status_x)) (msb (~- (var status_y)))) (&& (|| (msb (var status_x)) (msb (~- (var status_y)))) (! (msb (var status_res)))))) (set _dc (|| (&& (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (var status_x) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (~- (var status_y)) (bv 32 0x3) false)))) (! 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_bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorlw 0x3" 033a 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x3))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorlw 0x3" 033a 0x00ff00 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x3))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorlw 0x4" 043a 0x000000 (seq (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4))) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))))) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf indf0, 0" 0006 0x000000 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf indf0, 0" 0006 0x00ff00 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (append (load 0 (+ (bv 16 0x5) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf indf1, 0" 0106 0x000000 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf indf1, 0" 0106 0x00ff00 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (append (load 0 (+ (bv 16 0x7) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x6) (cast 16 false (* (var _bank) (bv 8 0x80))))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf pcl, 0" 0206 0x000000 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf pcl, 0" 0206 0x00ff00 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x2) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf status, 0" 0306 0x000000 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf status, 0" 0306 0x00ff00 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) +d "xorwf fsr0l, 0" 0406 0x000000 (seq (set _res (^ (load 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80))))) (load 0 (+ (bv 16 0x4) (cast 16 false (* (var _bank) (bv 8 0x80))))))) (store 0 (+ (bv 16 0x9) (cast 16 false (* (var _bank) (bv 8 0x80)))) (var _res)) (store 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80)))) (ite (is_zero (var _res)) (| (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0x4)) (& (load 0 (+ (bv 16 0x3) (cast 16 false (* (var _bank) (bv 8 0x80))))) (bv 8 0xfb))))) diff --git a/test/db/asm/pic_pic18_8 b/test/db/asm/pic_pic18_8 index 3ea12004117..369b039286c 100644 --- a/test/db/asm/pic_pic18_8 +++ b/test/db/asm/pic_pic18_8 @@ -1,21 +1,545 @@ -d "addlw 0x12" 120f -d "addwf 0xd1, 0, 1" d125 -d "addwfc 0x35, 1, 0" 3522 -d "andwf 0x85, 1, 1" 8517 -d "bcf 0x42, 7, 1" 429f -d "bnn 0xfa" fae7 -d "bra 0x51e" 1ed5 -d "call 0x612a1, 1" a1ed12f6 -d "clrf 0x15, 0" 156a -d "comf 0x48, 0, 0" 481c -d "cpfseq 0x71, 1" 7163 -d "cpfsgt 0x62, 0" 6264 -d "cpfslt 0xc4, 0" c460 -d "goto 0x274e" a7ef13f0 +d "addlw 0x12" 120f 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x12))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x12))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x12))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x12) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x12) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x12)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf wdtcon, 0, 1" d125 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0xfd1)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0xfd1)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0xfd1)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfd1)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfd1)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfd1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (+ (* (cast 24 false (& (load 0 (bv 24 0xfe0)) (bv 8 0xf))) (bv 24 0x100)) (bv 24 0xfe8)) (var __res)))) +d "addwfc 0x35, 1, 0" 3522 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x35)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x35)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x35)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x35)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x35)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x35))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0x35) (var __res)))) +d "andwf 0x85, 1, 1" 8517 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0xf85)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (+ (* (cast 24 false (& (load 0 (bv 24 0xfe0)) (bv 8 0xf))) (bv 24 0x100)) (bv 24 0xf85)) (var __res)))) +d "bcf 0x42, 7, 1" 429f 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x42) (& (load 0 (bv 24 0x42)) (bv 8 0x7f)))) +d "bnn 0xfa" fae7 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10))))) (jmp (bv 24 0xfffff6)) nop)) +d "bra 0x51e" 1ed5 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0x3e))) +d "call 0xc2542, 1" a1ed12f6 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __x (bv 24 0x4)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (set wregs (load 0 (bv 24 0xfe8))) (set statuss (load 0 (bv 24 0xfd8))) (set bsrs (load 0 (bv 24 0xfe0))) (jmp (bv 24 0xc2542)))) +d "clrf 0x15, 0" 156a 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x15) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "comf 0x48, 0, 0" 481c 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x48)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "cpfseq 0x71, 1" 7163 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x71))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x62, 0" 6264 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x62)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt adresh, 0" c460 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0xfc4)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0xfc4)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "goto 0x274e" a7ef13f0 0x0 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0x274e))) d "invalid" 02 dB "invalid" 0200 -d "lfsr fsr2, 4005" 2feea5f0 -d "movff 0xe54, 0x49" 54ce49f0 -d "movlb 0xd" 0d01 -d "nop" 15f0 -d "return 0" 1200 \ No newline at end of file +d "addlw 0x0" 000f 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x0))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x0))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x0))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x0)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x0" 000f 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x0))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x0))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x0))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x0)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x1" 010f 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x1" 010f 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x2" 020f 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x2))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x2))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x2))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x2)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x2" 020f 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x2))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x2))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x2))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x2)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x3" 030f 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x3))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x3))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x3))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x3)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x3" 030f 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x3))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x3))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x3))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x3)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addlw 0x4" 040f 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (bv 8 0x4))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x4))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (bv 8 0x4))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x4) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x4) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (bv 8 0x4)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x00, 0, 0" 0024 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x00, 0, 0" 0024 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x01, 0, 0" 0124 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x01, 0, 0" 0124 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x02, 0, 0" 0224 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x02, 0, 0" 0224 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x03, 0, 0" 0324 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x03, 0, 0" 0324 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwf 0x04, 0, 0" 0424 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x4)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x4)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x4)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x00, 0, 0" 0020 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x0)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x00, 0, 0" 0020 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x0)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x0)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x01, 0, 0" 0120 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x1)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x01, 0, 0" 0120 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x1)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x1)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x02, 0, 0" 0220 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x2)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x02, 0, 0" 0220 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x2)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x2)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x03, 0, 0" 0320 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x3)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x03, 0, 0" 0320 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x3)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x3)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "addwfc 0x04, 0, 0" 0420 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x4)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x4)))) (&& (|| (msb (load 0 (bv 24 0xfe8))) (msb (load 0 (bv 24 0x4)))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x0" 000b 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x0))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x0" 000b 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x0))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x1" 010b 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x1" 010b 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x2" 020b 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x2))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x2" 020b 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x2))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x3" 030b 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x3))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x3" 030b 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x3))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andlw 0x4" 040b 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (bv 8 0x4))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x00, 0, 0" 0014 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x00, 0, 0" 0014 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x01, 0, 0" 0114 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x01, 0, 0" 0114 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x02, 0, 0" 0214 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x02, 0, 0" 0214 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x03, 0, 0" 0314 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x03, 0, 0" 0314 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "andwf 0x04, 0, 0" 0414 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (& (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x4)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "bc 0x0" 00e2 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0x2)) nop)) +d "bc 0x0" 00e2 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0xff02)) nop)) +d "bc 0x1" 01e2 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0x4)) nop)) +d "bc 0x1" 01e2 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0xff04)) nop)) +d "bc 0x2" 02e2 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0x6)) nop)) +d "bc 0x2" 02e2 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0xff06)) nop)) +d "bc 0x3" 03e2 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0x8)) nop)) +d "bc 0x3" 03e2 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0xff08)) nop)) +d "bc 0x4" 04e2 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (jmp (bv 24 0xa)) nop)) +d "bcf 0x00, 0, 0" 0090 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (& (load 0 (bv 24 0x0)) (bv 8 0xfe)))) +d "bcf 0x00, 0, 0" 0090 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (& (load 0 (bv 24 0x0)) (bv 8 0xfe)))) +d "bcf 0x01, 0, 0" 0190 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (& (load 0 (bv 24 0x1)) (bv 8 0xfe)))) +d "bcf 0x01, 0, 0" 0190 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (& (load 0 (bv 24 0x1)) (bv 8 0xfe)))) +d "bcf 0x02, 0, 0" 0290 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (& (load 0 (bv 24 0x2)) (bv 8 0xfe)))) +d "bcf 0x02, 0, 0" 0290 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (& (load 0 (bv 24 0x2)) (bv 8 0xfe)))) +d "bcf 0x03, 0, 0" 0390 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (& (load 0 (bv 24 0x3)) (bv 8 0xfe)))) +d "bcf 0x03, 0, 0" 0390 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (& (load 0 (bv 24 0x3)) (bv 8 0xfe)))) +d "bcf 0x04, 0, 0" 0490 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x4) (& (load 0 (bv 24 0x4)) (bv 8 0xfe)))) +d "bn 0x0" 00e6 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0x2)) nop)) +d "bn 0x0" 00e6 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0xff02)) nop)) +d "bn 0x1" 01e6 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0x4)) nop)) +d "bn 0x1" 01e6 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0xff04)) nop)) +d "bn 0x2" 02e6 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0x6)) nop)) +d "bn 0x2" 02e6 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0xff06)) nop)) +d "bn 0x3" 03e6 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0x8)) nop)) +d "bn 0x3" 03e6 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0xff08)) nop)) +d "bn 0x4" 04e6 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x10)))) (jmp (bv 24 0xa)) nop)) +d "bnc 0x0" 00e3 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1))))) (jmp (bv 24 0x2)) nop)) +d "bnc 0x0" 00e3 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1))))) (jmp (bv 24 0xff02)) nop)) +d "bnc 0x1" 01e3 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! 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(is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4))))) (jmp (bv 24 0xff04)) nop)) +d "bnz 0x2" 02e1 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4))))) (jmp (bv 24 0x6)) nop)) +d "bnz 0x2" 02e1 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4))))) (jmp (bv 24 0xff06)) nop)) +d "bnz 0x3" 03e1 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4))))) (jmp (bv 24 0x8)) nop)) +d "bnz 0x3" 03e1 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4))))) (jmp (bv 24 0xff08)) nop)) +d "bnz 0x4" 04e1 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (! 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(is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x8)))) (jmp (bv 24 0xff06)) nop)) +d "bov 0x3" 03e4 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x8)))) (jmp (bv 24 0x8)) nop)) +d "bov 0x3" 03e4 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x8)))) (jmp (bv 24 0xff08)) nop)) +d "bov 0x4" 04e4 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x8)))) (jmp (bv 24 0xa)) nop)) +d "bra 0x0" 00d0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0x2))) +d "bra 0x0" 00d0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0xff02))) +d "bra 0x1" 01d0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0x4))) +d "bra 0x1" 01d0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0xff04))) +d "bra 0x2" 02d0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0x6))) +d "bra 0x2" 02d0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0xff06))) +d "bra 0x3" 03d0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0x8))) +d "bra 0x3" 03d0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0xff08))) +d "bra 0x4" 04d0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (jmp (bv 24 0xa))) +d "bsf 0x00, 0, 0" 0080 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (| (load 0 (bv 24 0x0)) (bv 8 0x1)))) +d "bsf 0x00, 0, 0" 0080 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (| (load 0 (bv 24 0x0)) (bv 8 0x1)))) +d "bsf 0x01, 0, 0" 0180 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (| (load 0 (bv 24 0x1)) (bv 8 0x1)))) +d "bsf 0x01, 0, 0" 0180 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (| (load 0 (bv 24 0x1)) (bv 8 0x1)))) +d "bsf 0x02, 0, 0" 0280 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (| (load 0 (bv 24 0x2)) (bv 8 0x1)))) +d "bsf 0x02, 0, 0" 0280 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (| (load 0 (bv 24 0x2)) (bv 8 0x1)))) +d "bsf 0x03, 0, 0" 0380 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (| (load 0 (bv 24 0x3)) (bv 8 0x1)))) +d "bsf 0x03, 0, 0" 0380 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (| (load 0 (bv 24 0x3)) (bv 8 0x1)))) +d "bsf 0x04, 0, 0" 0480 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x4) (| (load 0 (bv 24 0x4)) (bv 8 0x1)))) +d "btfsc 0x00, 0, 0" 00b0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x00, 0, 0" 00b0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x01, 0, 0" 01b0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x01, 0, 0" 01b0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x02, 0, 0" 02b0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x02, 0, 0" 02b0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x03, 0, 0" 03b0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x03, 0, 0" 03b0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfsc 0x04, 0, 0" 04b0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x0) false))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x00, 0, 0" 00a0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x0)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x00, 0, 0" 00a0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x0)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x01, 0, 0" 01a0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x1)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x01, 0, 0" 01a0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x1)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x02, 0, 0" 02a0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x2)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x02, 0, 0" 02a0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x2)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x03, 0, 0" 03a0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x3)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x03, 0, 0" 03a0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x3)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btfss 0x04, 0, 0" 04a0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0x4)) (bv 8 0x1)))) (set _skip (bv 8 0x1)) nop)) +d "btg 0x00, 0, 0" 0070 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (ite (! (! (is_zero (& (load 0 (bv 24 0x0)) (bv 8 0x1))))) (| (load 0 (bv 24 0x0)) (bv 8 0x1)) (& (load 0 (bv 24 0x0)) (bv 8 0xfe))))) +d "btg 0x00, 0, 0" 0070 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (ite (! (! (is_zero (& (load 0 (bv 24 0x0)) (bv 8 0x1))))) (| (load 0 (bv 24 0x0)) (bv 8 0x1)) (& (load 0 (bv 24 0x0)) (bv 8 0xfe))))) +d "btg 0x01, 0, 0" 0170 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (ite (! (! (is_zero (& (load 0 (bv 24 0x1)) (bv 8 0x1))))) (| (load 0 (bv 24 0x1)) (bv 8 0x1)) (& (load 0 (bv 24 0x1)) (bv 8 0xfe))))) +d "btg 0x01, 0, 0" 0170 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (ite (! (! (is_zero (& (load 0 (bv 24 0x1)) (bv 8 0x1))))) (| (load 0 (bv 24 0x1)) (bv 8 0x1)) (& (load 0 (bv 24 0x1)) (bv 8 0xfe))))) +d "btg 0x02, 0, 0" 0270 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (ite (! (! (is_zero (& (load 0 (bv 24 0x2)) (bv 8 0x1))))) (| (load 0 (bv 24 0x2)) (bv 8 0x1)) (& (load 0 (bv 24 0x2)) (bv 8 0xfe))))) +d "btg 0x02, 0, 0" 0270 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (ite (! (! (is_zero (& (load 0 (bv 24 0x2)) (bv 8 0x1))))) (| (load 0 (bv 24 0x2)) (bv 8 0x1)) (& (load 0 (bv 24 0x2)) (bv 8 0xfe))))) +d "btg 0x03, 0, 0" 0370 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (ite (! (! (is_zero (& (load 0 (bv 24 0x3)) (bv 8 0x1))))) (| (load 0 (bv 24 0x3)) (bv 8 0x1)) (& (load 0 (bv 24 0x3)) (bv 8 0xfe))))) +d "btg 0x03, 0, 0" 0370 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (ite (! (! (is_zero (& (load 0 (bv 24 0x3)) (bv 8 0x1))))) (| (load 0 (bv 24 0x3)) (bv 8 0x1)) (& (load 0 (bv 24 0x3)) (bv 8 0xfe))))) +d "btg 0x04, 0, 0" 0470 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x4) (ite (! (! (is_zero (& (load 0 (bv 24 0x4)) (bv 8 0x1))))) (| (load 0 (bv 24 0x4)) (bv 8 0x1)) (& (load 0 (bv 24 0x4)) (bv 8 0xfe))))) +d "bz 0x0" 00e0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0x2)) nop)) +d "bz 0x0" 00e0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0xff02)) nop)) +d "bz 0x1" 01e0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0x4)) nop)) +d "bz 0x1" 01e0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0xff04)) nop)) +d "bz 0x2" 02e0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0x6)) nop)) +d "bz 0x2" 02e0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0xff06)) nop)) +d "bz 0x3" 03e0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0x8)) nop)) +d "bz 0x3" 03e0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0xff08)) nop)) +d "bz 0x4" 04e0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x4)))) (jmp (bv 24 0xa)) nop)) +d "clrf 0x00, 0" 006a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x0) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x00, 0" 006a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x0) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x01, 0" 016a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x1) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x01, 0" 016a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x1) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x02, 0" 026a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x2) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x02, 0" 026a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x2) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x03, 0" 036a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x3) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x03, 0" 036a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x3) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "clrf 0x04, 0" 046a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0x4) (bv 8 0x0)) (store 0 (bv 24 0xfd8) (ite true (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))))) +d "comf 0x00, 0, 0" 001c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x00, 0, 0" 001c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x01, 0, 0" 011c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x01, 0, 0" 011c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x02, 0, 0" 021c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x02, 0, 0" 021c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x03, 0, 0" 031c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x03, 0, 0" 031c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "comf 0x04, 0, 0" 041c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (~- (load 0 (bv 24 0x4)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "cpfseq 0x00, 0" 0062 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x00, 0" 0062 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x01, 0" 0162 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x01, 0" 0162 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x02, 0" 0262 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x02, 0" 0262 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x03, 0" 0362 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x03, 0" 0362 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3))) (set _skip (bv 8 0x1)) nop)) +d "cpfseq 0x04, 0" 0462 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (== (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x4))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x00, 0" 0064 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x00, 0" 0064 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x01, 0" 0164 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x01, 0" 0164 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x02, 0" 0264 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x02, 0" 0264 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x03, 0" 0364 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x03, 0" 0364 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfsgt 0x04, 0" 0464 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (! (ule (load 0 (bv 24 0x4)) (load 0 (bv 24 0xfe8)))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x00, 0" 0060 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x00, 0" 0060 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x01, 0" 0160 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x01, 0" 0160 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x02, 0" 0260 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x02, 0" 0260 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x03, 0" 0360 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x03, 0" 0360 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "cpfslt 0x04, 0" 0460 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (&& (ule (load 0 (bv 24 0x4)) (load 0 (bv 24 0xfe8))) (! (== (load 0 (bv 24 0x4)) (load 0 (bv 24 0xfe8))))) (set _skip (bv 8 0x1)) nop)) +d "daw" 0700 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x03 (cast 4 false (load 0 (bv 24 0xfe8))) (let _x47 (cast 4 false (>> (load 0 (bv 24 0xfe8)) (bv 8 0x4) false)) (append (ite (|| (! (ule (var _x47) (bv 4 0x9))) (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1))))) (+ (var _x47) (bv 4 0x6)) (var _x47)) (ite (|| (! (ule (var _x03) (bv 4 0x9))) (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x2))))) (+ (var _x03) (bv 4 0x6)) (var _x03)))))) (store 0 (bv 24 0xfd8) (ite false (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "daw" 0700 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x03 (cast 4 false (load 0 (bv 24 0xfe8))) (let _x47 (cast 4 false (>> (load 0 (bv 24 0xfe8)) (bv 8 0x4) false)) (append (ite (|| (! (ule (var _x47) (bv 4 0x9))) (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1))))) (+ (var _x47) (bv 4 0x6)) (var _x47)) (ite (|| (! (ule (var _x03) (bv 4 0x9))) (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x2))))) (+ (var _x03) (bv 4 0x6)) (var _x03)))))) (store 0 (bv 24 0xfd8) (ite false (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "dcfsnz 0x00, 0, 0" 004c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x00, 0, 0" 004c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x01, 0, 0" 014c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x01, 0, 0" 014c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x02, 0, 0" 024c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x02, 0, 0" 024c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x03, 0, 0" 034c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x03, 0, 0" 034c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "dcfsnz 0x04, 0, 0" 044c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x4)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "decf 0x00, 0, 0" 0004 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x0)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x0)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x0))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x00, 0, 0" 0004 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x0)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x0)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x0))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x01, 0, 0" 0104 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x1)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x1)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x1))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x01, 0, 0" 0104 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x1)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x1)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x1))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x02, 0, 0" 0204 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x2)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x2)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x2))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x02, 0, 0" 0204 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x2)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x2)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x2))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x03, 0, 0" 0304 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x3)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x3)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x3))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x03, 0, 0" 0304 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x3)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x3)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x3))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decf 0x04, 0, 0" 0404 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x4)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x4)))) (msb (bv 8 0x1))) (&& (! (msb (load 0 (bv 24 0x4)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x4))) (&& (msb (bv 8 0x1)) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "decfsz 0x00, 0, 0" 002c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x00, 0, 0" 002c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x01, 0, 0" 012c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x01, 0, 0" 012c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x02, 0, 0" 022c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x02, 0, 0" 022c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x03, 0, 0" 032c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x03, 0, 0" 032c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "decfsz 0x04, 0, 0" 042c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x4)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incf 0x00, 0, 0" 0028 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x0))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x0))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x00, 0, 0" 0028 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x0))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x0))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x01, 0, 0" 0128 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x1))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x1))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x01, 0, 0" 0128 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x1))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x1))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x02, 0, 0" 0228 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x2))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x2))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x02, 0, 0" 0228 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x2))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x2))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x03, 0, 0" 0328 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x3))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x3))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x03, 0, 0" 0328 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x3))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x3))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incf 0x04, 0, 0" 0428 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x4)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (|| (&& (msb (load 0 (bv 24 0x4))) (msb (bv 8 0x1))) (&& (|| (msb (load 0 (bv 24 0x4))) (msb (bv 8 0x1))) (! (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (&& (|| (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (! (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res))) (^^ (msb (bv 8 0x1)) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "incfsz 0x00, 0, 0" 003c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x00, 0, 0" 003c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x01, 0, 0" 013c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x01, 0, 0" 013c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x02, 0, 0" 023c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x02, 0, 0" 023c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x03, 0, 0" 033c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x03, 0, 0" 033c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "incfsz 0x04, 0, 0" 043c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x4)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (is_zero (var __res)) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x00, 0, 0" 0048 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x00, 0, 0" 0048 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x0)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x01, 0, 0" 0148 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x01, 0, 0" 0148 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x1)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x02, 0, 0" 0248 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x02, 0, 0" 0248 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x2)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x03, 0, 0" 0348 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x03, 0, 0" 0348 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x3)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "infsnz 0x04, 0, 0" 0448 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (+ (load 0 (bv 24 0x4)) (bv 8 0x1))) (store 0 (bv 24 0xfe8) (var __res)) (branch (! (is_zero (var __res))) (set _skip (bv 8 0x1)) nop))) +d "iorlw 0x0" 0009 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x0))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x0" 0009 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x0))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x1" 0109 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x1" 0109 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x1))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x2" 0209 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x2))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x2" 0209 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x2))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x3" 0309 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x3))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x3" 0309 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x3))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorlw 0x4" 0409 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (| (load 0 (bv 24 0xfe8)) (bv 8 0x4))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "iorwf 0x00, 0, 0" 0010 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x00, 0, 0" 0010 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x01, 0, 0" 0110 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x01, 0, 0" 0110 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x02, 0, 0" 0210 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x02, 0, 0" 0210 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x03, 0, 0" 0310 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x03, 0, 0" 0310 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "iorwf 0x04, 0, 0" 0410 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (| (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x4)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x00, 0, 0" 0050 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x0))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x00, 0, 0" 0050 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x0))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x01, 0, 0" 0150 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x1))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x01, 0, 0" 0150 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x1))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x02, 0, 0" 0250 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x2))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x02, 0, 0" 0250 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x2))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x03, 0, 0" 0350 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x3))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x03, 0, 0" 0350 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x3))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movf 0x04, 0, 0" 0450 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (load 0 (bv 24 0x4))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "movlb 0x0" 0001 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x0) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x0" 0001 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x0) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x1" 0101 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x1) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x1" 0101 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x1) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x2" 0201 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x2) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x2" 0201 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x2) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x3" 0301 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x3) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x3" 0301 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x3) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlb 0x4" 0401 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe0) (| (bv 8 0x4) (& (load 0 (bv 24 0xfe0)) (bv 8 0xf0))))) +d "movlw 0x0" 000e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x0))) +d "movlw 0x0" 000e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x0))) +d "movlw 0x1" 010e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x1))) +d "movlw 0x1" 010e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x1))) +d "movlw 0x2" 020e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x2))) +d "movlw 0x2" 020e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x2))) +d "movlw 0x3" 030e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x3))) +d "movlw 0x3" 030e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x3))) +d "movlw 0x4" 040e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (bv 8 0x4))) +d "movwf 0x00, 0" 006e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (load 0 (bv 24 0xfe8)))) +d "movwf 0x00, 0" 006e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (load 0 (bv 24 0xfe8)))) +d "movwf 0x01, 0" 016e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (load 0 (bv 24 0xfe8)))) +d "movwf 0x01, 0" 016e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (load 0 (bv 24 0xfe8)))) +d "movwf 0x02, 0" 026e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (load 0 (bv 24 0xfe8)))) +d "movwf 0x02, 0" 026e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (load 0 (bv 24 0xfe8)))) +d "movwf 0x03, 0" 036e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (load 0 (bv 24 0xfe8)))) +d "movwf 0x03, 0" 036e 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (load 0 (bv 24 0xfe8)))) +d "movwf 0x04, 0" 046e 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x4) (load 0 (bv 24 0xfe8)))) +d "mullw 0x0" 000d 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x0))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x0" 000d 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x0))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x1" 010d 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x1))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x1" 010d 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x1))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x2" 020d 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x2))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x2" 020d 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x2))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x3" 030d 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x3))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x3" 030d 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x3))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mullw 0x4" 040d 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (bv 16 0x4))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x00, 0" 0002 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x0))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x00, 0" 0002 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x0))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x01, 0" 0102 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x1))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x01, 0" 0102 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x1))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x02, 0" 0202 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x2))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x02, 0" 0202 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x2))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x03, 0" 0302 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x3))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x03, 0" 0302 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x3))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "mulwf 0x04, 0" 0402 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (* (cast 16 false (load 0 (bv 24 0xfe8))) (cast 16 false (load 0 (bv 24 0x4))))) (store 0 (bv 24 0xff4) (cast 8 false (>> (var __res) (bv 8 0x8) false))) (store 0 (bv 24 0xff3) (cast 8 false (var __res))))) +d "negf 0x00, 0" 006c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x0)))))) +d "negf 0x00, 0" 006c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x0)))))) +d "negf 0x01, 0" 016c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x1)))))) +d "negf 0x01, 0" 016c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x1)))))) +d "negf 0x02, 0" 026c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x2)))))) +d "negf 0x02, 0" 026c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x2)))))) +d "negf 0x03, 0" 036c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x3)))))) +d "negf 0x03, 0" 036c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x3)))))) +d "negf 0x04, 0" 046c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x4) (+ (bv 8 0x1) (~- (load 0 (bv 24 0x4)))))) +d "nop" 0000 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 0000 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 00f0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 00f0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 01f0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 01f0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 02f0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 02f0 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "nop" 03f0 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "pop" 0600 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))))) +d "pop" 0600 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))))) +d "push" 0500 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0x0)) (set __x (bv 24 0x0)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))))) +d "push" 0500 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0xff00)) (set __x (bv 24 0xff00)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))))) +d "rcall 0x0" 00d8 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0x2)) (set __x (bv 24 0x2)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0x2)))) +d "rcall 0x0" 00d8 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0xff02)) (set __x (bv 24 0xff02)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0xff02)))) +d "rcall 0x1" 01d8 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0x2)) (set __x (bv 24 0x2)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0x4)))) +d "rcall 0x1" 01d8 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0xff02)) (set __x (bv 24 0xff02)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0xff04)))) +d "rcall 0x2" 02d8 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0x2)) (set __x (bv 24 0x2)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0x6)))) +d "rcall 0x2" 02d8 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0xff02)) (set __x (bv 24 0xff02)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0xff06)))) +d "rcall 0x3" 03d8 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0x2)) (set __x (bv 24 0x2)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0x8)))) +d "rcall 0x3" 03d8 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0xff02)) (set __x (bv 24 0xff02)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0xff08)))) +d "rcall 0x4" 04d8 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xffc) (+ (load 0 (bv 24 0xffc)) (bv 8 0x4))) (storew 0 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))) (bv 24 0x2)) (set __x (bv 24 0x2)) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (bv 24 0xa)))) +d "reset" ff00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "reset" ff00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "retfie 0" 1000 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (branch (! (! (is_zero (& (load 0 (bv 24 0xfd0)) (bv 8 0x80))))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))) (branch (! (is_zero (& (load 0 (bv 24 0xff2)) (bv 8 0x80)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x40)) (& (load 0 (bv 24 0xff2)) (bv 8 0xbf)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))))) nop (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retfie 0" 1000 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (branch (! (! (is_zero (& (load 0 (bv 24 0xfd0)) (bv 8 0x80))))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))) (branch (! (is_zero (& (load 0 (bv 24 0xff2)) (bv 8 0x80)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x40)) (& (load 0 (bv 24 0xff2)) (bv 8 0xbf)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))))) nop (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retfie 1" 1100 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (branch (! (! (is_zero (& (load 0 (bv 24 0xfd0)) (bv 8 0x80))))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))) (branch (! (is_zero (& (load 0 (bv 24 0xff2)) (bv 8 0x80)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x40)) (& (load 0 (bv 24 0xff2)) (bv 8 0xbf)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))))) (set wregs (load 0 (bv 24 0xfe8))) (set statuss (load 0 (bv 24 0xfd8))) (set bsrs (load 0 (bv 24 0xfe0))) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retfie 1" 1100 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (branch (! (! (is_zero (& (load 0 (bv 24 0xfd0)) (bv 8 0x80))))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))) (branch (! (is_zero (& (load 0 (bv 24 0xff2)) (bv 8 0x80)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x40)) (& (load 0 (bv 24 0xff2)) (bv 8 0xbf)))) (store 0 (bv 24 0xff2) (ite true (| (load 0 (bv 24 0xff2)) (bv 8 0x80)) (& (load 0 (bv 24 0xff2)) (bv 8 0x7f)))))) (set wregs (load 0 (bv 24 0xfe8))) (set statuss (load 0 (bv 24 0xfd8))) (set bsrs (load 0 (bv 24 0xfe0))) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x0" 000c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x0)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x0" 000c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x0)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x1" 010c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x1)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x1" 010c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x1)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x2" 020c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x2)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x2" 020c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x2)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x3" 030c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x3)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x3" 030c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x3)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "retlw 0x4" 040c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (bv 8 0x4)) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "return 0" 1200 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq nop (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "return 0" 1200 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq nop (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "return 1" 1300 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set wregs (load 0 (bv 24 0xfe8))) (set statuss (load 0 (bv 24 0xfd8))) (set bsrs (load 0 (bv 24 0xfe0))) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "return 1" 1300 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set wregs (load 0 (bv 24 0xfe8))) (set statuss (load 0 (bv 24 0xfd8))) (set bsrs (load 0 (bv 24 0xfe0))) (set _pc (append (load 0 (bv 24 0xfff)) (append (load 0 (bv 24 0xffe)) (load 0 (bv 24 0xffd))))) (store 0 (bv 24 0xffc) (- (load 0 (bv 24 0xffc)) (bv 8 0x4))) (set __x (loadw 0 24 (cast 24 false (+ (var _stack) (load 0 (bv 24 0xffc)))))) (store 0 (bv 24 0xfff) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xffe) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xffd) (cast 8 false (var __x))) (jmp (var _pc)))) +d "rlcf 0x00, 0, 0" 0034 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x0))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x00, 0, 0" 0034 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x0))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x01, 0, 0" 0134 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x1))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x01, 0, 0" 0134 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x1))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x02, 0, 0" 0234 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x2))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x02, 0, 0" 0234 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x2))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x03, 0, 0" 0334 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x3))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x03, 0, 0" 0334 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x3))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlcf 0x04, 0, 0" 0434 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x4))) (store 0 (bv 24 0xfd8) (ite (msb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (<< (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x00, 0, 0" 0044 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x0)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x00, 0, 0" 0044 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x0)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x01, 0, 0" 0144 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x1)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x01, 0, 0" 0144 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x1)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x02, 0, 0" 0244 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x2)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x02, 0, 0" 0244 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x2)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x03, 0, 0" 0344 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x3)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x03, 0, 0" 0344 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x3)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rlncf 0x04, 0, 0" 0444 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x4)) (| (<< (var _x) (bv 8 0x7) false) (ite (msb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x00, 0, 0" 0030 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x0))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x00, 0, 0" 0030 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x0))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x01, 0, 0" 0130 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x1))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x01, 0, 0" 0130 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x1))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x02, 0, 0" 0230 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x2))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x02, 0, 0" 0230 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x2))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x03, 0, 0" 0330 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x3))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x03, 0, 0" 0330 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x3))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrcf 0x04, 0, 0" 0430 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set _x (load 0 (bv 24 0x4))) (store 0 (bv 24 0xfd8) (ite (lsb (var _x)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (set __res (| (>> (var _x) (bv 8 0x7) false) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x00, 0, 0" 0040 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x0)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x00, 0, 0" 0040 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x0)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x01, 0, 0" 0140 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x1)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x01, 0, 0" 0140 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x1)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x02, 0, 0" 0240 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x2)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x02, 0, 0" 0240 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x2)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x03, 0, 0" 0340 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x3)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x03, 0, 0" 0340 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x3)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "rrncf 0x04, 0, 0" 0440 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (let _x (load 0 (bv 24 0x4)) (| (>> (var _x) (bv 8 0x7) false) (ite (lsb (var _x)) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "setf 0x00, 0" 0068 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (bv 8 0xff))) +d "setf 0x00, 0" 0068 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x0) (bv 8 0xff))) +d "setf 0x01, 0" 0168 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (bv 8 0xff))) +d "setf 0x01, 0" 0168 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x1) (bv 8 0xff))) +d "setf 0x02, 0" 0268 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (bv 8 0xff))) +d "setf 0x02, 0" 0268 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x2) (bv 8 0xff))) +d "setf 0x03, 0" 0368 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (bv 8 0xff))) +d "setf 0x03, 0" 0368 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x3) (bv 8 0xff))) +d "setf 0x04, 0" 0468 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0x4) (bv 8 0xff))) +d "sleep" 0300 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "sleep" 0300 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) nop) +d "subfwb 0x00, 0, 0" 0054 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x0)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x0)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x0))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x00, 0, 0" 0054 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x0)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x0)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x0))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x01, 0, 0" 0154 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x1)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x1)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x1))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x01, 0, 0" 0154 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x1)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x1)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x1))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x02, 0, 0" 0254 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x2)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x2)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x2))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x02, 0, 0" 0254 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x2)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x2)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x2))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x03, 0, 0" 0354 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x3)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x3)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x3))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x03, 0, 0" 0354 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x3)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x3)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x3))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subfwb 0x04, 0, 0" 0454 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0xfe8)) (+ (load 0 (bv 24 0x4)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (load 0 (bv 24 0x4)))) (&& (! (msb (load 0 (bv 24 0xfe8)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0xfe8))) (&& (msb (load 0 (bv 24 0x4))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x0" 0008 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x0) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x0))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x0))) (msb (var __res)))) (&& (msb (bv 8 0x0)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x0)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x0" 0008 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x0) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x0))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x0))) (msb (var __res)))) (&& (msb (bv 8 0x0)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x0) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x0)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x1" 0108 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x1) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x1))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x1))) (msb (var __res)))) (&& (msb (bv 8 0x1)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x1)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x1" 0108 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x1) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x1))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x1))) (msb (var __res)))) (&& (msb (bv 8 0x1)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x1) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x1)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x2" 0208 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x2) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x2))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x2))) (msb (var __res)))) (&& (msb (bv 8 0x2)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x2)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x2" 0208 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x2) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x2))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x2))) (msb (var __res)))) (&& (msb (bv 8 0x2)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x2) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x2)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x3" 0308 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x3) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x3))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x3))) (msb (var __res)))) (&& (msb (bv 8 0x3)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x3)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x3" 0308 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x3) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x3))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x3))) (msb (var __res)))) (&& (msb (bv 8 0x3)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x3) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x3)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "sublw 0x4" 0408 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (bv 8 0x4) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (bv 8 0x4))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (bv 8 0x4))) (msb (var __res)))) (&& (msb (bv 8 0x4)) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (bv 8 0x4) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (bv 8 0x4) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (bv 8 0x4) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (bv 8 0x4)) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x00, 0, 0" 005c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x0)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x0)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x0))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x00, 0, 0" 005c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x0)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x0)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x0))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x01, 0, 0" 015c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x1)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x1)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x1))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x01, 0, 0" 015c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x1)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x1)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x1))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x02, 0, 0" 025c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x2)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x2)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x2))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x02, 0, 0" 025c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x2)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x2)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x2))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x03, 0, 0" 035c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x3)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x3)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x3))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x03, 0, 0" 035c 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x3)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x3)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x3))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwf 0x04, 0, 0" 045c 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x4)) (load 0 (bv 24 0xfe8)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x4)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x4)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x4))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x00, 0, 0" 0058 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x0)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x0)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x0))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x00, 0, 0" 0058 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x0)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x0)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x0)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x0))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x0)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x0))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x01, 0, 0" 0158 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x1)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x1)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x1))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x01, 0, 0" 0158 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x1)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x1)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x1)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x1))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x1)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x1))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x02, 0, 0" 0258 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x2)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x2)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x2))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x02, 0, 0" 0258 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x2)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x2)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x2)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x2))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x2)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x2))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x03, 0, 0" 0358 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x3)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x3)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x3))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x03, 0, 0" 0358 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x3)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x3)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x3)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x3))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x3)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x3))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "subwfb 0x04, 0, 0" 0458 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (- (load 0 (bv 24 0x4)) (+ (load 0 (bv 24 0xfe8)) (ite (! (is_zero (& (load 0 (bv 24 0xfd8)) (bv 8 0x1)))) (bv 8 0x1) (bv 8 0x0))))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (msb (load 0 (bv 24 0x4)))) (msb (load 0 (bv 24 0xfe8)))) (&& (! (msb (load 0 (bv 24 0x4)))) (msb (var __res)))) (&& (msb (load 0 (bv 24 0x4))) (&& (msb (load 0 (bv 24 0xfe8))) (msb (var __res))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x1)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfe)))) (store 0 (bv 24 0xfd8) (ite (|| (|| (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false)))) (&& (! (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false)))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false))))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0x4)) (bv 32 0x3) false))) (&& (is_zero (cast 1 false (>> (load 0 (bv 24 0xfe8)) (bv 32 0x3) false))) (is_zero (cast 1 false (>> (var __res) (bv 32 0x3) false)))))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x2)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfd)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (&& (^^ (msb (load 0 (bv 24 0x4))) (msb (var __res))) (^^ (msb (load 0 (bv 24 0xfe8))) (msb (var __res)))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x8)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xf7)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "swapf 0x00, 0, 0" 0038 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x0))) (cast 4 false (>> (load 0 (bv 24 0x0)) (bv 8 0x4) false))))) +d "swapf 0x00, 0, 0" 0038 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x0))) (cast 4 false (>> (load 0 (bv 24 0x0)) (bv 8 0x4) false))))) +d "swapf 0x01, 0, 0" 0138 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x1))) (cast 4 false (>> (load 0 (bv 24 0x1)) (bv 8 0x4) false))))) +d "swapf 0x01, 0, 0" 0138 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x1))) (cast 4 false (>> (load 0 (bv 24 0x1)) (bv 8 0x4) false))))) +d "swapf 0x02, 0, 0" 0238 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x2))) (cast 4 false (>> (load 0 (bv 24 0x2)) (bv 8 0x4) false))))) +d "swapf 0x02, 0, 0" 0238 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x2))) (cast 4 false (>> (load 0 (bv 24 0x2)) (bv 8 0x4) false))))) +d "swapf 0x03, 0, 0" 0338 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x3))) (cast 4 false (>> (load 0 (bv 24 0x3)) (bv 8 0x4) false))))) +d "swapf 0x03, 0, 0" 0338 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x3))) (cast 4 false (>> (load 0 (bv 24 0x3)) (bv 8 0x4) false))))) +d "swapf 0x04, 0, 0" 0438 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xfe8) (append (cast 4 false (load 0 (bv 24 0x4))) (cast 4 false (>> (load 0 (bv 24 0x4)) (bv 8 0x4) false))))) +d "tblrd*" 0800 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6))))))) +d "tblrd*" 0800 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6))))))) +d "tblrd*+" 0900 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))))) (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblrd*+" 0900 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))))) (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblrd*-" 0a00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))))) (set __x (- (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblrd*-" 0a00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))))) (set __x (- (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblrd+*" 0b00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))) (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))))))) +d "tblrd+*" 0b00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))) (store 0 (bv 24 0xff5) (load 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))))))) +d "tblwt*" 0c00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5)))) +d "tblwt*" 0c00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5)))) +d "tblwt*+" 0d00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5))) (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblwt*+" 0d00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5))) (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblwt*-" 0e00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5))) (set __x (- (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblwt*-" 0e00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5))) (set __x (- (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))))) +d "tblwt+*" 0f00 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))) (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5))))) +d "tblwt+*" 0f00 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __x (+ (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (bv 24 0x1))) (store 0 (bv 24 0xff8) (cast 8 false (>> (var __x) (bv 8 0x10) false))) (set __x (var __x)) (store 0 (bv 24 0xff7) (cast 8 false (>> (var __x) (bv 8 0x8) false))) (store 0 (bv 24 0xff6) (cast 8 false (var __x))) (store 0 (append (load 0 (bv 24 0xff8)) (append (load 0 (bv 24 0xff7)) (load 0 (bv 24 0xff6)))) (load 0 (bv 24 0xff5))))) +d "tstfsz 0x00, 0" 0066 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x0))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x00, 0" 0066 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x0))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x01, 0" 0166 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x1))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x01, 0" 0166 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x1))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x02, 0" 0266 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x2))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x02, 0" 0266 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x2))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x03, 0" 0366 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x3))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x03, 0" 0366 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x3))) (set _skip (bv 8 0x1)) nop)) +d "tstfsz 0x04, 0" 0466 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (branch (is_zero (load 0 (bv 24 0x4))) (set _skip (bv 8 0x1)) nop)) +d "xorlw 0x0" 000a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x0" 000a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x1" 010a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x1" 010a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x2" 020a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x2" 020a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x3" 030a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x3" 030a 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorlw 0x4" 040a 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (store 0 (bv 24 0xfe8) (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (load 0 (bv 24 0xfe8))) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))))) +d "xorwf 0x00, 0, 0" 0018 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x00, 0, 0" 0018 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x0)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x01, 0, 0" 0118 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x01, 0, 0" 0118 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x1)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x02, 0, 0" 0218 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x02, 0, 0" 0218 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x2)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x03, 0, 0" 0318 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x03, 0, 0" 0318 0x00ff00 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x3)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) +d "xorwf 0x04, 0, 0" 0418 0x000000 (branch (! (is_zero (var _skip))) (set _skip (bv 8 0x0)) (seq (set __res (^ (load 0 (bv 24 0xfe8)) (load 0 (bv 24 0x4)))) (store 0 (bv 24 0xfd8) (ite (is_zero (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x4)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xfb)))) (store 0 (bv 24 0xfd8) (ite (msb (var __res)) (| (load 0 (bv 24 0xfd8)) (bv 8 0x10)) (& (load 0 (bv 24 0xfd8)) (bv 8 0xef)))) (store 0 (bv 24 0xfe8) (var __res)))) diff --git a/test/db/cmd/cmd_list b/test/db/cmd/cmd_list index 66436970289..9adfd8d9db9 100644 --- a/test/db/cmd/cmd_list +++ b/test/db/cmd/cmd_list @@ -412,7 +412,7 @@ adAe_ 16 32 64 mips BSD Capstone MIPS disassembler _dA__ 16 msp430 LGPL3 msp430 disassembly plugin adA__ 16 32 64 null MIT no disassemble (by pancake) v1.0.0 _dA__ 32 or1k LGPL3 OpenRISC 1000 -_dAe_ 8 pic LGPL3 PIC disassembler +_dAeI 8 pic LGPL3 PIC disassembler a____ 32 64 ppc.as LGPL3 as PPC Assembler (use RZ_PPC_AS environment) (by eagleoflqj) _dAeI 32 64 ppc BSD Capstone PowerPC disassembler (by pancake) _dA__ 32 propeller LGPL3 propeller disassembly plugin diff --git a/test/db/rzil/pic b/test/db/rzil/pic new file mode 100644 index 00000000000..11b37e1a652 --- /dev/null +++ b/test/db/rzil/pic @@ -0,0 +1,46 @@ +NAME=Testing the decryption in emulateme +FILE=bins/pic/emulateme.pic18f2520.elf +TIMEOUT=30 +CMDS=<