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vec_helper.c
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/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* QEMU LoongArch vector helper functions.
*
* Copyright (c) 2022-2023 Loongson Technology Corporation Limited
*/
#include "qemu/osdep.h"
#include "cpu.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
#include "internals.h"
// #include "tcg/tcg.h"
#include "vec.h"
#include "tcg/tcg-gvec-desc.h"
#include "exec/memop.h"
#define dup_const(VECE, C) \
(__builtin_constant_p(VECE) \
? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \
: (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \
: (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \
: (VECE) == MO_64 ? (uint64_t)(C) \
: (qemu_build_not_reached_always(), 0)) \
: dup_const(VECE, C))
/* Duplicate C as per VECE. */
uint64_t (dup_const)(unsigned vece, uint64_t c)
{
switch (vece) {
case MO_8:
return 0x0101010101010101ull * (uint8_t)c;
case MO_16:
return 0x0001000100010001ull * (uint16_t)c;
case MO_32:
return 0x0000000100000001ull * (uint32_t)c;
case MO_64:
return c;
default:
g_assert_not_reached();
}
}
# define tcg_debug_assert(X) \
do { if (!(X)) { __builtin_unreachable(); } } while (0)
/* Verify vector size and alignment rules. OFS should be the OR of all
of the operand offsets so that we can check them all at once. */
static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs)
{
uint32_t max_align;
switch (oprsz) {
case 8:
case 16:
case 32:
tcg_debug_assert(oprsz <= maxsz);
break;
default:
tcg_debug_assert(oprsz == maxsz);
break;
}
tcg_debug_assert(maxsz <= (8 << SIMD_MAXSZ_BITS));
max_align = maxsz >= 16 ? 15 : 7;
tcg_debug_assert((maxsz & max_align) == 0);
tcg_debug_assert((ofs & max_align) == 0);
}
/* Create a descriptor from components. */
uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data)
{
uint32_t desc = 0;
check_size_align(oprsz, maxsz, 0);
tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));
oprsz = (oprsz / 8) - 1;
maxsz = (maxsz / 8) - 1;
/*
* We have just asserted in check_size_align that either
* oprsz is {8,16,32} or matches maxsz. Encode the final
* case with '2', as that would otherwise map to 24.
*/
if (oprsz == maxsz) {
oprsz = 2;
}
desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz);
desc = deposit32(desc, SIMD_MAXSZ_SHIFT, SIMD_MAXSZ_BITS, maxsz);
desc = deposit32(desc, SIMD_DATA_SHIFT, SIMD_DATA_BITS, data);
return desc;
}
#define DO_ODD_EVEN(NAME, BIT, E1, E2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->E1(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E1(i) = DO_OP((TD)Vj->E2(2 * i + 1), (TD)Vk->E2(2 * i)); \
} \
}
DO_ODD_EVEN(vhaddw_h_b, 16, H, B, DO_ADD)
DO_ODD_EVEN(vhaddw_w_h, 32, W, H, DO_ADD)
DO_ODD_EVEN(vhaddw_d_w, 64, D, W, DO_ADD)
void HELPER(vhaddw_q_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16 ; i++) {
Vd->Q(i) = int128_add(int128_makes64(Vj->D(2 * i + 1)),
int128_makes64(Vk->D(2 * i)));
}
}
DO_ODD_EVEN(vhsubw_h_b, 16, H, B, DO_SUB)
DO_ODD_EVEN(vhsubw_w_h, 32, W, H, DO_SUB)
DO_ODD_EVEN(vhsubw_d_w, 64, D, W, DO_SUB)
void HELPER(vhsubw_q_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_sub(int128_makes64(Vj->D(2 * i + 1)),
int128_makes64(Vk->D(2 * i)));
}
}
DO_ODD_EVEN(vhaddw_hu_bu, 16, UH, UB, DO_ADD)
DO_ODD_EVEN(vhaddw_wu_hu, 32, UW, UH, DO_ADD)
DO_ODD_EVEN(vhaddw_du_wu, 64, UD, UW, DO_ADD)
void HELPER(vhaddw_qu_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i ++) {
Vd->Q(i) = int128_add(int128_make64(Vj->UD(2 * i + 1)),
int128_make64(Vk->UD(2 * i)));
}
}
DO_ODD_EVEN(vhsubw_hu_bu, 16, UH, UB, DO_SUB)
DO_ODD_EVEN(vhsubw_wu_hu, 32, UW, UH, DO_SUB)
DO_ODD_EVEN(vhsubw_du_wu, 64, UD, UW, DO_SUB)
void HELPER(vhsubw_qu_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_sub(int128_make64(Vj->UD(2 * i + 1)),
int128_make64(Vk->UD(2 * i)));
}
}
#define DO_EVEN(NAME, BIT, E1, E2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->E1(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E1(i) = DO_OP((TD)Vj->E2(2 * i) ,(TD)Vk->E2(2 * i)); \
} \
}
#define DO_ODD(NAME, BIT, E1, E2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->E1(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E1(i) = DO_OP((TD)Vj->E2(2 * i + 1), (TD)Vk->E2(2 * i + 1)); \
} \
}
void HELPER(vaddwev_q_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_add(int128_makes64(Vj->D(2 * i)),
int128_makes64(Vk->D(2 * i)));
}
}
DO_EVEN(vaddwev_h_b, 16, H, B, DO_ADD)
DO_EVEN(vaddwev_w_h, 32, W, H, DO_ADD)
DO_EVEN(vaddwev_d_w, 64, D, W, DO_ADD)
void HELPER(vaddwod_q_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_add(int128_makes64(Vj->D(2 * i +1)),
int128_makes64(Vk->D(2 * i +1)));
}
}
DO_ODD(vaddwod_h_b, 16, H, B, DO_ADD)
DO_ODD(vaddwod_w_h, 32, W, H, DO_ADD)
DO_ODD(vaddwod_d_w, 64, D, W, DO_ADD)
void HELPER(vsubwev_q_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_sub(int128_makes64(Vj->D(2 * i)),
int128_makes64(Vk->D(2 * i)));
}
}
DO_EVEN(vsubwev_h_b, 16, H, B, DO_SUB)
DO_EVEN(vsubwev_w_h, 32, W, H, DO_SUB)
DO_EVEN(vsubwev_d_w, 64, D, W, DO_SUB)
void HELPER(vsubwod_q_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_sub(int128_makes64(Vj->D(2 * i + 1)),
int128_makes64(Vk->D(2 * i + 1)));
}
}
DO_ODD(vsubwod_h_b, 16, H, B, DO_SUB)
DO_ODD(vsubwod_w_h, 32, W, H, DO_SUB)
DO_ODD(vsubwod_d_w, 64, D, W, DO_SUB)
void HELPER(vaddwev_q_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_add(int128_make64(Vj->UD(2 * i)),
int128_make64(Vk->UD(2 * i)));
}
}
DO_EVEN(vaddwev_h_bu, 16, UH, UB, DO_ADD)
DO_EVEN(vaddwev_w_hu, 32, UW, UH, DO_ADD)
DO_EVEN(vaddwev_d_wu, 64, UD, UW, DO_ADD)
void HELPER(vaddwod_q_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_add(int128_make64(Vj->UD(2 * i + 1)),
int128_make64(Vk->UD(2 * i + 1)));
}
}
DO_ODD(vaddwod_h_bu, 16, UH, UB, DO_ADD)
DO_ODD(vaddwod_w_hu, 32, UW, UH, DO_ADD)
DO_ODD(vaddwod_d_wu, 64, UD, UW, DO_ADD)
void HELPER(vsubwev_q_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_sub(int128_make64(Vj->UD(2 * i)),
int128_make64(Vk->UD(2 * i)));
}
}
DO_EVEN(vsubwev_h_bu, 16, UH, UB, DO_SUB)
DO_EVEN(vsubwev_w_hu, 32, UW, UH, DO_SUB)
DO_EVEN(vsubwev_d_wu, 64, UD, UW, DO_SUB)
void HELPER(vsubwod_q_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_sub(int128_make64(Vj->UD(2 * i + 1)),
int128_make64(Vk->UD(2 * i + 1)));
}
}
DO_ODD(vsubwod_h_bu, 16, UH, UB, DO_SUB)
DO_ODD(vsubwod_w_hu, 32, UW, UH, DO_SUB)
DO_ODD(vsubwod_d_wu, 64, UD, UW, DO_SUB)
#define DO_EVEN_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->ES1(0)) TDS; \
typedef __typeof(Vd->EU1(0)) TDU; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->ES1(i) = DO_OP((TDU)Vj->EU2(2 * i) ,(TDS)Vk->ES2(2 * i)); \
} \
}
#define DO_ODD_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->ES1(0)) TDS; \
typedef __typeof(Vd->EU1(0)) TDU; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->ES1(i) = DO_OP((TDU)Vj->EU2(2 * i + 1), (TDS)Vk->ES2(2 * i + 1)); \
} \
}
void HELPER(vaddwev_q_du_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_add(int128_make64(Vj->UD(2 * i)),
int128_makes64(Vk->D(2 * i)));
}
}
DO_EVEN_U_S(vaddwev_h_bu_b, 16, H, UH, B, UB, DO_ADD)
DO_EVEN_U_S(vaddwev_w_hu_h, 32, W, UW, H, UH, DO_ADD)
DO_EVEN_U_S(vaddwev_d_wu_w, 64, D, UD, W, UW, DO_ADD)
void HELPER(vaddwod_q_du_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_add(int128_make64(Vj->UD(2 * i + 1)),
int128_makes64(Vk->D(2 * i + 1)));
}
}
DO_ODD_U_S(vaddwod_h_bu_b, 16, H, UH, B, UB, DO_ADD)
DO_ODD_U_S(vaddwod_w_hu_h, 32, W, UW, H, UH, DO_ADD)
DO_ODD_U_S(vaddwod_d_wu_w, 64, D, UD, W, UW, DO_ADD)
#define DO_3OP(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \
} \
}
DO_3OP(vavg_b, 8, B, DO_VAVG)
DO_3OP(vavg_h, 16, H, DO_VAVG)
DO_3OP(vavg_w, 32, W, DO_VAVG)
DO_3OP(vavg_d, 64, D, DO_VAVG)
DO_3OP(vavgr_b, 8, B, DO_VAVGR)
DO_3OP(vavgr_h, 16, H, DO_VAVGR)
DO_3OP(vavgr_w, 32, W, DO_VAVGR)
DO_3OP(vavgr_d, 64, D, DO_VAVGR)
DO_3OP(vavg_bu, 8, UB, DO_VAVG)
DO_3OP(vavg_hu, 16, UH, DO_VAVG)
DO_3OP(vavg_wu, 32, UW, DO_VAVG)
DO_3OP(vavg_du, 64, UD, DO_VAVG)
DO_3OP(vavgr_bu, 8, UB, DO_VAVGR)
DO_3OP(vavgr_hu, 16, UH, DO_VAVGR)
DO_3OP(vavgr_wu, 32, UW, DO_VAVGR)
DO_3OP(vavgr_du, 64, UD, DO_VAVGR)
DO_3OP(vabsd_b, 8, B, DO_VABSD)
DO_3OP(vabsd_h, 16, H, DO_VABSD)
DO_3OP(vabsd_w, 32, W, DO_VABSD)
DO_3OP(vabsd_d, 64, D, DO_VABSD)
DO_3OP(vabsd_bu, 8, UB, DO_VABSD)
DO_3OP(vabsd_hu, 16, UH, DO_VABSD)
DO_3OP(vabsd_wu, 32, UW, DO_VABSD)
DO_3OP(vabsd_du, 64, UD, DO_VABSD)
#define DO_VADDA(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = DO_VABS(Vj->E(i)) + DO_VABS(Vk->E(i)); \
} \
}
DO_VADDA(vadda_b, 8, B)
DO_VADDA(vadda_h, 16, H)
DO_VADDA(vadda_w, 32, W)
DO_VADDA(vadda_d, 64, D)
#define VMINMAXI(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, uint64_t imm, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
typedef __typeof(Vd->E(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = DO_OP(Vj->E(i), (TD)imm); \
} \
}
VMINMAXI(vmini_b, 8, B, DO_MIN)
VMINMAXI(vmini_h, 16, H, DO_MIN)
VMINMAXI(vmini_w, 32, W, DO_MIN)
VMINMAXI(vmini_d, 64, D, DO_MIN)
VMINMAXI(vmaxi_b, 8, B, DO_MAX)
VMINMAXI(vmaxi_h, 16, H, DO_MAX)
VMINMAXI(vmaxi_w, 32, W, DO_MAX)
VMINMAXI(vmaxi_d, 64, D, DO_MAX)
VMINMAXI(vmini_bu, 8, UB, DO_MIN)
VMINMAXI(vmini_hu, 16, UH, DO_MIN)
VMINMAXI(vmini_wu, 32, UW, DO_MIN)
VMINMAXI(vmini_du, 64, UD, DO_MIN)
VMINMAXI(vmaxi_bu, 8, UB, DO_MAX)
VMINMAXI(vmaxi_hu, 16, UH, DO_MAX)
VMINMAXI(vmaxi_wu, 32, UW, DO_MAX)
VMINMAXI(vmaxi_du, 64, UD, DO_MAX)
#define DO_VMUH(NAME, BIT, E1, E2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->E1(0)) T; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E2(i) = ((T)Vj->E2(i)) * ((T)Vk->E2(i)) >> BIT; \
} \
}
void HELPER(vmuh_d)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
uint64_t l, h;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 8; i++) {
muls64(&l, &h, Vj->D(i), Vk->D(i));
Vd->D(i) = h;
}
}
DO_VMUH(vmuh_b, 8, H, B, DO_MUH)
DO_VMUH(vmuh_h, 16, W, H, DO_MUH)
DO_VMUH(vmuh_w, 32, D, W, DO_MUH)
void HELPER(vmuh_du)(void *vd, void *vj, void *vk, uint32_t desc)
{
int i;
uint64_t l, h;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
VReg *Vk = (VReg *)vk;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 8; i++) {
mulu64(&l, &h, Vj->D(i), Vk->D(i));
Vd->D(i) = h;
}
}
DO_VMUH(vmuh_bu, 8, UH, UB, DO_MUH)
DO_VMUH(vmuh_hu, 16, UW, UH, DO_MUH)
DO_VMUH(vmuh_wu, 32, UD, UW, DO_MUH)
DO_EVEN(vmulwev_h_b, 16, H, B, DO_MUL)
DO_EVEN(vmulwev_w_h, 32, W, H, DO_MUL)
DO_EVEN(vmulwev_d_w, 64, D, W, DO_MUL)
DO_ODD(vmulwod_h_b, 16, H, B, DO_MUL)
DO_ODD(vmulwod_w_h, 32, W, H, DO_MUL)
DO_ODD(vmulwod_d_w, 64, D, W, DO_MUL)
DO_EVEN(vmulwev_h_bu, 16, UH, UB, DO_MUL)
DO_EVEN(vmulwev_w_hu, 32, UW, UH, DO_MUL)
DO_EVEN(vmulwev_d_wu, 64, UD, UW, DO_MUL)
DO_ODD(vmulwod_h_bu, 16, UH, UB, DO_MUL)
DO_ODD(vmulwod_w_hu, 32, UW, UH, DO_MUL)
DO_ODD(vmulwod_d_wu, 64, UD, UW, DO_MUL)
DO_EVEN_U_S(vmulwev_h_bu_b, 16, H, UH, B, UB, DO_MUL)
DO_EVEN_U_S(vmulwev_w_hu_h, 32, W, UW, H, UH, DO_MUL)
DO_EVEN_U_S(vmulwev_d_wu_w, 64, D, UD, W, UW, DO_MUL)
DO_ODD_U_S(vmulwod_h_bu_b, 16, H, UH, B, UB, DO_MUL)
DO_ODD_U_S(vmulwod_w_hu_h, 32, W, UW, H, UH, DO_MUL)
DO_ODD_U_S(vmulwod_d_wu_w, 64, D, UD, W, UW, DO_MUL)
#define VMADDSUB(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = DO_OP(Vd->E(i), Vj->E(i) ,Vk->E(i)); \
} \
}
VMADDSUB(vmadd_b, 8, B, DO_MADD)
VMADDSUB(vmadd_h, 16, H, DO_MADD)
VMADDSUB(vmadd_w, 32, W, DO_MADD)
VMADDSUB(vmadd_d, 64, D, DO_MADD)
VMADDSUB(vmsub_b, 8, B, DO_MSUB)
VMADDSUB(vmsub_h, 16, H, DO_MSUB)
VMADDSUB(vmsub_w, 32, W, DO_MSUB)
VMADDSUB(vmsub_d, 64, D, DO_MSUB)
#define VMADDWEV(NAME, BIT, E1, E2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->E1(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E1(i) += DO_OP((TD)Vj->E2(2 * i), (TD)Vk->E2(2 * i)); \
} \
}
VMADDWEV(vmaddwev_h_b, 16, H, B, DO_MUL)
VMADDWEV(vmaddwev_w_h, 32, W, H, DO_MUL)
VMADDWEV(vmaddwev_d_w, 64, D, W, DO_MUL)
VMADDWEV(vmaddwev_h_bu, 16, UH, UB, DO_MUL)
VMADDWEV(vmaddwev_w_hu, 32, UW, UH, DO_MUL)
VMADDWEV(vmaddwev_d_wu, 64, UD, UW, DO_MUL)
#define VMADDWOD(NAME, BIT, E1, E2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->E1(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E1(i) += DO_OP((TD)Vj->E2(2 * i + 1), \
(TD)Vk->E2(2 * i + 1)); \
} \
}
VMADDWOD(vmaddwod_h_b, 16, H, B, DO_MUL)
VMADDWOD(vmaddwod_w_h, 32, W, H, DO_MUL)
VMADDWOD(vmaddwod_d_w, 64, D, W, DO_MUL)
VMADDWOD(vmaddwod_h_bu, 16, UH, UB, DO_MUL)
VMADDWOD(vmaddwod_w_hu, 32, UW, UH, DO_MUL)
VMADDWOD(vmaddwod_d_wu, 64, UD, UW, DO_MUL)
#define VMADDWEV_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->ES1(0)) TS1; \
typedef __typeof(Vd->EU1(0)) TU1; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->ES1(i) += DO_OP((TU1)Vj->EU2(2 * i), \
(TS1)Vk->ES2(2 * i)); \
} \
}
VMADDWEV_U_S(vmaddwev_h_bu_b, 16, H, UH, B, UB, DO_MUL)
VMADDWEV_U_S(vmaddwev_w_hu_h, 32, W, UW, H, UH, DO_MUL)
VMADDWEV_U_S(vmaddwev_d_wu_w, 64, D, UD, W, UW, DO_MUL)
#define VMADDWOD_U_S(NAME, BIT, ES1, EU1, ES2, EU2, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
typedef __typeof(Vd->ES1(0)) TS1; \
typedef __typeof(Vd->EU1(0)) TU1; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->ES1(i) += DO_OP((TU1)Vj->EU2(2 * i + 1), \
(TS1)Vk->ES2(2 * i + 1)); \
} \
}
VMADDWOD_U_S(vmaddwod_h_bu_b, 16, H, UH, B, UB, DO_MUL)
VMADDWOD_U_S(vmaddwod_w_hu_h, 32, W, UW, H, UH, DO_MUL)
VMADDWOD_U_S(vmaddwod_d_wu_w, 64, D, UD, W, UW, DO_MUL)
#define VDIV(NAME, BIT, E, DO_OP) \
void HELPER(NAME)(void *vd, void *vj, void *vk, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
VReg *Vk = (VReg *)vk; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = DO_OP(Vj->E(i), Vk->E(i)); \
} \
}
VDIV(vdiv_b, 8, B, DO_DIV)
VDIV(vdiv_h, 16, H, DO_DIV)
VDIV(vdiv_w, 32, W, DO_DIV)
VDIV(vdiv_d, 64, D, DO_DIV)
VDIV(vdiv_bu, 8, UB, DO_DIVU)
VDIV(vdiv_hu, 16, UH, DO_DIVU)
VDIV(vdiv_wu, 32, UW, DO_DIVU)
VDIV(vdiv_du, 64, UD, DO_DIVU)
VDIV(vmod_b, 8, B, DO_REM)
VDIV(vmod_h, 16, H, DO_REM)
VDIV(vmod_w, 32, W, DO_REM)
VDIV(vmod_d, 64, D, DO_REM)
VDIV(vmod_bu, 8, UB, DO_REMU)
VDIV(vmod_hu, 16, UH, DO_REMU)
VDIV(vmod_wu, 32, UW, DO_REMU)
VDIV(vmod_du, 64, UD, DO_REMU)
#define VSAT_S(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, uint64_t max, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
typedef __typeof(Vd->E(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = Vj->E(i) > (TD)max ? (TD)max : \
Vj->E(i) < (TD)~max ? (TD)~max: Vj->E(i); \
} \
}
VSAT_S(vsat_b, 8, B)
VSAT_S(vsat_h, 16, H)
VSAT_S(vsat_w, 32, W)
VSAT_S(vsat_d, 64, D)
#define VSAT_U(NAME, BIT, E) \
void HELPER(NAME)(void *vd, void *vj, uint64_t max, uint32_t desc) \
{ \
int i; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
typedef __typeof(Vd->E(0)) TD; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
Vd->E(i) = Vj->E(i) > (TD)max ? (TD)max : Vj->E(i); \
} \
}
VSAT_U(vsat_bu, 8, UB)
VSAT_U(vsat_hu, 16, UH)
VSAT_U(vsat_wu, 32, UW)
VSAT_U(vsat_du, 64, UD)
#define VEXTH(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint32_t desc) \
{ \
int i, j, ofs; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
ofs = LSX_LEN / BIT; \
for (i = 0; i < oprsz / 16; i++) { \
for (j = 0; j < ofs; j++) { \
Vd->E1(j + i * ofs) = Vj->E2(j + ofs + ofs * 2 * i); \
} \
} \
}
void HELPER(vexth_q_d)(void *vd, void *vj, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_makes64(Vj->D(2 * i + 1));
}
}
void HELPER(vexth_qu_du)(void *vd, void *vj, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
Vd->Q(i) = int128_make64(Vj->UD(2 * i + 1));
}
}
VEXTH(vexth_h_b, 16, H, B)
VEXTH(vexth_w_h, 32, W, H)
VEXTH(vexth_d_w, 64, D, W)
VEXTH(vexth_hu_bu, 16, UH, UB)
VEXTH(vexth_wu_hu, 32, UW, UH)
VEXTH(vexth_du_wu, 64, UD, UW)
#define VEXT2XV(NAME, BIT, E1, E2) \
void HELPER(NAME)(void *vd, void *vj, uint32_t desc) \
{ \
int i; \
VReg temp = {}; \
VReg *Vd = (VReg *)vd; \
VReg *Vj = (VReg *)vj; \
int oprsz = simd_oprsz(desc); \
\
for (i = 0; i < oprsz / (BIT / 8); i++) { \
temp.E1(i) = Vj->E2(i); \
} \
*Vd = temp; \
}
VEXT2XV(vext2xv_h_b, 16, H, B)
VEXT2XV(vext2xv_w_b, 32, W, B)
VEXT2XV(vext2xv_d_b, 64, D, B)
VEXT2XV(vext2xv_w_h, 32, W, H)
VEXT2XV(vext2xv_d_h, 64, D, H)
VEXT2XV(vext2xv_d_w, 64, D, W)
VEXT2XV(vext2xv_hu_bu, 16, UH, UB)
VEXT2XV(vext2xv_wu_bu, 32, UW, UB)
VEXT2XV(vext2xv_du_bu, 64, UD, UB)
VEXT2XV(vext2xv_wu_hu, 32, UW, UH)
VEXT2XV(vext2xv_du_hu, 64, UD, UH)
VEXT2XV(vext2xv_du_wu, 64, UD, UW)
DO_3OP(vsigncov_b, 8, B, DO_SIGNCOV)
DO_3OP(vsigncov_h, 16, H, DO_SIGNCOV)
DO_3OP(vsigncov_w, 32, W, DO_SIGNCOV)
DO_3OP(vsigncov_d, 64, D, DO_SIGNCOV)
static uint64_t do_vmskltz_b(int64_t val)
{
uint64_t m = 0x8080808080808080ULL;
uint64_t c = val & m;
c |= c << 7;
c |= c << 14;
c |= c << 28;
return c >> 56;
}
void HELPER(vmskltz_b)(void *vd, void *vj, uint32_t desc)
{
int i;
uint16_t temp = 0;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
temp = 0;
temp = do_vmskltz_b(Vj->D(2 * i));
temp |= (do_vmskltz_b(Vj->D(2 * i + 1)) << 8);
Vd->D(2 * i) = temp;
Vd->D(2 * i + 1) = 0;
}
}
static uint64_t do_vmskltz_h(int64_t val)
{
uint64_t m = 0x8000800080008000ULL;
uint64_t c = val & m;
c |= c << 15;
c |= c << 30;
return c >> 60;
}
void HELPER(vmskltz_h)(void *vd, void *vj, uint32_t desc)
{
int i;
uint16_t temp = 0;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
temp = 0;
temp = do_vmskltz_h(Vj->D(2 * i));
temp |= (do_vmskltz_h(Vj->D(2 * i + 1)) << 4);
Vd->D(2 * i) = temp;
Vd->D(2 * i + 1) = 0;
}
}
static uint64_t do_vmskltz_w(int64_t val)
{
uint64_t m = 0x8000000080000000ULL;
uint64_t c = val & m;
c |= c << 31;
return c >> 62;
}
void HELPER(vmskltz_w)(void *vd, void *vj, uint32_t desc)
{
int i;
uint16_t temp = 0;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
temp = 0;
temp = do_vmskltz_w(Vj->D(2 * i));
temp |= (do_vmskltz_w(Vj->D(2 * i + 1)) << 2);
Vd->D(2 * i) = temp;
Vd->D(2 * i + 1) = 0;
}
}
static uint64_t do_vmskltz_d(int64_t val)
{
return (uint64_t)val >> 63;
}
void HELPER(vmskltz_d)(void *vd, void *vj, uint32_t desc)
{
int i;
uint16_t temp = 0;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
temp = 0;
temp = do_vmskltz_d(Vj->D(2 * i));
temp |= (do_vmskltz_d(Vj->D(2 * i + 1)) << 1);
Vd->D(2 * i) = temp;
Vd->D(2 * i + 1) = 0;
}
}
void HELPER(vmskgez_b)(void *vd, void *vj, uint32_t desc)
{
int i;
uint16_t temp = 0;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
temp = 0;
temp = do_vmskltz_b(Vj->D(2 * i));
temp |= (do_vmskltz_b(Vj->D(2 * i + 1)) << 8);
Vd->D(2 * i) = (uint16_t)(~temp);
Vd->D(2 * i + 1) = 0;
}
}
static uint64_t do_vmskez_b(uint64_t a)
{
uint64_t m = 0x7f7f7f7f7f7f7f7fULL;
uint64_t c = ~(((a & m) + m) | a | m);
c |= c << 7;
c |= c << 14;
c |= c << 28;
return c >> 56;
}
void HELPER(vmsknz_b)(void *vd, void *vj, uint32_t desc)
{
int i;
uint16_t temp = 0;
VReg *Vd = (VReg *)vd;
VReg *Vj = (VReg *)vj;
int oprsz = simd_oprsz(desc);
for (i = 0; i < oprsz / 16; i++) {
temp = 0;
temp = do_vmskez_b(Vj->D(2 * i));
temp |= (do_vmskez_b(Vj->D(2 * i + 1)) << 8);
Vd->D(2 * i) = (uint16_t)(~temp);
Vd->D(2 * i + 1) = 0;
}
}
void HELPER(vnori_b)(void *vd, void *vj, uint64_t imm, uint32_t desc)
{
int i;
VReg *Vd = (VReg *)vd;