Rust 1.45+ generates suboptimal control flow for ARMv7 atomic compare exchange #123113
Labels
A-codegen
Area: Code generation
A-LLVM
Area: Code generation parts specific to LLVM. Both correctness bugs and optimization-related issues.
C-optimization
Category: An issue highlighting optimization opportunities or PRs implementing such
I-heavy
Issue: Problems and improvements with respect to binary size of generated code.
I-slow
Issue: Problems and improvements with respect to performance of generated code.
O-Arm
Target: 32-bit Arm processors (armv6, armv7, thumb...), including 64-bit Arm in AArch32 state
P-low
Low priority
regression-from-stable-to-stable
Performance or correctness regression from one stable version to another.
T-compiler
Relevant to the compiler team, which will review and decide on the PR/issue.
Code
I tried this code:
https://rust.godbolt.org/z/vP88v5GGc
I expected to see this happen:
A tight loop.
Instead, this happened:
In Rust 1.45 and later, LLVM generates a switch + unconditional branch to a conditional branch. This happens in opt-level=z, s, 1, 2, 3.
In some versions generates a dead branch, e.g.
Version it worked on
It most recently worked on: 1.44
Version with regression
rustc --version --verbose
:@rustbot modify labels: +regression-from-stable-to-stable -regression-untriaged
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