nandgate_sim.vcd

$version Generated by VerilatedVcd $end
$timescale 1ps $end
 $scope module TOP $end
  $var wire 1 / c $end
  $scope module nandgate_sim $end
   $var wire 1 / c $end
   $var wire 32 0 fd [31:0] $end
   $var wire 1 1 clk $end
   $var wire 32 + cycle [31:0] $end
   $var wire 1 # a_vectors[0] $end
   $var wire 1 $ a_vectors[1] $end
   $var wire 1 % a_vectors[2] $end
   $var wire 1 & a_vectors[3] $end
   $var wire 1 , a $end
   $var wire 1 ' b_vectors[0] $end
   $var wire 1 ( b_vectors[1] $end
   $var wire 1 ) b_vectors[2] $end
   $var wire 1 * b_vectors[3] $end
   $var wire 1 - b $end
   $scope module nandgate_dut $end
    $var wire 1 , a $end
    $var wire 1 - b $end
    $var wire 1 / c $end
    $var wire 1 / net1 $end
    $var wire 1 . net0 $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
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b10000000000000000000000000101100 0
01
#10
b00000000000000000000000000000001 +
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11
#20
01
#30
b00000000000000000000000000000010 +
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11
#40
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#50
b00000000000000000000000000000011 +
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11
#60
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#70
11