Discussion: Nits/ideas

[pathfinder49]

Fastino v1.2 performance is good and I see no need for further revisions. This issue is intened to collate ideas for future revisions, should any be attempted. If you have any nits, ideas or requests, pease add them here.

DAC-SPI signal reference-plane changes without ground vias

The SPI signals from the FPGA to the DACs change ground reference planes without nearby ground vias. This causes spreading of the digital return current, leading to EMI. We may want to adress this, especially in the area between the FPGA and DAC channel 8 (channel 9 in Altium). The solution would be twofold:

• Reduce the number of digital reference-layer changes and avoid changing ground reference plane where possible. For channel 20 (channel 21 in Altium), refenece layer changes can be avoided by routing the MOSI and CLK traces on L8, and LDAC on L6. This channel gives rise to the largest digital to analogue cross-talk in v1.2.
• Adding more vias to the fencing between the analogue and digital circuits may reduce return currents coupling to the analogue circuit.
• Any ground vias we can add in the yellow area should help localise the return currents (from reference-layer changes), reducing the associated EMI. Currently there are almost no ground vias in this area.
  

Analogue output pair reference (near the output connectors)

The analogue output pairs reference the nearby ground pours. However, the refenece for the pairs on L1 is split due to the pairs routed in L2. There is space on L5, so we may wish to move the L1 traces to L5 (adjacent to ground plane) and include ground vias when performing reference changes. However, the op-amp filter gives us fairly slow analogue rise-times, so we may not care.