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out.txt
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out.txt
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;; GCC machine description for IA-32 and x86-64.
;; Copyright (C) 1988, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
;; 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2012
;; Free Software Foundation, Inc.
;; Mostly by William Schelter.
;; x86_64 support added by Jan Hubicka
;;
;; This file is part of GCC.
;;
;; GCC is free software; you can redistribute it and/or modify
;; it under the terms of the GNU General Public License as published by
;; the Free Software Foundation; either version 3, or (at your option)
;; any later version.
;;
;; GCC is distributed in the hope that it will be useful,
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
;; GNU General Public License for more details.
;;
;; You should have received a copy of the GNU General Public License
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>. */
;;
;; The original PO technology requires these to be ordered by speed,
;; so that assigner will pick the fastest.
;;
;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
;;
;; The special asm out single letter directives following a '%' are:
;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
;; C -- print opcode suffix for set/cmov insn.
;; c -- like C, but print reversed condition
;; F,f -- likewise, but for floating-point.
;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
;; otherwise nothing
;; R -- print the prefix for register names.
;; z -- print the opcode suffix for the size of the current operand.
;; Z -- likewise, with special suffixes for x87 instructions.
;; * -- print a star (in certain assembler syntax)
;; A -- print an absolute memory reference.
;; E -- print address with DImode register names if TARGET_64BIT.
;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
;; s -- print a shift double count, followed by the assemblers argument
;; delimiter.
;; b -- print the QImode name of the register for the indicated operand.
;; %b0 would print %al if operands[0] is reg 0.
;; w -- likewise, print the HImode name of the register.
;; k -- likewise, print the SImode name of the register.
;; q -- likewise, print the DImode name of the register.
;; x -- likewise, print the V4SFmode name of the register.
;; t -- likewise, print the V8SFmode name of the register.
;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
;; y -- print "st(0)" instead of "st" as a register.
;; d -- print duplicated register operand for AVX instruction.
;; D -- print condition for SSE cmp instruction.
;; P -- if PIC, print an @PLT suffix.
;; p -- print raw symbol name.
;; X -- don't print any sort of PIC '@' suffix for a symbol.
;; & -- print some in-use local-dynamic symbol name.
;; H -- print a memory address offset by 8; used for sse high-parts
;; Y -- print condition for XOP pcom* instruction.
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
;; @ -- print a segment register of thread base pointer load
(define_c_enum "unspec" [
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
UNSPEC_GOT
])
(define_c_enum "unspecv" [
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
UNSPECV_BLOCKAGE
])
;; Constants to represent rounding modes in the ROUND instruction
(define_constants [ (ROUND_FLOOR 0x1)
(ROUND_CEIL 0x2)
(ROUND_TRUNC 0x3)
(ROUND_MXCSR 0x4)
(ROUND_NO_EXC 0x8)
])
;; Constants to represent pcomtrue/pcomfalse variants
;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
;; from i386.c.
;; In C guard expressions, put expressions which may be compile-time
;; constants first. This allows for better optimization. For
;; example, write "TARGET_64BIT && reload_completed", not
;; "reload_completed && TARGET_64BIT".
;; Processor type.
(define_attr "cpu"
"none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7,
atom,generic64,amdfam10,bdver1,bdver2,btver1"
(const (symbol_ref "ix86_schedule") ) )
;; A basic instruction type. Refinements due to arguments to be
;; provided in other attributes.
(define_attr "type"
"other,multi,
alu,alu1,negnot,imov,imovx,lea,
incdec,ishift,ishiftx,ishift1,rotate,rotatex,rotate1,imul,imulx,idiv,
icmp,test,ibr,setcc,icmov,
push,pop,call,callv,leave,
str,bitmanip,
fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,
ssemuladd,sse4arg,lwp, mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
(const_string "other") )
;; Main data type used by the insn
(define_attr "mode"
"unknown,none,QI,HI,SI,DI,TI,OI,SF,DF,XF,TF,V8SF,V4DF,V4SF,V2DF,V2SF,V1DF"
(const_string "unknown") )
;; The CPU unit operations uses.
(define_attr "unit"
"integer,i387,sse,mmx,unknown"
(cond [ (eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint"
) (const_string "i387") (eq_attr "type" "sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,
sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins,ssemuladd,sse4arg"
) (const_string "sse") (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
) (eq_attr "type" "mmx"
) (const_string "unknown") ](const_string "integer") ) )
;; The (bounding maximum) length of an instruction immediate.
(define_attr "length_immediate"
(cond [ (eq_attr "type" "incdec,setcc,icmov,str,lea,other,multi,idiv,leave, bitmanip,imulx"
) (const_int 0) (eq_attr "unit" "i387,sse,mmx"
) (const_int 0) (eq_attr "type" "alu,alu1,negnot,imovx,ishift,ishiftx,ishift1,
rotate,rotatex,rotate1,imul,icmp,push,pop"
) (symbol_ref "ix86_attr_length_immediate_default (insn, true)") (eq_attr "type" "imov,test"
) (symbol_ref "ix86_attr_length_immediate_default (insn, false)") (eq_attr "type" "call"
) (if_then_else (match_operand 0 "constant_call_address_operand" "") (const_int 4) (const_int 0) ) (eq_attr "type" "callv"
) (if_then_else (match_operand 1 "constant_call_address_operand" "") (const_int 4) (const_int 0) ) (eq_attr "type" "ibr"
) (const_int 1) ](symbol_ref "gcc_unreachable (),1") ) )
;; The (bounding maximum) length of an instruction address.
(define_attr "length_address"
(cond [ (eq_attr "type" "str,other,multi,fxch"
) (const_int 0) (and (eq_attr "type" "call"
) (match_operand 0 "constant_call_address_operand" "") ) (const_int 0) (and (eq_attr "type" "callv"
) (match_operand 1 "constant_call_address_operand" "") ) (const_int 0) ](symbol_ref "ix86_attr_length_address_default (insn)") ) )
;; Set when length prefix is used.
(define_attr "prefix_data16"
(cond [ (eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1"
) (const_int 0) (eq_attr "mode" "HI"
) (const_int 1) (and (eq_attr "unit" "sse"
) (eq_attr "mode" "V2DF,TI"
) ) (const_int 1) ](const_int 0) ) )
(define_attr "prefix_rep"
(cond [ (eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1"
) (const_int 0) (and (eq_attr "unit" "sse"
) (eq_attr "mode" "SF,DF"
) ) (const_int 1) ](const_int 0) ) )
(define_attr "prefix_0f"
(if_then_else (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip"
) (eq_attr "unit" "sse,mmx"
) ) (const_int 1) (const_int 0) ) )
(define_attr "prefix_rex"
(cond [ (not (match_test "TARGET_64BIT") ) (const_int 0) (and (eq_attr "mode" "DI"
) (and (eq_attr "type" "!push,pop,call,callv,leave,ibr"
) (eq_attr "unit" "!mmx"
) ) ) (const_int 1) (and (eq_attr "mode" "QI"
) (match_test "x86_extended_QIreg_mentioned_p (insn)") ) (const_int 1) (eq_attr "type" "imovx"
) (match_operand:QI 1 "ext_QIreg_operand" "") (const_int 1) ](const_int 0) ) )
;; There are also additional prefixes in 3DNOW, SSSE3.
;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
(define_attr "prefix_extra"
(cond [ (eq_attr "type" "ssemuladd,sse4arg"
) (const_int 2) (eq_attr "type" "sseiadd1,ssecvt1"
) (const_int 1) ](const_int 0) ) )
(define_attr "prefix"
"orig,vex,maybe_vex"
(if_then_else (eq_attr "mode" "OI,V8SF,V4DF"
) (const_string "vex") (const_string "orig") ) )
(define_attr "prefix_vex_w"
(const_int 0) )
;; The length of VEX prefix
;; Only instructions with 0f prefix can have 2 byte VEX prefix,
;; 0f38/0f3a prefixes can't. In i386.md 0f3[8a] is
;; still prefix_0f 1, with prefix_extra 1.
(define_attr "length_vex"
(if_then_else (and (eq_attr "prefix_0f" "1"
) (eq_attr "prefix_extra" "0"
) ) (if_then_else (eq_attr "prefix_vex_w" "1"
) (symbol_ref "ix86_attr_length_vex_default (insn, true, true)") (symbol_ref "ix86_attr_length_vex_default (insn, true, false)") ) (if_then_else (eq_attr "prefix_vex_w" "1"
) (symbol_ref "ix86_attr_length_vex_default (insn, false, true)") (symbol_ref "ix86_attr_length_vex_default (insn, false, false)") ) ) )
;; Set when modrm byte is used.
(define_attr "modrm"
(cond [ (eq_attr "type" "str,leave"
) (const_int 0) (eq_attr "unit" "i387"
) (const_int 0) (and (eq_attr "type" "incdec"
) (and (not (match_test "TARGET_64BIT") ) (ior (match_operand:SI 1 "register_operand" "") (match_operand:HI 1 "register_operand" "") ) ) ) (const_int 0) (and (eq_attr "type" "push"
) (not (match_operand 1 "memory_operand" "") ) ) (const_int 0) (and (eq_attr "type" "pop"
) (not (match_operand 0 "memory_operand" "") ) ) (const_int 0) (and (eq_attr "type" "imov"
) (and (not (eq_attr "mode" "DI"
) ) (ior (and (match_operand 0 "register_operand" "") (match_operand 1 "immediate_operand" "") ) (ior (and (match_operand 0 "ax_reg_operand" "") (match_operand 0 "memory_displacement_only_operand" "") ) (and (match_operand 1 "ax_reg_operand" "") (const_int 0) ) ) ) ) ) (eq_attr "type" "call"
) (and (match_operand 0 "constant_call_address_operand" "") (const_int 0) ) (eq_attr "type" "callv"
) (and (match_operand 1 "constant_call_address_operand" "") (const_int 0) ) (eq_attr "type" "alu,alu1,icmp,test"
) (match_operand 0 "ax_reg_operand" "") (symbol_ref "(get_attr_length_immediate (insn) <= (get_attr_mode (insn) != MODE_QI))") ](const_int 1) ) )
;; The (bounding maximum) length of an instruction in bytes.
;; ??? fistp and frndint are in fact fldcw/{fistp,frndint}/fldcw sequences.
;; Later we may want to split them and compute proper length as for
;; other insns.
(define_attr "length"
(cond [ (eq_attr "type" "other,multi,fistp,frndint"
) (const_int 16) (eq_attr "type" "fcmp"
) (const_int 4) (eq_attr "unit" "i387"
) (plus (const_int 2) (plus (attr "prefix_data16") (attr "length_address") ) ) (ior (eq_attr "prefix" "vex"
) (and (eq_attr "prefix" "maybe_vex"
) (match_test "TARGET_AVX") ) ) (plus (attr "length_vex") (plus (attr "length_immediate") (plus (attr "modrm") (attr "length_address") ) ) ) ](plus (plus (attr "modrm") (plus (attr "prefix_0f") (plus (attr "prefix_rex") (plus (attr "prefix_extra") (const_int 1) ) ) ) ) (plus (attr "prefix_rep") (plus (attr "prefix_data16") (plus (attr "length_immediate") (attr "length_address") ) ) ) ) ) )
;; The `memory' attribute is `none' if no memory is referenced, `load' or
;; `store' if there is a simple memory reference therein, or `unknown'
;; if the instruction is complex.
(define_attr "memory"
"none,load,store,both,unknown"
(cond [ (eq_attr "type" "other,multi,str,lwp"
) (const_string "unknown") (eq_attr "type" "lea,fcmov,fpspc"
) (const_string "none") (eq_attr "type" "fistp,leave"
) (const_string "both") (eq_attr "type" "frndint"
) (const_string "load") (eq_attr "type" "push"
) (if_then_else (match_operand 1 "memory_operand" "") (const_string "both") (const_string "store") ) (eq_attr "type" "pop"
) (if_then_else (match_operand 0 "memory_operand" "") (const_string "both") (const_string "load") ) (eq_attr "type" "setcc"
) (if_then_else (match_operand 0 "memory_operand" "") (const_string "store") (const_string "none") ) (eq_attr "type" "icmp,test,ssecmp,ssecomi,mmxcmp,fcmp"
) (if_then_else (ior (match_operand 0 "memory_operand" "") (match_operand 1 "memory_operand" "") ) (const_string "load") (const_string "none") ) (eq_attr "type" "ibr"
) (if_then_else (match_operand 0 "memory_operand" "") (const_string "load") (const_string "none") ) (eq_attr "type" "call"
) (if_then_else (match_operand 0 "constant_call_address_operand" "") (const_string "none") (const_string "load") ) (eq_attr "type" "callv"
) (if_then_else (match_operand 1 "constant_call_address_operand" "") (const_string "none") (const_string "load") ) (and (eq_attr "type" "alu1,negnot,ishift1,sselog1"
) (match_operand 1 "memory_operand" "") ) (match_operand 1 "memory_operand" "") (and (const_string "both") (match_operand 0 "memory_operand" "") ) (match_operand 1 "memory_operand" "") (const_string "both") (match_operand 0 "memory_operand" "") (const_string "store") (match_operand 1 "memory_operand" "") (and (const_string "load") (eq_attr "type" "!alu1,negnot,ishift1,imov,imovx,icmp,test,bitmanip,fmov,fcmp,fsgn,
sse,ssemov,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,sselog1,sseiadd1,
mmx,mmxmov,mmxcmp,mmxcvt"
) ) (match_operand 2 "memory_operand" "") (and (const_string "load") (eq_attr "type" "icmov,ssemuladd,sse4arg"
) ) (match_operand 3 "memory_operand" "") (const_string "load") ](const_string "none") ) )
;; Indicates if an instruction has both an immediate and a displacement.
(define_attr "imm_disp"
(cond [ (eq_attr "type" "other,multi"
) (const_string "unknown") (and (eq_attr "type" "icmp,test,imov,alu1,ishift1,rotate1"
) (and (match_operand 0 "memory_displacement_operand" "") (match_operand 1 "immediate_operand" "") ) ) (const_string "true") (and (eq_attr "type" "alu,ishift,ishiftx,rotate,rotatex,imul,idiv"
) (and (match_operand 0 "memory_displacement_operand" "") (match_operand 2 "immediate_operand" "") ) ) (const_string "true") ](const_string "false") ) )
;; Indicates if an FP operation has an integer source.
(define_attr "fp_int_src"
"false,true"
(const_string "false") )
;; Defines rounding mode of an FP operation.
(define_attr "i387_cw"
"trunc,floor,ceil,mask_pm,uninitialized,any"
(const_string "any") )
;; Define attribute to classify add/sub insns that consumes carry flag (CF)
(define_attr "use_carry"
"0,1"
(const_string "0") )
;; Define attribute to indicate unaligned ssemov insns
(define_attr "movu"
"0,1"
(const_string "0") )
;; Used to control the "enabled" attribute on a per-instruction basis.
(define_attr "isa"
"base,sse2,sse2_noavx,sse3,sse4,sse4_noavx,noavx,avx,bmi2,fma,fma4"
(const_string "base") )
;; Fma instruction selection has to be done based on
;; register pressure. For generating fma4, a cost model
;; based on register pressure is required. Till then,
;; fma4 instruction is disabled for targets that implement
;; both fma and fma4 instruction sets.
(define_attr "enabled"
(cond [ (eq_attr "isa" "sse2"
) (symbol_ref "TARGET_SSE2") (eq_attr "isa" "sse2_noavx"
) (symbol_ref "TARGET_SSE2 && !TARGET_AVX") (eq_attr "isa" "sse3"
) (symbol_ref "TARGET_SSE3") (eq_attr "isa" "sse4"
) (symbol_ref "TARGET_SSE4_1") (eq_attr "isa" "sse4_noavx"
) (symbol_ref "TARGET_SSE4_1 && !TARGET_AVX") (eq_attr "isa" "avx"
) (symbol_ref "TARGET_AVX") (eq_attr "isa" "noavx"
) (symbol_ref "!TARGET_AVX") (eq_attr "isa" "bmi2"
) (symbol_ref "TARGET_BMI2") (eq_attr "isa" "fma"
) (symbol_ref "TARGET_FMA") (eq_attr "isa" "fma4"
) (symbol_ref "TARGET_FMA4 && !TARGET_FMA") ](const_int 1) ) )
;; Describe a user's asm statement.
(define_asm_attributes [
( set_attr "length" "128")
( set_attr "type" "multi")
])
(define_code_iterator plusminus [
plus
minus
])
(define_code_iterator any_extend [
sign_extend
zero_extend
])
(define_code_iterator absneg [
abs
neg
])
(define_code_iterator any_or [
ior
xor
])
(define_code_iterator any_shiftrt [
lshiftrt
ashiftrt
])
(define_code_iterator any_rotate [
rotate
rotatert
])
(define_code_iterator smaxmin [
smax
smin
])
(define_expand "cbranch<mode>4"
[ (set (reg:CC FLAGS_REG) (compare:CC (match_operand:SDWIM 1 "nonimmediate_operand" "") (match_operand:SDWIM 2 "<general_operand>" "") ) ) (set (pc) (if_then_else (match_operator 0 "ordered_comparison_operator" [ (reg:CC FLAGS_REG) (const_int 0) ]) (label_ref (match_operand 3 "" "") ) (pc) ) ) ]
""
{
if (MEM_P (operands[1]) && MEM_P (operands[2]))
operands[1] = force_reg (<MODE>mode, operands[1]);
ix86_expand_branch (GET_CODE (operands[0]),
operands[1], operands[2], operands[3]);
DONE;
}
)
(define_expand "cstore<mode>4"
[ (set (reg:CC FLAGS_REG) (compare:CC (match_operand:SWIM 2 "nonimmediate_operand" "") (match_operand:SWIM 3 "<general_operand>" "") ) ) (set (match_operand:QI 0 "register_operand" "") (match_operator 1 "ordered_comparison_operator" [ (reg:CC FLAGS_REG) (const_int 0) ]) ) ]
""
{
if (MEM_P (operands[2]) && MEM_P (operands[3]))
operands[2] = force_reg (<MODE>mode, operands[2]);
ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
operands[2], operands[3]);
DONE;
}
)
(define_expand "cmp<mode>_1"
[(set (reg:CC FLAGS_REG) (compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "") (match_operand:SWI48 1 "<general_operand>" "") ) ) ]
)
(define_insn "*cmp<mode>_ccno_1"
[(set (reg FLAGS_REG) (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>,?m<r>") (match_operand:SWI 1 "const0_operand" "") ) ) ]
"ix86_match_ccmode (insn, CCNOmode)"
"@
test{<imodesuffix>}\t%0, %0
cmp{<imodesuffix>}\t{%1, %0|%0,%1}"
[(set_attr "type" "test,icmp")
(set_attr "length_immediate" "0,1")
(set_attr "mode" "<MODE>")]
)
(define_insn "*cmp<mode>_1"
[(set (reg FLAGS_REG) (compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>") (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m") ) ) ]
"ix86_match_ccmode (insn, CCmode)"
"cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "<MODE>")]
)
(define_insn "*cmp<mode>_minus_1"
[(set (reg FLAGS_REG) (compare (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>") (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m") ) (const_int 0) ) ) ]
"ix86_match_ccmode (insn, CCGOCmode)"
"cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
[(set_attr "type" "icmp")
(set_attr "mode" "<MODE>")]
)
(define_insn "*cmpqi_ext_1"
[(set (reg FLAGS_REG) (compare (match_operand:QI 0 "general_operand" "Qm") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) ) ) ]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%h1, %0|%0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")]
)
(define_insn "*cmpqi_ext_1_rex64"
[(set (reg FLAGS_REG) (compare (match_operand:QI 0 "register_operand" "Q") (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) ) ) ]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%h1, %0|%0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")]
)
(define_insn "*cmpqi_ext_2"
[(set (reg FLAGS_REG) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) (match_operand:QI 1 "const0_operand" "") ) ) ]
"ix86_match_ccmode (insn, CCNOmode)"
"test{b}\t%h0, %h0"
[(set_attr "type" "test")
(set_attr "length_immediate" "0")
(set_attr "mode" "QI")]
)
(define_expand "cmpqi_ext_3"
[(set (reg:CC FLAGS_REG) (compare:CC (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "") (const_int 8) (const_int 8) ) 0) (match_operand:QI 1 "immediate_operand" "") ) ) ]
)
(define_insn "*cmpqi_ext_3_insn"
[(set (reg FLAGS_REG) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) (match_operand:QI 1 "general_operand" "Qmn") ) ) ]
"!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "modrm" "1")
(set_attr "mode" "QI")]
)
(define_insn "*cmpqi_ext_3_insn_rex64"
[(set (reg FLAGS_REG) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) (match_operand:QI 1 "nonmemory_operand" "Qn") ) ) ]
"TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%1, %h0|%h0, %1}"
[(set_attr "type" "icmp")
(set_attr "modrm" "1")
(set_attr "mode" "QI")]
)
(define_insn "*cmpqi_ext_4"
[(set (reg FLAGS_REG) (compare (subreg:QI (zero_extract:SI (match_operand 0 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) (subreg:QI (zero_extract:SI (match_operand 1 "ext_register_operand" "Q") (const_int 8) (const_int 8) ) 0) ) ) ]
"ix86_match_ccmode (insn, CCmode)"
"cmp{b}\t{%h1, %h0|%h0, %h1}"
[(set_attr "type" "icmp")
(set_attr "mode" "QI")]
)
;; These implement float point compares.
;; %%% See if we can get away with VOIDmode operands on the actual insns,
;; which would allow mix and match FP modes on the compares. Which is what
;; the old patterns did, but with many more of them.
(define_expand "cbranchxf4"
[ (set (reg:CC FLAGS_REG) (compare:CC (match_operand:XF 1 "nonmemory_operand" "") (match_operand:XF 2 "nonmemory_operand" "") ) ) (set (pc) (if_then_else (match_operator 0 "ix86_fp_comparison_operator" [ (reg:CC FLAGS_REG) (const_int 0) ]) (label_ref (match_operand 3 "" "") ) (pc) ) ) ]
"TARGET_80387"
{
ix86_expand_branch (GET_CODE (operands[0]),
operands[1], operands[2], operands[3]);
DONE;
}
)
(define_expand "cstorexf4"
[ (set (reg:CC FLAGS_REG) (compare:CC (match_operand:XF 2 "nonmemory_operand" "") (match_operand:XF 3 "nonmemory_operand" "") ) ) (set (match_operand:QI 0 "register_operand" "") (match_operator 1 "ix86_fp_comparison_operator" [ (reg:CC FLAGS_REG) (const_int 0) ]) ) ]
"TARGET_80387"
{
ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
operands[2], operands[3]);
DONE;
}
)
;; Query #1
(define_expand "cbranch<mode>4"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:MODEF 1 "cmp_fp_expander_operand" "")
(match_operand:MODEF 2 "cmp_fp_expander_operand" "")))
(set (pc) (if_then_else
(match_operator 0 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)])
(label_ref (match_operand 3 "" ""))
(pc)))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
ix86_expand_branch (GET_CODE (operands[0]),
operands[1], operands[2], operands[3]);
DONE;
})
(define_expand "cstore<mode>4"
[(set (reg:CC FLAGS_REG)
(compare:CC (match_operand:MODEF 2 "cmp_fp_expander_operand" "")
(match_operand:MODEF 3 "cmp_fp_expander_operand" "")))
(set (match_operand:QI 0 "register_operand" "")
(match_operator 1 "ix86_fp_comparison_operator"
[(reg:CC FLAGS_REG)
(const_int 0)]))]
"TARGET_80387 || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
{
ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
operands[2], operands[3]);
DONE;
})
(define_expand "cbranchcc4"
[(set (pc) (if_then_else (match_operator 0 "comparison_operator" [ (match_operand 1 "flags_reg_operand" "") (match_operand 2 "const0_operand" "") ]) (label_ref (match_operand 3 "" "") ) (pc) ) ) ]
""
{
ix86_expand_branch (GET_CODE (operands[0]),
operands[1], operands[2], operands[3]);
DONE;
}
)
(define_expand "cstorecc4"
[(set (match_operand:QI 0 "register_operand" "") (match_operator 1 "comparison_operator" [ (match_operand 2 "flags_reg_operand" "") (match_operand 3 "const0_operand" "") ]) ) ]
""
{
ix86_expand_setcc (operands[0], GET_CODE (operands[1]),
operands[2], operands[3]);
DONE;
}
)
;; FP compares, step 1:
;; Set the FP condition codes.
;;
;; CCFPmode compare with exceptions
;; CCFPUmode compare with no exceptions
;; We may not use "#" to split and emit these, since the REG_DEAD notes
;; used to manage the reg stack popping would not be preserved.
(define_insn "*cmpfp_0"
[(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand 1 "register_operand" "f") (match_operand 2 "const0_operand" "") ) ] UNSPEC_FNSTSW) ) ]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"* return output_fp_compare (insn, operands, false, false);"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
(match_operand:DF 1 "" "")
(const_string "DF")
]
(const_string "XF")))]
)
(define_insn_and_split "*cmpfp_0_cc"
[ (set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 1 "register_operand" "f") (match_operand 2 "const0_operand" "") ) ) (clobber (match_operand:HI 0 "register_operand" "=a") ) ]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"#"
"&& reload_completed"
[ (set (match_dup 0) (unspec:HI [(compare:CCFP (match_dup 1) (match_dup 2) ) ] UNSPEC_FNSTSW) ) (set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 0) ] UNSPEC_SAHF) ) ]
""
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
(match_operand:DF 1 "" "")
(const_string "DF")
]
(const_string "XF")))]
)
(define_insn "*cmpfp_xf"
[(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand:XF 1 "register_operand" "f") (match_operand:XF 2 "register_operand" "f") ) ] UNSPEC_FNSTSW) ) ]
"TARGET_80387"
"* return output_fp_compare (insn, operands, false, false);"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "mode" "XF")]
)
(define_insn_and_split "*cmpfp_xf_cc"
[ (set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand:XF 1 "register_operand" "f") (match_operand:XF 2 "register_operand" "f") ) ) (clobber (match_operand:HI 0 "register_operand" "=a") ) ]
"TARGET_80387
&& TARGET_SAHF && !TARGET_CMOVE"
"#"
"&& reload_completed"
[ (set (match_dup 0) (unspec:HI [(compare:CCFP (match_dup 1) (match_dup 2) ) ] UNSPEC_FNSTSW) ) (set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 0) ] UNSPEC_SAHF) ) ]
""
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "mode" "XF")]
)
(define_insn "*cmpfp_<mode>"
[(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFP (match_operand:MODEF 1 "register_operand" "f") (match_operand:MODEF 2 "nonimmediate_operand" "fm") ) ] UNSPEC_FNSTSW) ) ]
"TARGET_80387"
"* return output_fp_compare (insn, operands, false, false);"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")]
)
(define_insn_and_split "*cmpfp_<mode>_cc"
[ (set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand:MODEF 1 "register_operand" "f") (match_operand:MODEF 2 "nonimmediate_operand" "fm") ) ) (clobber (match_operand:HI 0 "register_operand" "=a") ) ]
"TARGET_80387
&& TARGET_SAHF && !TARGET_CMOVE"
"#"
"&& reload_completed"
[ (set (match_dup 0) (unspec:HI [(compare:CCFP (match_dup 1) (match_dup 2) ) ] UNSPEC_FNSTSW) ) (set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 0) ] UNSPEC_SAHF) ) ]
""
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "mode" "<MODE>")]
)
(define_insn "*cmpfp_u"
[(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(compare:CCFPU (match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f") ) ] UNSPEC_FNSTSW) ) ]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"* return output_fp_compare (insn, operands, false, true);"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
(match_operand:DF 1 "" "")
(const_string "DF")
]
(const_string "XF")))]
)
(define_insn_and_split "*cmpfp_u_cc"
[ (set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 1 "register_operand" "f") (match_operand 2 "register_operand" "f") ) ) (clobber (match_operand:HI 0 "register_operand" "=a") ) ]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
&& GET_MODE (operands[1]) == GET_MODE (operands[2])"
"#"
"&& reload_completed"
[ (set (match_dup 0) (unspec:HI [(compare:CCFPU (match_dup 1) (match_dup 2) ) ] UNSPEC_FNSTSW) ) (set (reg:CC FLAGS_REG) (unspec:CC [(match_dup 0) ] UNSPEC_SAHF) ) ]
""
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
(match_operand:DF 1 "" "")
(const_string "DF")
]
(const_string "XF")))]
)
;; This pattern occurs twice.
(define_insn "*cmpfp_<mode>"
[(set (match_operand:HI 0 "register_operand" "=a")
(unspec:HI
[(compare:CCFP
(match_operand 1 "register_operand" "f")
(match_operator 3 "float_operator"
[(match_operand:SWI24 2 "memory_operand" "m")]))]
UNSPEC_FNSTSW))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"* return output_fp_compare (insn, operands, false, false);"
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "fp_int_src" "true")
(set_attr "mode" "<MODE>")])
;; This pattern appears twice.
(define_insn_and_split "*cmpfp_<mode>_cc"
[(set (reg:CCFP FLAGS_REG)
(compare:CCFP
(match_operand 1 "register_operand" "f")
(match_operator 3 "float_operator"
[(match_operand:SWI24 2 "memory_operand" "m")])))
(clobber (match_operand:HI 0 "register_operand" "=a"))]
"X87_FLOAT_MODE_P (GET_MODE (operands[1]))
&& TARGET_SAHF && !TARGET_CMOVE
&& (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
&& (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
"#"
"&& reload_completed"
[(set (match_dup 0)
(unspec:HI
[(compare:CCFP
(match_dup 1)
(match_op_dup 3 [(match_dup 2)]))]
UNSPEC_FNSTSW))
(set (reg:CC FLAGS_REG)
(unspec:CC [(match_dup 0)] UNSPEC_SAHF))]
""
[(set_attr "type" "multi")
(set_attr "unit" "i387")
(set_attr "fp_int_src" "true")
(set_attr "mode" "<MODE>")])
;; FP compares, step 2
;; Move the fpsw to ax.
(define_insn "x86_fnstsw_1"
[(set (match_operand:HI 0 "register_operand" "=a") (unspec:HI [(reg:CCFP FPSR_REG) ] UNSPEC_FNSTSW) ) ]
"TARGET_80387"
"fnstsw\t%0"
[(set (attr "length")
(symbol_ref "ix86_attr_length_address_default (insn) + 2"))
(set_attr "mode" "SI")
(set_attr "unit" "i387")]
)
;; FP compares, step 3
;; Get ax into flags, general case.
(define_insn "x86_sahf_1"
[(set (reg:CC FLAGS_REG) (unspec:CC [(match_operand:HI 0 "register_operand" "a") ] UNSPEC_SAHF) ) ]
"TARGET_SAHF"
{
#ifndef HAVE_AS_IX86_SAHF
if (TARGET_64BIT)
return ASM_BYTE "0x9e";
else
#endif
return "sahf";
}
[(set_attr "length" "1")
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "direct")
(set_attr "mode" "SI")]
)
;; Pentium Pro can do steps 1 through 3 in one go.
;; comi*, ucomi*, fcomi*, ficomi*, fucomi*
;; (these i387 instructions set flags directly)
(define_insn "*cmpfp_i_mixed"
[(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 0 "register_operand" "f,x") (match_operand 1 "nonimmediate_operand" "f,xm") ) ) ]
"TARGET_MIX_SSE_I387
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, true, false);"
[(set_attr "type" "fcmp,ssecomi")
(set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
(if_then_else (eq_attr "type" "ssecomi")
(const_string "0")
(const_string "*")))
(set (attr "prefix_data16")
(cond [(eq_attr "type" "fcmp")
(const_string "*")
(eq_attr "mode" "DF")
(const_string "1")
]
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")]
)
(define_insn "*cmpfp_i_sse"
[(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 0 "register_operand" "x") (match_operand 1 "nonimmediate_operand" "xm") ) ) ]
"TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, true, false);"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "DF")
(const_string "1")
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")]
)
(define_insn "*cmpfp_i_i387"
[(set (reg:CCFP FLAGS_REG) (compare:CCFP (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f") ) ) ]
"X87_FLOAT_MODE_P (GET_MODE (operands[0]))
&& TARGET_CMOVE
&& !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, true, false);"
[(set_attr "type" "fcmp")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
(match_operand:DF 1 "" "")
(const_string "DF")
]
(const_string "XF")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")]
)
(define_insn "*cmpfp_iu_mixed"
[(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 0 "register_operand" "f,x") (match_operand 1 "nonimmediate_operand" "f,xm") ) ) ]
"TARGET_MIX_SSE_I387
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, true, true);"
[(set_attr "type" "fcmp,ssecomi")
(set_attr "prefix" "orig,maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set (attr "prefix_rep")
(if_then_else (eq_attr "type" "ssecomi")
(const_string "0")
(const_string "*")))
(set (attr "prefix_data16")
(cond [(eq_attr "type" "fcmp")
(const_string "*")
(eq_attr "mode" "DF")
(const_string "1")
]
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")]
)
(define_insn "*cmpfp_iu_sse"
[(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 0 "register_operand" "x") (match_operand 1 "nonimmediate_operand" "xm") ) ) ]
"TARGET_SSE_MATH
&& SSE_FLOAT_MODE_P (GET_MODE (operands[0]))
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, true, true);"
[(set_attr "type" "ssecomi")
(set_attr "prefix" "maybe_vex")
(set (attr "mode")
(if_then_else (match_operand:SF 1 "" "")
(const_string "SF")
(const_string "DF")))
(set_attr "prefix_rep" "0")
(set (attr "prefix_data16")
(if_then_else (eq_attr "mode" "DF")
(const_string "1")
(const_string "0")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "double")]
)
(define_insn "*cmpfp_iu_387"
[(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (match_operand 0 "register_operand" "f") (match_operand 1 "register_operand" "f") ) ) ]
"X87_FLOAT_MODE_P (GET_MODE (operands[0]))
&& TARGET_CMOVE
&& !(SSE_FLOAT_MODE_P (GET_MODE (operands[0])) && TARGET_SSE_MATH)
&& GET_MODE (operands[0]) == GET_MODE (operands[1])"
"* return output_fp_compare (insn, operands, true, true);"
[(set_attr "type" "fcmp")
(set (attr "mode")
(cond [(match_operand:SF 1 "" "")
(const_string "SF")
(match_operand:DF 1 "" "")
(const_string "DF")
]
(const_string "XF")))
(set_attr "athlon_decode" "vector")
(set_attr "amdfam10_decode" "direct")
(set_attr "bdver1_decode" "direct")]
)