Terasic Intel Arria 10 SoC 4.1.22 ltsi armv7l

tinymembench v0.4.9 (simple benchmark for memory throughput and latency)

========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets ==

C copy backwards : 342.9 MB/s (1.1%) C copy backwards (32 byte blocks) : 358.6 MB/s (1.2%) C copy backwards (64 byte blocks) : 266.6 MB/s (1.4%) C copy : 463.5 MB/s (10.8%) C copy prefetched (32 bytes step) : 457.8 MB/s (1.6%) C copy prefetched (64 bytes step) : 443.5 MB/s (2.0%) C 2-pass copy : 347.9 MB/s (0.8%) C 2-pass copy prefetched (32 bytes step) : 382.9 MB/s (1.1%) C 2-pass copy prefetched (64 bytes step) : 398.6 MB/s (1.1%) C fill : 571.6 MB/s C fill (shuffle within 16 byte blocks) : 578.3 MB/s C fill (shuffle within 32 byte blocks) : 1916.2 MB/s (24.3%) C fill (shuffle within 64 byte blocks) : 598.8 MB/s (3.1%)

standard memcpy : 528.4 MB/s (0.7%) standard memset : 2886.9 MB/s (3.3%)

NEON read : 805.4 MB/s (1.7%) NEON read prefetched (32 bytes step) : 858.1 MB/s (1.1%) NEON read prefetched (64 bytes step) : 979.6 MB/s (1.4%) NEON read 2 data streams : 919.3 MB/s (0.7%) NEON read 2 data streams prefetched (32 bytes step) : 948.0 MB/s (1.2%) NEON read 2 data streams prefetched (64 bytes step) : 1078.1 MB/s (1.2%) NEON copy : 489.4 MB/s (6.0%) NEON copy prefetched (32 bytes step) : 463.7 MB/s (1.6%) NEON copy prefetched (64 bytes step) : 509.0 MB/s (4.4%) NEON unrolled copy : 408.7 MB/s (1.3%) NEON unrolled copy prefetched (32 bytes step) : 455.4 MB/s (1.6%) NEON unrolled copy prefetched (64 bytes step) : 464.6 MB/s (2.0%) NEON copy backwards : 351.1 MB/s (1.6%) NEON copy backwards prefetched (32 bytes step) : 401.0 MB/s (1.1%) NEON copy backwards prefetched (64 bytes step) : 352.7 MB/s (1.5%) NEON 2-pass copy : 428.0 MB/s (6.6%) NEON 2-pass copy prefetched (32 bytes step) : 392.4 MB/s (1.7%) NEON 2-pass copy prefetched (64 bytes step) : 412.5 MB/s (1.2%) NEON unrolled 2-pass copy : 357.1 MB/s (1.6%) NEON unrolled 2-pass copy prefetched (32 bytes step) : 435.8 MB/s (4.7%) NEON unrolled 2-pass copy prefetched (64 bytes step) : 404.8 MB/s (1.7%) NEON fill : 572.3 MB/s (0.6%) NEON fill backwards : 574.1 MB/s (0.3%) VFP copy : 433.7 MB/s (26.3%) VFP 2-pass copy : 363.4 MB/s (1.3%) ARM fill (STRD) : 572.2 MB/s (0.3%) ARM fill (STM with 8 registers) : 573.8 MB/s (0.5%) ARM fill (STM with 4 registers) : 1991.6 MB/s (22.3%) ARM copy prefetched (incr pld) : 455.5 MB/s (5.7%) ARM copy prefetched (wrap pld) : 448.7 MB/s (1.7%) ARM 2-pass copy prefetched (incr pld) : 385.7 MB/s (1.3%) ARM 2-pass copy prefetched (wrap pld) : 384.9 MB/s (0.8%)

========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. ==

block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 13.1 ns / 20.5 ns 131072 : 19.1 ns / 26.4 ns 262144 : 27.2 ns / 34.9 ns 524288 : 37.1 ns / 41.6 ns 1048576 : 117.5 ns / 173.3 ns 2097152 : 160.3 ns / 217.0 ns 4194304 : 189.0 ns / 243.2 ns 8388608 : 206.0 ns / 258.6 ns 16777216 : 220.1 ns / 276.1 ns 33554432 : 236.7 ns / 301.5 ns 67108864 : 256.0 ns / 340.8 ns