Merge pull request #2489 from fpistm/STM32CubeWBA_update

chore(wba): update to latest STM32CubeWBA v1.4.1
stm32duino · Aug 20, 2024 · c7175b3 · c7175b3
2 parents 6a03b54 + 91c9559
commit c7175b3
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diff --git a/cmake/boards_db.cmake b/cmake/boards_db.cmake
@@ -73174,6 +73174,170 @@ target_compile_options(GENERIC_G4A1VETX_xusb_HSFS INTERFACE
   "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
 )
 
+# GENERIC_H503CBTX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H503CBTX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503CB(T-U)")
+set(GENERIC_H503CBTX_MAXSIZE 131072)
+set(GENERIC_H503CBTX_MAXDATASIZE 32768)
+set(GENERIC_H503CBTX_MCU cortex-m33)
+set(GENERIC_H503CBTX_FPCONF "-")
+add_library(GENERIC_H503CBTX INTERFACE)
+target_compile_options(GENERIC_H503CBTX INTERFACE
+  "SHELL:-DSTM32H503xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H503CBTX_MCU}
+)
+target_compile_definitions(GENERIC_H503CBTX INTERFACE
+  "STM32H5xx"
+	"ARDUINO_GENERIC_H503CBTX"
+	"BOARD_NAME=\"GENERIC_H503CBTX\""
+	"BOARD_ID=GENERIC_H503CBTX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H503CBTX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+  ${GENERIC_H503CBTX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H503CBTX INTERFACE
+  "LINKER:--default-script=${GENERIC_H503CBTX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H503CBTX_MCU}
+)
+
+add_library(GENERIC_H503CBTX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H503CBTX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503CBTX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H503CBTX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H503CBTX_serial_none INTERFACE)
+target_compile_options(GENERIC_H503CBTX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H503CBTX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H503CBTX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H503CBTX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H503CBTX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H503CBTX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H503CBTX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H503CBTX_usb_none INTERFACE)
+target_compile_options(GENERIC_H503CBTX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503CBTX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H503CBTX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503CBTX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H503CBTX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H503CBTX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H503CBTX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
+# GENERIC_H503CBUX
+# -----------------------------------------------------------------------------
+
+set(GENERIC_H503CBUX_VARIANT_PATH "${CMAKE_CURRENT_LIST_DIR}/../variants/STM32H5xx/H503CB(T-U)")
+set(GENERIC_H503CBUX_MAXSIZE 131072)
+set(GENERIC_H503CBUX_MAXDATASIZE 32768)
+set(GENERIC_H503CBUX_MCU cortex-m33)
+set(GENERIC_H503CBUX_FPCONF "-")
+add_library(GENERIC_H503CBUX INTERFACE)
+target_compile_options(GENERIC_H503CBUX INTERFACE
+  "SHELL:-DSTM32H503xx  "
+  "SHELL:"
+  "SHELL:"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H503CBUX_MCU}
+)
+target_compile_definitions(GENERIC_H503CBUX INTERFACE
+  "STM32H5xx"
+	"ARDUINO_GENERIC_H503CBUX"
+	"BOARD_NAME=\"GENERIC_H503CBUX\""
+	"BOARD_ID=GENERIC_H503CBUX"
+	"VARIANT_H=\"variant_generic.h\""
+)
+target_include_directories(GENERIC_H503CBUX INTERFACE
+  ${CMAKE_CURRENT_LIST_DIR}/../system/STM32H5xx
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Inc
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/STM32H5xx_HAL_Driver/Src
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Include/
+  ${CMAKE_CURRENT_LIST_DIR}/../system/Drivers/CMSIS/Device/ST/STM32H5xx/Source/Templates/gcc/
+  ${GENERIC_H503CBUX_VARIANT_PATH}
+)
+
+target_link_options(GENERIC_H503CBUX INTERFACE
+  "LINKER:--default-script=${GENERIC_H503CBUX_VARIANT_PATH}/ldscript.ld"
+  "LINKER:--defsym=LD_FLASH_OFFSET=0x0"
+	"LINKER:--defsym=LD_MAX_SIZE=131072"
+	"LINKER:--defsym=LD_MAX_DATA_SIZE=32768"
+  "SHELL:-mfpu=fpv4-sp-d16 -mfloat-abi=hard"
+  -mcpu=${GENERIC_H503CBUX_MCU}
+)
+
+add_library(GENERIC_H503CBUX_serial_disabled INTERFACE)
+target_compile_options(GENERIC_H503CBUX_serial_disabled INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503CBUX_serial_generic INTERFACE)
+target_compile_options(GENERIC_H503CBUX_serial_generic INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED"
+)
+add_library(GENERIC_H503CBUX_serial_none INTERFACE)
+target_compile_options(GENERIC_H503CBUX_serial_none INTERFACE
+  "SHELL:-DHAL_UART_MODULE_ENABLED -DHWSERIAL_NONE"
+)
+add_library(GENERIC_H503CBUX_usb_CDC INTERFACE)
+target_compile_options(GENERIC_H503CBUX_usb_CDC INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC -DDISABLE_GENERIC_SERIALUSB"
+)
+add_library(GENERIC_H503CBUX_usb_CDCgen INTERFACE)
+target_compile_options(GENERIC_H503CBUX_usb_CDCgen INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_CDC"
+)
+add_library(GENERIC_H503CBUX_usb_HID INTERFACE)
+target_compile_options(GENERIC_H503CBUX_usb_HID INTERFACE
+  "SHELL:-DUSBCON  -DUSBD_VID=0x0483 -DUSBD_PID=0x5740 -DHAL_PCD_MODULE_ENABLED -DUSBD_USE_HID_COMPOSITE"
+)
+add_library(GENERIC_H503CBUX_usb_none INTERFACE)
+target_compile_options(GENERIC_H503CBUX_usb_none INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503CBUX_xusb_FS INTERFACE)
+target_compile_options(GENERIC_H503CBUX_xusb_FS INTERFACE
+  "SHELL:"
+)
+add_library(GENERIC_H503CBUX_xusb_HS INTERFACE)
+target_compile_options(GENERIC_H503CBUX_xusb_HS INTERFACE
+  "SHELL:-DUSE_USB_HS"
+)
+add_library(GENERIC_H503CBUX_xusb_HSFS INTERFACE)
+target_compile_options(GENERIC_H503CBUX_xusb_HSFS INTERFACE
+  "SHELL:-DUSE_USB_HS -DUSE_USB_HS_IN_FS"
+)
+
 # GENERIC_H503KBUX
 # -----------------------------------------------------------------------------
 

diff --git a/libraries/SrcWrapper/CMakeLists.txt b/libraries/SrcWrapper/CMakeLists.txt
@@ -114,6 +114,7 @@ add_library(SrcWrapper_bin OBJECT EXCLUDE_FROM_ALL
   src/HAL/stm32yyxx_hal_sd.c
   src/HAL/stm32yyxx_hal_sd_ex.c
   src/HAL/stm32yyxx_hal_sdadc.c
+  src/HAL/stm32yyxx_hal_sdio.c
   src/HAL/stm32yyxx_hal_sdram.c
   src/HAL/stm32yyxx_hal_smartcard.c
   src/HAL/stm32yyxx_hal_smartcard_ex.c

diff --git a/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h b/system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h
@@ -253,14 +253,14 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t IDCODE;      /*!< MCU device ID code,                 Address offset: 0x00 */
-  __IO uint32_t SCR;         /*!< Debug MCU status and configuration register,   Address offset: 0x04 */
-  __IO uint32_t APB1LFZR;    /*!< Debug MCU APB1 freeze register 1,   Address offset: 0x08 */
-  __IO uint32_t APB1HFZR;    /*!< Debug MCU APB1 freeze register 2,   Address offset: 0x0C */
-  __IO uint32_t APB2FZR;     /*!< Debug MCU APB2 freeze register,     Address offset: 0x10 */
-       uint32_t RESERVED1[4];/*!< Reserved,                                    0x14 - 0x20 */
-  __IO uint32_t APB7FZR;     /*!< Debug MCU APB7 freeze register,     Address offset: 0x24 */
-  __IO uint32_t AHB1FZR;     /*!< Debug MCU AHB1 freeze register,     Address offset: 0x28 */
+  __IO uint32_t IDCODE;          /*!< MCU device ID code,                             Address offset: 0x00 */
+  __IO uint32_t SCR;             /*!< Debug MCU status and configuration register,    Address offset: 0x04 */
+  __IO uint32_t APB1LFZR;        /*!< Debug MCU APB1 freeze register 1,               Address offset: 0x08 */
+  __IO uint32_t APB1HFZR;        /*!< Debug MCU APB1 freeze register 2,               Address offset: 0x0C */
+  __IO uint32_t APB2FZR;         /*!< Debug MCU APB2 freeze register,                 Address offset: 0x10 */
+       uint32_t RESERVED1[4];    /*!< Reserved,                                       Address offset: 0x14 - 0x20 */
+  __IO uint32_t APB7FZR;         /*!< Debug MCU APB7 freeze register,                 Address offset: 0x24 */
+  __IO uint32_t AHB1FZR;         /*!< Debug MCU AHB1 freeze register,                 Address offset: 0x28 */
 } DBGMCU_TypeDef;
 
 /**
@@ -617,11 +617,11 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t CR;    /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;    /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;    /*!< RNG data register,    Address offset: 0x08 */
+  __IO uint32_t CR;      /*!< RNG control register,                   Address offset: 0x00 */
+  __IO uint32_t SR;      /*!< RNG status register,                    Address offset: 0x04 */
+  __IO uint32_t DR;      /*!< RNG data register,                      Address offset: 0x08 */
   uint32_t RESERVED;
-  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */
+  __IO uint32_t HTCR;    /*!< RNG health test configuration register, Address offset: 0x10 */
 } RNG_TypeDef;
 
 /*
@@ -693,18 +693,18 @@ typedef struct
   */
 typedef struct
 {
-  __IO uint32_t SECCFGR;      /*!< SYSCFG secure configuration register,            Address offset: 0x00 */
-  __IO uint32_t CFGR1;        /*!< SYSCFG configuration register 1,                 Address offset: 0x04 */
-  __IO uint32_t FPUIMR;       /*!< SYSCFG FPU interrupt mask register,              Address offset: 0x08 */
-  __IO uint32_t CNSLCKR;      /*!< SYSCFG CPU non-secure lock register,             Address offset: 0x0C */
-  __IO uint32_t CSLCKR;       /*!< SYSCFG CPU secure lock register,                 Address offset: 0x10 */
-  __IO uint32_t CFGR2;        /*!< SYSCFG configuration register 2,                 Address offset: 0x14 */
-  __IO uint32_t MESR;         /*!< SYSCFG Memory Erase Status register,             Address offset: 0x18 */
-  __IO uint32_t CCCSR;        /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
-  __IO uint32_t CCVR;         /*!< SYSCFG Conpensaion Cell value register,          Address offset: 0x20 */
-  __IO uint32_t CCCR;         /*!< SYSCFG Conpensaion Cell Code register,           Address offset: 0x24 */
-       uint32_t RESERVED1;    /*!< RESERVED1,                                       Address offset: 0x28 */
-  __IO uint32_t RSSCMDR;      /*!< SYSCFG RSS command mode register,                Address offset: 0x2C */
+  __IO uint32_t SECCFGR;        /*!< SYSCFG secure configuration register,            Address offset: 0x00 */
+  __IO uint32_t CFGR1;          /*!< SYSCFG configuration register 1,                 Address offset: 0x04 */
+  __IO uint32_t FPUIMR;         /*!< SYSCFG FPU interrupt mask register,              Address offset: 0x08 */
+  __IO uint32_t CNSLCKR;        /*!< SYSCFG CPU non-secure lock register,             Address offset: 0x0C */
+  __IO uint32_t CSLCKR;         /*!< SYSCFG CPU secure lock register,                 Address offset: 0x10 */
+  __IO uint32_t CFGR2;          /*!< SYSCFG configuration register 2,                 Address offset: 0x14 */
+  __IO uint32_t MESR;           /*!< SYSCFG Memory Erase Status register,             Address offset: 0x18 */
+  __IO uint32_t CCCSR;          /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */
+  __IO uint32_t CCVR;           /*!< SYSCFG Conpensaion Cell value register,          Address offset: 0x20 */
+  __IO uint32_t CCCR;           /*!< SYSCFG Conpensaion Cell Code register,           Address offset: 0x24 */
+       uint32_t RESERVED1;      /*!< RESERVED1,                                       Address offset: 0x28 */
+  __IO uint32_t RSSCMDR;        /*!< SYSCFG RSS command mode register,                Address offset: 0x2C */
 } SYSCFG_TypeDef;
 
 /**
@@ -4256,7 +4256,7 @@ typedef struct
 #define I2C_CR1_ADDRACLR_Pos                (30U)
 #define I2C_CR1_ADDRACLR_Msk                (0x1UL << I2C_CR1_ADDRACLR_Pos)         /*!< 0x40000000 */
 #define I2C_CR1_ADDRACLR                    I2C_CR1_ADDRACLR_Msk                    /*!< ADDRACLR enable */
-#define I2C_CR1_STOPFACLR_Pos               (30U)
+#define I2C_CR1_STOPFACLR_Pos               (31U)
 #define I2C_CR1_STOPFACLR_Msk               (0x1UL << I2C_CR1_STOPFACLR_Pos)        /*!< 0x80000000 */
 #define I2C_CR1_STOPFACLR                   I2C_CR1_STOPFACLR_Msk                   /*!< STOPFACLR enable */
 
@@ -4942,7 +4942,6 @@ typedef struct
 #define LPTIM_CCR2_CCR2_Msk                 (0xFFFFUL << LPTIM_CCR2_CCR2_Pos)       /*!< 0x0000FFFF */
 #define LPTIM_CCR2_CCR2                     LPTIM_CCR2_CCR2_Msk                     /*!< Compare register 2 */
 
-
 /******************************************************************************/
 /*                                                                            */
 /*                       Public Key Accelerator (PKA)                         */
@@ -6669,6 +6668,9 @@ typedef struct
 #define RNG_HTCR_HTCFG_Pos                 (0U)
 #define RNG_HTCR_HTCFG_Msk                 (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos)     /*!< 0xFFFFFFFF */
 #define RNG_HTCR_HTCFG                     RNG_HTCR_HTCFG_Msk
+/********************  RNG Nist Compliance Values  *******************/
+#define RNG_CR_NIST_VALUE                   (0x00F02D00U)
+#define RNG_HTCR_NIST_VALUE                 (0xAAC7U)
 
 
 /******************************************************************************/
@@ -10293,7 +10295,8 @@ typedef struct
 
 /****************** TIM Instances : supporting OCxREF clear *******************/
 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1_NS)  || \
-                                                 ((INSTANCE) == TIM2_NS))
+                                                 ((INSTANCE) == TIM2_NS)  || \
+                                                 ((INSTANCE) == TIM16_NS))
 
 /********* TIM Instances : supporting bitfield OCCS in SMCR register **********/
 #define IS_TIM_OCCS_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1_NS)  || \