From 1ee3798406a9f50f05c94d311f3e96c19da9e077 Mon Sep 17 00:00:00 2001 From: stnolting <22944758+stnolting@users.noreply.github.com> Date: Thu, 18 May 2023 12:00:15 +0200 Subject: [PATCH] :rocket: preparing new release 1.8.5 --- CHANGELOG.md | 1 + docs/attrs.adoc | 2 +- rtl/core/neorv32_package.vhd | 2 +- sw/svd/neorv32.svd | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 7eaa3e8b1..56b9e2077 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -33,6 +33,7 @@ mimpid = 0x01080200 => Version 01.08.02.00 => v1.8.2 | Date (*dd.mm.yyyy*) | Version | Comment | |:-------------------:|:-------:|:--------| +| 18.05.2023 | [**:rocket:1.8.5**](https://github.com/stnolting/neorv32/releases/tag/v1.8.5) | **New release** | | 18.05.2023 | 1.8.4.9 | remove `is_simulation` flag from SYSINFO; add programmable interrupt to **TRNG** module; [#615](https://github.com/stnolting/neorv32/pull/615) | | 12.05.2023 | 1.8.4.8 | `mtval` CSR now provides the address of `ebreak` exceptions (re-added temporarily to pass RISC-V ISA tests); [#611](https://github.com/stnolting/neorv32/pull/611) | | 03.05.2023 | 1.8.4.7 | :bug: fix bug in FPU (terminate FPU sub-module operations if an exception has been raised); [#609](https://github.com/stnolting/neorv32/pull/609) | diff --git a/docs/attrs.adoc b/docs/attrs.adoc index ca0691c4c..a6f230221 100644 --- a/docs/attrs.adoc +++ b/docs/attrs.adoc @@ -1,7 +1,7 @@ :author: by Stephan Nolting (M.Sc.) :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. -:revnumber: v1.8.4 +:revnumber: v1.8.5 :doctype: book :sectnums: :stem: diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 4b0577c0e..31d5195db 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -60,7 +60,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080409"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01080500"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width, do not change! diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index 53901a719..41dcb2549 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.8.4 + 1.8.5 The NEORV32 RISC-V Processor