From da53729a9d48db78c387e30bdbbef95372a8b579 Mon Sep 17 00:00:00 2001
From: stnolting <22944758+stnolting@users.noreply.github.com>
Date: Sat, 4 Nov 2023 16:52:43 +0100
Subject: [PATCH] [docs] rework TRNG section

---
 docs/datasheet/soc_trng.adoc | 27 ++++++++++++++-------------
 1 file changed, 14 insertions(+), 13 deletions(-)

diff --git a/docs/datasheet/soc_trng.adoc b/docs/datasheet/soc_trng.adoc
index 822d7fb6e..2bd00a2b5 100644
--- a/docs/datasheet/soc_trng.adoc
+++ b/docs/datasheet/soc_trng.adoc
@@ -17,26 +17,27 @@
 
 **Overview**
 
-The NEORV32 true random number generator provides _physically_ true random numbers.
-Instead of using a pseudo RNG like a LFSR, the TRNG uses a simple, straight-forward ring
-oscillator concept as physical entropy source. Hence, voltage, thermal and also semiconductor manufacturing
-fluctuations are used to provide a true physical entropy source.
+The NEORV32 true random number generator provides _physically_ true random numbers. It is based on free-running
+ring-oscillators that generate **phase noise** when being sampled by a constant clock. This phase noise is
+used as physical entropy source. The TRNG features a platform independent architecture without FPGA-specific
+primitives, macros or attributes so it can be synthesized for _any_ FPGA. 
 
-The TRNG features a platform independent architecture without FPGA-specific primitives, macros or
-attributes so it can be synthesized for _any_ FPGA. It is based on the **neoTRNG V2**, which is a "spin-off project" of the
-NEORV32 processor. More detailed information about the neoTRNG, its architecture and a
-detailed evaluation of the random number quality can be found it the neoTRNG repository: https://github.com/stnolting/neoTRNG
+.In-Depth Documentation
+[TIP]
+For more information about the neoTRNG architecture and an analysis of its random quality check out the
+neoTRNG repository: https://github.com/stnolting/neoTRNG
 
 .Inferring Latches
 [NOTE]
-The synthesis tool might emit a warning like "inferring latches for ... neorv32_trng ...". This is no problem
-as this is what we actually want: the TRNG is based on latches, which implement the inverters of the ring oscillators.
+The synthesis tool might emit warnings regarding **inferred latches** or **combinatorial loops**. However, this
+is not design flaw as this is exactly what we want. ;)
 
 .Simulation
 [IMPORTANT]
-When simulating the processor the NEORV32 TRNG is automatically set to "simulation mode". In this mode, the physical entropy
-sources (= the ring oscillators) are replaced by a simple **pseudo RNG (LFSR)** providing weak pseudo-random data only.
-The `TRNG_CTRL_SIM_MODE` flag of the control register is set if simulation mode is active.
+When simulating the processor the TRNG is automatically set to "simulation mode". In this mode the physical entropy
+sources (the ring oscillators) are replaced by a simple **pseudo RNG** based on a LFSR providing only
+**deterministic pseudo-random** data. The `TRNG_CTRL_SIM_MODE` flag of the control register is set if simulation
+mode is active.
 
 
 **Theory of Operation**