From f5e4546a95f86d40153609cdedcf97a872c7ecbd Mon Sep 17 00:00:00 2001
From: stnolting <stnolting@gmail.com>
Date: Tue, 7 Jan 2025 17:23:08 +0100
Subject: [PATCH] [sw] minor edits and cleanups

---
 sw/example/processor_check/main.c | 4 ++--
 sw/lib/source/neorv32_aux.c       | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/sw/example/processor_check/main.c b/sw/example/processor_check/main.c
index cc3bc4c11..53d385c5e 100644
--- a/sw/example/processor_check/main.c
+++ b/sw/example/processor_check/main.c
@@ -2141,10 +2141,10 @@ int main() {
 
 
   // ----------------------------------------------------------
-  // Dual-core test
+  // SMP dual-core test
   // ----------------------------------------------------------
   neorv32_cpu_csr_write(CSR_MCAUSE, mcause_never_c);
-  PRINT_STANDARD("[%i] Dual-core ", cnt_test);
+  PRINT_STANDARD("[%i] SMP dual-core boot ", cnt_test);
 
   if ((NEORV32_SYSINFO->MISC[SYSINFO_MISC_HART] > 1) && // we need at least two cores
       (neorv32_clint_available() != 0)) { // we need the CLINT
diff --git a/sw/lib/source/neorv32_aux.c b/sw/lib/source/neorv32_aux.c
index c0ceda4c6..424230bd1 100644
--- a/sw/lib/source/neorv32_aux.c
+++ b/sw/lib/source/neorv32_aux.c
@@ -269,7 +269,7 @@ void neorv32_aux_print_hw_config(void) {
   if (neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_IS_SIM)) { neorv32_uart0_printf("yes\n"); }
   else { neorv32_uart0_printf("no\n"); }
 
-  neorv32_uart0_printf("CPU cores (harts):   %u\n", (uint32_t)NEORV32_SYSINFO->MISC[SYSINFO_MISC_HART]);
+  neorv32_uart0_printf("CPU cores (harts):   %u\n", neorv32_sysinfo_get_numcores());
 
   neorv32_uart0_printf("Clock speed:         %u Hz\n", neorv32_sysinfo_get_clk());
 
@@ -399,7 +399,7 @@ void neorv32_aux_print_hw_config(void) {
   }
 
   neorv32_uart0_printf("\nBoot configuration:  ");
-  int boot_config = (int)(NEORV32_SYSINFO->MISC[SYSINFO_MISC_BOOT]);
+  int boot_config = neorv32_sysinfo_get_bootmode();
   switch (boot_config) {
     case 0:  neorv32_uart0_printf("boot via bootloader (0)\n"); break;
     case 1:  neorv32_uart0_printf("boot from custom address (1)\n"); break;
@@ -410,7 +410,7 @@ void neorv32_aux_print_hw_config(void) {
   // internal IMEM
   neorv32_uart0_printf("Internal IMEM:       ");
   if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_INT_IMEM)) {
-    neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MISC[SYSINFO_MISC_IMEM]) & 0xFFFFFFFCUL);
+    neorv32_uart0_printf("%u bytes\n", neorv32_sysinfo_get_imemsize());
   }
   else {
     neorv32_uart0_printf("none\n");
@@ -419,7 +419,7 @@ void neorv32_aux_print_hw_config(void) {
   // internal DMEM
   neorv32_uart0_printf("Internal DMEM:       ");
   if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_INT_DMEM)) {
-    neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MISC[SYSINFO_MISC_DMEM]) & 0xFFFFFFFCUL);
+    neorv32_uart0_printf("%u bytes\n", neorv32_sysinfo_get_dmemsize());
   }
   else {
     neorv32_uart0_printf("none\n");