Introduce in UART register configured FIFO size

[akaeba]

Hi Stephan,

I plan to write an ISR driven UART TX driver. For this driver would be very helpfull to know the size of the implmented FIFO. Because then i can use following scheme:

1. ISR is triggered on FIFO empty
2. Fill in the FIFO size in chars

I see that there are only 3 bits free in the register. Therefore one question are the bits for FIFO Half (more/less) are really necessary? In relation to the transfer speed in the major cases is the ISR several times faster. Therefore i would recomend to free BIT 17, 20, 23, 26.

BR,
Andreas

[stnolting]

I see that there are only 3 bits free in the register. Therefore one question are the bits for FIFO Half (more/less) are really necessary? In relation to the transfer speed in the major cases is the ISR several times faster. Therefore i would recomend to free BIT 17, 20, 23, 26.

That is the problem - we were simply running out of space 😅

We could use some of the bits of the UART data register - just the lowest 8 bits are used right now.

However, if you just want to check for the TX FIFO depth you could also use a piece of software:

• set a minimal baudrate (clock prescaler = max, baud divisor = max)
• clear the TX FIFO by clearing the module's enable flag
• re-enable the module
• repeat and count: write any data value to the data FIFO until the TX FIFO's full flag is set

[akaeba]

We could use some of the bits of the UART data register - just the lowest 8 bits are used right now.

This i would appreciate the most :)

However, if you just want to check for the TX FIFO depth you could also use a piece of software:

this would lead to some test traffic on the uart. I ove more the approach with a second control register

neorv32/sw/lib/include/neorv32_uart.h

Line 52 in 88ef812

typedef volatile struct __attribute__((packed,aligned(4))) {

This could then changed to

typedef volatile struct __attribute__((packed,aligned(4))) {
  uint32_t CTRL;  /**< offset 0: control register (#NEORV32_UART_CTRL_enum) */
  uint8_t  DATA;  /**< offset 4: data register */
  uint8_t  CTRL2;  /**< offset 5: control */
  uint8_t  CTRL3;  /**< offset 6: control */
  uint8_t  CTRL4  /**< offset 7: control */
} neorv32_uart_t;

[stnolting]

This i would appreciate the most :)

Me too 👍

This could then changed to
uint8_t DATA; /**< offset 4: data register */

From a memory / address-space point of view DATA is a 32-bit register (even if just the lowest 8 bits are accessible right now). So I would recommend to keep the struct in it's current state and just add some bit defines for the (new) FIFO size bits in DATA.

[stnolting]

I made a PR (#581) that implements this. 😉

[akaeba]

Many Thanks. Great work!