clkgendcm_720p60hz2.v

// file: clkgendcm_720p60hz.v
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//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// 720p60hzclocksource
//
//----------------------------------------------------------------------------
// Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase
// Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)
//----------------------------------------------------------------------------
// CLK_OUT1    74.287      0.000       N/A      200.000        N/A
//
//----------------------------------------------------------------------------
// Input Clock   Input Freq (MHz)   Input Jitter (UI)
//----------------------------------------------------------------------------
// primary              26            0.010

`timescale 1ps/1ps

(* CORE_GENERATION_INFO = "clkgendcm_720p60hz,clk_wiz_v3_1,{component_name=clkgendcm_720p60hz,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_CLKGEN,num_out_clk=1,clkin1_period=38.461,clkin2_period=38.461,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=true}" *)
module clkgendcm_720p60hz
 (// Clock in ports
  input         CLK_IN1,
  // Clock out ports
  output        CLK_OUT1,
  // Status and control signals
  input         RESET,
  output        LOCKED
 );

  // Input buffering
  //------------------------------------
  assign clkin1 = CLK_IN1;


  // Clocking primitive
  //------------------------------------
  // Instantiation of the DCM primitive
  //    * Unused inputs are tied off
  //    * Unused outputs are labeled unused
  wire        psdone_unused;
  wire        locked_int;
  wire [2:1]  status_int;
  wire        clkfx;
  wire        clkfx180_unused;
  wire        clkfxdv_unused;

  DCM_CLKGEN
  #(.CLKFXDV_DIVIDE        (2),
    .CLKFX_DIVIDE          (7),
    .CLKFX_MULTIPLY        (20),
    .SPREAD_SPECTRUM       ("NONE"),
    .STARTUP_WAIT          ("FALSE"),
 //   .CLKIN_PERIOD          (38.461),
    .CLKFX_MD_MAX          (2.8571))
   dcm_clkgen_inst
    // Input clock
   (.CLKIN                 (clkin1),
    // Output clocks
    .CLKFX                 (clkfx),
    .CLKFX180              (clkfx180_unused),
    .CLKFXDV               (clkfxdv_unused),
    // Ports for dynamic reconfiguration
    .PROGCLK               (1'b0),
    .PROGDATA              (PROGDATA),
    .PROGEN                (PROGEN),
    .PROGDONE              (progdone_unused),
    // Other control and status signals
    .FREEZEDCM             (1'b0),
    .LOCKED                (locked_int),
    .STATUS                (status_int),
    .RST                   (RESET));

    assign LOCKED = locked_int;

  // Output buffering
  //-----------------------------------

  BUFG clkout1_buf
   (.O   (CLK_OUT1),
    .I   (clkfx));




endmodule