From c5751dcff2185a46a987542f59a6f73dfc9044ed Mon Sep 17 00:00:00 2001
From: Taiki Endo <te316e89@gmail.com>
Date: Wed, 8 Nov 2023 23:19:15 +0900
Subject: [PATCH] riscv: Add more comments

---
 src/imp/riscv.rs | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/imp/riscv.rs b/src/imp/riscv.rs
index eba0cc3d..e4e5d164 100644
--- a/src/imp/riscv.rs
+++ b/src/imp/riscv.rs
@@ -2,6 +2,11 @@
 
 // Atomic load/store implementation on RISC-V.
 //
+// This is for RISC-V targets without atomic CAS. (rustc doesn't provide atomics
+// at all on such targets. https://github.com/rust-lang/rust/pull/114499)
+//
+// Also, optionally provides RMW implementation when force-amo is enabled.
+//
 // Refs:
 // - RISC-V Instruction Set Manual Volume I: Unprivileged ISA
 //   https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf