diff --git a/cgra/CgraRTL.py b/cgra/CgraRTL.py index 6d79132..a0f909f 100644 --- a/cgra/CgraRTL.py +++ b/cgra/CgraRTL.py @@ -85,7 +85,7 @@ def construct(s, DataType, PredicateType, CtrlPktType, CtrlSignalType, multi_cgra_rows, multi_cgra_columns, controller_id, controller2addr_map, idTo2d_map) - s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 0) + s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 1) # Connections # Connects data memory with controller. diff --git a/cgra/CgraTemplateRTL.py b/cgra/CgraTemplateRTL.py index 851b1e5..d582bf3 100644 --- a/cgra/CgraTemplateRTL.py +++ b/cgra/CgraTemplateRTL.py @@ -24,7 +24,8 @@ class CgraTemplateRTL(Component): def construct(s, DataType, PredicateType, CtrlPktType, CtrlSignalType, - NocPktType, CmdType, ControllerIdType, controller_id, + NocPktType, CmdType, ControllerIdType, multi_cgra_rows, + multi_cgra_columns, controller_id, ctrl_mem_size, data_mem_size_global, data_mem_size_per_bank, num_banks_per_cgra, num_ctrl, total_steps, FunctionUnit, FuList, TileList, LinkList, @@ -77,8 +78,9 @@ def construct(s, DataType, PredicateType, CtrlPktType, CtrlSignalType, preload_data) s.controller = ControllerRTL(ControllerIdType, CmdType, CtrlPktType, NocPktType, DataType, DataAddrType, - controller_id, controller2addr_map) - s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 0) + multi_cgra_rows, multi_cgra_columns, + controller_id, controller2addr_map, idTo2d_map) + s.ctrl_ring = RingNetworkRTL(CtrlPktType, CtrlRingPos, s.num_tiles, 1) # Connections # Connects data memory with controller. diff --git a/cgra/test/CgraTemplateRTL_test.py b/cgra/test/CgraTemplateRTL_test.py index e82df43..43e584d 100644 --- a/cgra/test/CgraTemplateRTL_test.py +++ b/cgra/test/CgraTemplateRTL_test.py @@ -212,8 +212,8 @@ def test_cgra_universal(cmdline_opts, paramCGRA = None): idTo2d_map = { 0: [0, 0], 1: [1, 0], - 2: [0, 1], - 3: [1, 1], + 2: [2, 0], + 3: [3, 0], } CtrlPktType = \ diff --git a/controller/test/ControllerRTL_test.py b/controller/test/ControllerRTL_test.py index a1a6783..2942ab8 100644 --- a/controller/test/ControllerRTL_test.py +++ b/controller/test/ControllerRTL_test.py @@ -8,7 +8,6 @@ Date : Dec 15, 2024 ''' - from pymtl3 import * from pymtl3.stdlib.test_utils import TestVectorSimulator from ..ControllerRTL import ControllerRTL @@ -38,7 +37,8 @@ def construct(s, ControllerIdType, CtrlPktType, CmdType, MsgType, expected_to_tile_store_request_data_msgs, from_noc_pkts, expected_to_noc_pkts, - controller2addr_map): + controller2addr_map, + idTo2d_map, num_terminals): cmp_func = lambda a, b : a == b # a.data == b.data @@ -55,8 +55,12 @@ def construct(s, ControllerIdType, CtrlPktType, CmdType, MsgType, s.sink_to_noc_val_rdy = TestNetSinkRTL(PktType, expected_to_noc_pkts, cmp_fn = cmp_func) s.dut = ControllerRTL(ControllerIdType, CmdType, CtrlPktType, - PktType, MsgType, AddrType, controller_id, - controller2addr_map) + PktType, MsgType, AddrType, + # Number of controllers globally (x/y dimension). + 1, num_terminals, + controller_id, + controller2addr_map, + idTo2d_map) # Connections s.src_from_tile_load_request_pkt_en_rdy.send //= s.dut.recv_from_tile_load_request_pkt @@ -152,6 +156,13 @@ def mk_src_pkts(nterminals, lst): controller_id = 1 +idTo2d_map = { + 0: [0, 0], + 1: [1, 0], + 2: [2, 0], + 3: [3, 0] +} + controller2addr_map = { 0: [0, 3], 1: [4, 7], @@ -168,30 +179,30 @@ def mk_src_pkts(nterminals, lst): num_tile_inports, num_tile_outports) -Pkt = mk_ring_multi_cgra_pkt(nterminals, - addr_nbits = addr_nbits, - data_nbits = data_nbits, - predicate_nbits = predicate_nbits) +Pkt = mk_multi_cgra_noc_pkt(nterminals, 1, + addr_nbits = addr_nbits, + data_nbits = data_nbits, + predicate_nbits = predicate_nbits) from_tile_load_request_pkts = [ - # src dst opq vc cmd addr data predicate - Pkt(0, 0, 0, 0, CMD_LOAD_REQUEST, 1, 0, 1), - Pkt(0, 0, 0, 0, CMD_LOAD_REQUEST, 8, 0, 1), - Pkt(0, 0, 0, 0, CMD_LOAD_REQUEST, 13, 0, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_REQUEST, 1, 0, 1), + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_REQUEST, 8, 0, 1), + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_REQUEST, 13, 0, 1), ] from_tile_load_response_pkts = [ - # src dst opq vc cmd addr data predicate - Pkt(0, 0, 0, 0, CMD_LOAD_RESPONSE, 11, 11, 1), - Pkt(0, 0, 0, 0, CMD_LOAD_RESPONSE, 14, 14, 1), - Pkt(0, 0, 0, 0, CMD_LOAD_RESPONSE, 12, 12, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_RESPONSE, 11, 11, 1), + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_RESPONSE, 14, 14, 1), + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_RESPONSE, 12, 12, 1), ] from_tile_store_request_pkts = [ - # src dst opq vc cmd addr data predicate - Pkt(0, 0, 0, 0, CMD_STORE_REQUEST, 11, 110, 1), - Pkt(0, 0, 0, 0, CMD_STORE_REQUEST, 3, 300, 1), - Pkt(0, 0, 0, 0, CMD_STORE_REQUEST, 15, 150, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_STORE_REQUEST, 11, 110, 1), + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_STORE_REQUEST, 3, 300, 1), + Pkt(0, 0, 0, 0, 0, 0, 0, 0, CMD_STORE_REQUEST, 15, 150, 1), ] expected_to_tile_load_request_addr_msgs = [AddrType(2)] @@ -201,26 +212,26 @@ def mk_src_pkts(nterminals, lst): expected_to_tile_store_request_data_msgs = [DataType(50, 1)] from_noc_pkts = [ - # src dst opq vc cmd addr data predicate - Pkt(1, 0, 0, 0, CMD_LOAD_REQUEST, 2, 0, 1), - Pkt(2, 1, 0, 0, CMD_LOAD_RESPONSE, 8, 80, 1), - Pkt(0, 1, 0, 0, CMD_STORE_REQUEST, 5, 50, 1), - Pkt(0, 1, 0, 0, CMD_LOAD_RESPONSE, 9, 90, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + Pkt(1, 0, 1, 0, 0, 0, 0, 0, CMD_LOAD_REQUEST, 2, 0, 1), + Pkt(2, 1, 2, 0, 1, 0, 0, 0, CMD_LOAD_RESPONSE, 8, 80, 1), + Pkt(0, 1, 0, 0, 1, 0, 0, 0, CMD_STORE_REQUEST, 5, 50, 1), + Pkt(0, 1, 0, 0, 1, 0, 0, 0, CMD_LOAD_RESPONSE, 9, 90, 1), ] expected_to_noc_pkts = [ - # src dst opq vc cmd addr data predicate - Pkt(1, 0, 0, 0, CMD_LOAD_REQUEST, 1, 0, 1), - Pkt(1, 2, 0, 0, CMD_LOAD_RESPONSE, 11, 11, 1), - Pkt(1, 2, 0, 0, CMD_STORE_REQUEST, 11, 110, 1), - - Pkt(1, 2, 0, 0, CMD_LOAD_REQUEST, 8, 0, 1), - Pkt(1, 3, 0, 0, CMD_LOAD_RESPONSE, 14, 14, 1), - Pkt(1, 0, 0, 0, CMD_STORE_REQUEST, 3, 300, 1), - - Pkt(1, 3, 0, 0, CMD_LOAD_REQUEST, 13, 0, 1), - Pkt(1, 3, 0, 0, CMD_LOAD_RESPONSE, 12, 12, 1), - Pkt(1, 3, 0, 0, CMD_STORE_REQUEST, 15, 150, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + Pkt(1, 0, 1, 0, 0, 0, 0, 0, CMD_LOAD_REQUEST, 1, 0, 1), + Pkt(1, 2, 1, 0, 2, 0, 0, 0, CMD_LOAD_RESPONSE, 11, 11, 1), + Pkt(1, 2, 1, 0, 2, 0, 0, 0, CMD_STORE_REQUEST, 11, 110, 1), + + Pkt(1, 2, 1, 0, 2, 0, 0, 0, CMD_LOAD_REQUEST, 8, 0, 1), + Pkt(1, 3, 1, 0, 3, 0, 0, 0, CMD_LOAD_RESPONSE, 14, 14, 1), + Pkt(1, 0, 1, 0, 0, 0, 0, 0, CMD_STORE_REQUEST, 3, 300, 1), + + Pkt(1, 3, 1, 0, 3, 0, 0, 0, CMD_LOAD_REQUEST, 13, 0, 1), + Pkt(1, 3, 1, 0, 3, 0, 0, 0, CMD_LOAD_RESPONSE, 12, 12, 1), + Pkt(1, 3, 1, 0, 3, 0, 0, 0, CMD_STORE_REQUEST, 15, 150, 1), ] def test_simple(): @@ -240,6 +251,7 @@ def test_simple(): expected_to_tile_store_request_data_msgs, from_noc_pkts, expected_to_noc_pkts, - controller2addr_map) + controller2addr_map, idTo2d_map, + nterminals) run_sim(th) diff --git a/controller/test/TODO b/controller/test/TODO deleted file mode 100644 index 2a8d445..0000000 --- a/controller/test/TODO +++ /dev/null @@ -1,3 +0,0 @@ - - [ ] DataMemWithCrossbarRTL test with requests from NoC -> return correct response. - - [ ] E2e test with NoC. - - [ ] Translation. diff --git a/mem/data/test/DataMemWithCrossbarRTL_test.py b/mem/data/test/DataMemWithCrossbarRTL_test.py index 98f8889..057a54b 100644 --- a/mem/data/test/DataMemWithCrossbarRTL_test.py +++ b/mem/data/test/DataMemWithCrossbarRTL_test.py @@ -121,10 +121,10 @@ def test_const_queue(cmdline_opts): AddrType = mk_bits(addr_nbits) NocPktType = \ - mk_ring_multi_cgra_pkt(nterminals, - addr_nbits = addr_nbits, - data_nbits = data_nbits, - predicate_nbits = predicate_nbits) + mk_multi_cgra_noc_pkt(nterminals, 1, + addr_nbits = addr_nbits, + data_nbits = data_nbits, + predicate_nbits = predicate_nbits) test_meta_data = [ # addr: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 @@ -169,8 +169,8 @@ def test_const_queue(cmdline_opts): # Input data. # noc_send_read_addr = [AddrType(42)] send_to_noc_load_request_pkt = [ - # src dst opq vc cmd addr data predicate - NocPktType(0, 0, 0, 0, CMD_LOAD_REQUEST, 42, 0, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + NocPktType(0, 0, 0, 0, 0, 0, 0, 0, CMD_LOAD_REQUEST, 42, 0, 1), ] noc_recv_load_data = [DataType(0xbbbb, 1)] @@ -178,9 +178,9 @@ def test_const_queue(cmdline_opts): # noc_send_write_addr = [AddrType(40), AddrType(45)] # noc_send_write_data = [DataType(0xd040, 1), DataType(0xd545, 1)] send_to_noc_store_pkt = [ - # src dst opq vc cmd addr data predicate - NocPktType(0, 0, 0, 0, CMD_STORE_REQUEST, 40, 0xd040, 1), - NocPktType(0, 0, 0, 0, CMD_STORE_REQUEST, 45, 0xd545, 1), + # src dst src_x src_y dst_x dst_y opq vc cmd addr data predicate + NocPktType(0, 0, 0, 0, 0, 0, 0, 0, CMD_STORE_REQUEST, 40, 0xd040, 1), + NocPktType(0, 0, 0, 0, 0, 0, 0, 0, CMD_STORE_REQUEST, 45, 0xd545, 1), ] th = TestHarness(NocPktType, DataType, AddrType, data_mem_size_global,