From 418e75319ebf436e5a0987a38fab571b317cf17d Mon Sep 17 00:00:00 2001 From: tancheng Date: Fri, 3 Jan 2025 21:45:21 +0000 Subject: [PATCH] [test] Fix FP units rdy signals --- fu/flexible/translate/FlexibleFuRTL_test.py | 132 -------------------- fu/flexible/translate/__init__.py | 0 fu/float/FpAddRTL.py | 14 ++- fu/float/FpMulRTL.py | 22 ++-- fu/float/test/FpAddRTL_test.py | 96 +++++++------- fu/float/test/FpMulRTL_test.py | 103 +++++++-------- 6 files changed, 117 insertions(+), 250 deletions(-) delete mode 100644 fu/flexible/translate/FlexibleFuRTL_test.py delete mode 100644 fu/flexible/translate/__init__.py diff --git a/fu/flexible/translate/FlexibleFuRTL_test.py b/fu/flexible/translate/FlexibleFuRTL_test.py deleted file mode 100644 index 103223e..0000000 --- a/fu/flexible/translate/FlexibleFuRTL_test.py +++ /dev/null @@ -1,132 +0,0 @@ -""" -========================================================================== -FlexibleFuRTL_test.py -========================================================================== -Test cases for flexible functional unit. - -Author : Cheng Tan - Date : Dec 14, 2019 -""" - - -from pymtl3 import * -from pymtl3.stdlib.test_utils import run_sim, config_model_with_cmdline_opts -from ..FlexibleFuRTL import FlexibleFuRTL -from ...single.AdderRTL import AdderRTL -from ...single.BranchRTL import BranchRTL -from ...single.CompRTL import CompRTL -from ...single.LogicRTL import LogicRTL -from ...single.MemUnitRTL import MemUnitRTL -from ...single.MulRTL import MulRTL -from ...single.PhiRTL import PhiRTL -from ...single.SelRTL import SelRTL -from ...single.ShifterRTL import ShifterRTL -from ....lib.basic.en_rdy.test_sinks import TestSinkRTL -from ....lib.basic.en_rdy.test_srcs import TestSrcRTL -from ....lib.messages import * -from ....lib.opt_type import * - - -#------------------------------------------------------------------------- -# Test harness -#------------------------------------------------------------------------- - -class TestHarness( Component ): - - def construct( s, FunctionUnit, FuList, DataType, PredicateType, CtrlType, - data_mem_size, num_inports, num_outports, - src0_msgs, src1_msgs, src_predicate, ctrl_msgs, - sink0_msgs, sink1_msgs ): - - s.src_in0 = TestSrcRTL( DataType, src0_msgs ) - s.src_in1 = TestSrcRTL( DataType, src1_msgs ) - s.src_predicate = TestSrcRTL( PredicateType, src_predicate ) - s.src_const = TestSrcRTL( DataType, src1_msgs ) - s.src_opt = TestSrcRTL( CtrlType, ctrl_msgs ) - s.sink_out0 = TestSinkRTL( DataType, sink0_msgs ) - - s.dut = FunctionUnit( DataType, PredicateType, CtrlType, - num_inports, num_outports, data_mem_size, - FuList ) - - connect( s.src_const.send, s.dut.recv_const ) - connect( s.src_in0.send, s.dut.recv_in[0] ) - connect( s.src_in1.send, s.dut.recv_in[1] ) - connect( s.src_predicate.send, s.dut.recv_predicate ) - connect( s.src_opt.send, s.dut.recv_opt ) - connect( s.dut.send_out[0], s.sink_out0.recv ) - - AddrType = mk_bits( clog2( data_mem_size ) ) - s.to_mem_raddr = [ TestSinkRTL( AddrType, [] ) for _ in FuList ] - s.from_mem_rdata = [ TestSrcRTL( DataType, [] ) for _ in FuList ] - s.to_mem_waddr = [ TestSinkRTL( AddrType, [] ) for _ in FuList ] - s.to_mem_wdata = [ TestSinkRTL( DataType, [] ) for _ in FuList ] - - for i in range( len( FuList ) ): - s.to_mem_raddr[i].recv //= s.dut.to_mem_raddr[i] - s.from_mem_rdata[i].send //= s.dut.from_mem_rdata[i] - s.to_mem_waddr[i].recv //= s.dut.to_mem_waddr[i] - s.to_mem_wdata[i].recv //= s.dut.to_mem_wdata[i] - - def done( s ): - return s.src_in0.done() and s.src_in1.done() and\ - s.src_opt.done() and s.sink_out0.done() - - def line_trace( s ): - return s.dut.line_trace() - -# def run_sim( test_harness, max_cycles=100 ): -# test_harness.elaborate() -# test_harness.dut.verilog_translate_import = True -# test_harness.dut.config_verilog_import = VerilatorImportConfigs(vl_Wno_list = ['UNSIGNED', 'UNOPTFLAT', 'WIDTH', 'WIDTHCONCAT', 'ALWCOMBORDER']) -# test_harness = TranslationImportPass()(test_harness) -# test_harness.apply( DefaultPassGroup() ) -# test_harness.sim_reset() -# -# # Run simulation -# ncycles = 0 -# print() -# print( "{}:{}".format( ncycles, test_harness.line_trace() )) -# while not test_harness.done() and ncycles < max_cycles: -# test_harness.sim_tick() -# ncycles += 1 -# print( "{}:{}".format( ncycles, test_harness.line_trace() )) -# -# # Check timeout -# assert ncycles < max_cycles -# -# test_harness.sim_tick() -# test_harness.sim_tick() -# test_harness.sim_tick() - -import platform -import pytest - -# @pytest.mark.skipif('Linux' not in platform.platform(), -# reason="requires linux (gcc)") -def test_flexible_mul( cmdline_opts ): - FU = FlexibleFuRTL - FuList = [AdderRTL, MulRTL, LogicRTL, ShifterRTL, PhiRTL, CompRTL, BranchRTL, MemUnitRTL, SelRTL] - DataType = mk_data( 64, 1 ) - PredicateType = mk_predicate( 1, 1 ) - data_mem_size = 8 - num_inports = 4 - num_outports = 2 - CtrlType = mk_ctrl(num_inports) - FuInType = mk_bits( clog2( num_inports + 1 ) ) - pickRegister = [ FuInType( x+1 ) for x in range( num_inports ) ] - src_in0 = [ DataType(1, 1), DataType(2, 1), DataType(9, 1) ] - src_in1 = [ DataType(2, 1), DataType(3, 1), DataType(2, 1) ] - src_predicate = [ PredicateType(1, 1), PredicateType(1, 0), PredicateType(1, 1) ] - sink_out = [ DataType(2, 1), DataType(6, 1), DataType(18, 1) ] - src_opt = [ CtrlType( OPT_MUL, b1( 0 ), pickRegister ), - CtrlType( OPT_MUL, b1( 0 ), pickRegister ), - CtrlType( OPT_MUL, b1( 0 ), pickRegister ) ] - th = TestHarness( FU, FuList, DataType, PredicateType, CtrlType, - data_mem_size, num_inports, num_outports, - src_in0, src_in1, src_predicate, src_opt, - sink_out, sink_out ) - th = config_model_with_cmdline_opts( th, cmdline_opts, duts=['dut'] ) - th.apply( DefaultPassGroup(linetrace=True) ) - # run_sim( th ) - diff --git a/fu/flexible/translate/__init__.py b/fu/flexible/translate/__init__.py deleted file mode 100644 index e69de29..0000000 diff --git a/fu/float/FpAddRTL.py b/fu/float/FpAddRTL.py index 0ca51c8..ac58222 100644 --- a/fu/float/FpAddRTL.py +++ b/fu/float/FpAddRTL.py @@ -26,6 +26,7 @@ class FpAddRTL(Fu): def construct(s, DataType, PredicateType, CtrlType, num_inports, num_outports, data_mem_size, exp_nbits = 4, sig_nbits = 11): + super(FpAddRTL, s).construct(DataType, PredicateType, CtrlType, num_inports, num_outports, data_mem_size) @@ -36,6 +37,7 @@ def construct(s, DataType, PredicateType, CtrlType, num_entries = 2 FuInType = mk_bits(clog2(num_inports + 1)) CountType = mk_bits(clog2(num_entries + 1)) + # TODO: parameterize rounding mode s.rounding_mode = 0b000 s.FLOATING_ONE = concat( @@ -43,17 +45,17 @@ def construct(s, DataType, PredicateType, CtrlType, mk_bits(sig_nbits)() ) # Components - s.fadd = AddFN( exp_nbits+1, sig_nbits ) + s.fadd = AddFN(exp_nbits + 1, sig_nbits) s.fadd.roundingMode //= s.rounding_mode s.fadd.subOp //= lambda: s.recv_opt.msg.ctrl == OPT_FSUB # Wires - s.in0 = Wire( FuInType ) - s.in1 = Wire( FuInType ) + s.in0 = Wire(FuInType) + s.in1 = Wire(FuInType) - idx_nbits = clog2( num_inports ) - s.in0_idx = Wire( idx_nbits ) - s.in1_idx = Wire( idx_nbits ) + idx_nbits = clog2(num_inports) + s.in0_idx = Wire(idx_nbits) + s.in1_idx = Wire(idx_nbits) s.in0_idx //= s.in0[0:idx_nbits] s.in1_idx //= s.in1[0:idx_nbits] diff --git a/fu/float/FpMulRTL.py b/fu/float/FpMulRTL.py index 848e0f0..dd62a33 100644 --- a/fu/float/FpMulRTL.py +++ b/fu/float/FpMulRTL.py @@ -42,7 +42,7 @@ def construct(s, DataType, PredicateType, CtrlType, s.rounding_mode = 0b000 # Components - s.fmul = MulFN(exp_nbits+1, sig_nbits) + s.fmul = MulFN(exp_nbits + 1, sig_nbits) s.fmul.roundingMode //= s.rounding_mode # Wires @@ -61,29 +61,27 @@ def construct(s, DataType, PredicateType, CtrlType, @update def comb_logic(): + s.recv_all_val @= 0 # For pick input register s.in0 @= 0 s.in1 @= 0 - for i in range( num_inports ): + for i in range(num_inports): s.recv_in[i].rdy @= b1(0) - for i in range( num_outports ): - s.send_out[i].en @= s.recv_opt.en + for i in range(num_outports): + s.send_out[i].val @= 0 s.send_out[i].msg @= DataType() s.recv_const.rdy @= 0 s.recv_predicate.rdy @= b1(0) s.recv_opt.rdy @= 0 - if s.recv_opt.en: + if s.recv_opt.val & s.send_out[0].rdy: if s.recv_opt.msg.fu_in[0] != 0: s.in0 @= zext(s.recv_opt.msg.fu_in[0] - 1, FuInType) if s.recv_opt.msg.fu_in[1] != 0: s.in1 @= zext(s.recv_opt.msg.fu_in[1] - 1, FuInType) - s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ - s.recv_in[s.in1_idx].msg.predicate - if s.recv_opt.val: if s.recv_opt.msg.ctrl == OPT_FMUL: s.fmul.a @= s.recv_in[s.in0_idx].msg.payload @@ -105,16 +103,16 @@ def comb_logic(): s.send_out[0].msg.predicate @= s.recv_in[s.in0_idx].msg.predicate & \ (~s.recv_opt.msg.predicate | \ s.recv_predicate.msg.predicate) - s.recv_all_val @= s.recv_in[s.in0_idx].val & s.recv_in[s.in1_idx].val & \ + s.recv_all_val @= s.recv_in[s.in0_idx].val & \ ((s.recv_opt.msg.predicate == b1(0)) | s.recv_predicate.val) s.send_out[0].val @= s.recv_all_val s.recv_in[s.in0_idx].rdy @= s.recv_all_val & s.send_out[0].rdy - s.recv_in[s.in1_idx].rdy @= s.recv_all_val & s.send_out[0].rdy + s.recv_const.rdy @= s.recv_all_val & s.send_out[0].rdy s.recv_opt.rdy @= s.recv_all_val & s.send_out[0].rdy else: - for j in range( num_outports ): - s.send_out[j].val @= b1( 0 ) + for j in range(num_outports): + s.send_out[j].val @= b1(0) s.recv_opt.rdy @= 0 s.recv_in[s.in0_idx].rdy @= 0 s.recv_in[s.in1_idx].rdy @= 0 diff --git a/fu/float/test/FpAddRTL_test.py b/fu/float/test/FpAddRTL_test.py index 85b3a97..bc8f1ab 100644 --- a/fu/float/test/FpAddRTL_test.py +++ b/fu/float/test/FpAddRTL_test.py @@ -8,7 +8,6 @@ Date : Aug 8, 2023 """ - from pymtl3 import * from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) @@ -21,50 +20,49 @@ from ....lib.opt_type import * from ....mem.const.ConstQueueRTL import ConstQueueRTL - round_near_even = 0b000 -def test_elaborate( cmdline_opts ): - DataType = mk_data( 16, 1 ) - PredicateType = mk_predicate( 1, 1 ) +def test_elaborate(cmdline_opts): + DataType = mk_data(16, 1) + PredType = mk_predicate(1, 1) ConfigType = mk_ctrl() data_mem_size = 8 num_inports = 2 num_outports = 1 - FuInType = mk_bits( clog2( num_inports + 1 ) ) - pickRegister = [ FuInType( x+1 ) for x in range( num_inports ) ] - src_in0 = [ DataType(1, 1), DataType(7, 1), DataType(4, 1) ] - src_in1 = [ DataType(2, 1), DataType(3, 1), DataType(1, 1) ] - src_predicate = [ PredicateType(1, 0), PredicateType(1, 0), PredicateType(1, 1) ] - src_const = [ DataType(5, 1), DataType(0, 0), DataType(7, 1) ] + FuInType = mk_bits(clog2(num_inports + 1)) + pick_register = [ FuInType(x + 1) for x in range(num_inports) ] + src_in0 = [ DataType(1, 1), DataType(7, 1), DataType(4, 1) ] + src_in1 = [ DataType(3, 1), ] + src_predicate = [ PredType(1, 0), PredType(1, 0), PredType(1, 1) ] + src_const = [ DataType(5, 1), DataType(7, 1) ] sink_out = [ DataType(6, 0), DataType(4, 0), DataType(11, 1) ] - src_opt = [ ConfigType( OPT_ADD_CONST, b1( 1 ), pickRegister ), - ConfigType( OPT_SUB, b1( 1 ), pickRegister ), - ConfigType( OPT_ADD_CONST, b1( 1 ), pickRegister ) ] - dut = FpAddRTL( DataType, PredicateType, ConfigType, num_inports, - num_outports, data_mem_size, exp_nbits = 4, sig_nbits = 11 ) - dut = config_model_with_cmdline_opts( dut, cmdline_opts, duts=[] ) + src_opt = [ ConfigType( OPT_ADD_CONST, b1(1), pick_register ), + ConfigType( OPT_SUB, b1(1), pick_register ), + ConfigType( OPT_ADD_CONST, b1(1), pick_register ) ] + dut = FpAddRTL(DataType, PredType, ConfigType, num_inports, + num_outports, data_mem_size, exp_nbits = 4, sig_nbits = 11) + dut = config_model_with_cmdline_opts(dut, cmdline_opts, duts = []) #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- -class TestHarness( Component ): +class TestHarness(Component): - def construct( s, FunctionUnit, DataType, PredicateType, ConfigType, + def construct(s, FunctionUnit, DataType, PredType, ConfigType, num_inports, num_outports, data_mem_size, src0_msgs, src1_msgs, src_predicate, src_const, - ctrl_msgs, sink_msgs ): + ctrl_msgs, sink_msgs): - s.src_in0 = TestSrcRTL( DataType, src0_msgs ) - s.src_in1 = TestSrcRTL( DataType, src1_msgs ) - s.src_predicate = TestSrcRTL( PredicateType, src_predicate ) - s.src_opt = TestSrcRTL( ConfigType, ctrl_msgs ) - s.sink_out = TestSinkRTL( DataType, sink_msgs ) + s.src_in0 = TestSrcRTL ( DataType, src0_msgs ) + s.src_in1 = TestSrcRTL ( DataType, src1_msgs ) + s.src_predicate = TestSrcRTL ( PredType, src_predicate ) + s.src_opt = TestSrcRTL ( ConfigType, ctrl_msgs ) + s.sink_out = TestSinkRTL( DataType, sink_msgs ) - s.const_queue = ConstQueueRTL( DataType, src_const ) - s.dut = FunctionUnit( DataType, PredicateType, ConfigType, - num_inports, num_outports, data_mem_size ) + s.const_queue = ConstQueueRTL(DataType, src_const) + s.dut = FunctionUnit(DataType, PredType, ConfigType, + num_inports, num_outports, data_mem_size) connect( s.src_in0.send, s.dut.recv_in[0] ) connect( s.src_in1.send, s.dut.recv_in[1] ) @@ -73,43 +71,43 @@ def construct( s, FunctionUnit, DataType, PredicateType, ConfigType, connect( s.src_opt.send, s.dut.recv_opt ) connect( s.dut.send_out[0], s.sink_out.recv ) - def done( s ): + def done(s): return s.src_in0.done() and s.src_in1.done() and \ s.src_opt.done() and s.sink_out.done() - def line_trace( s ): + def line_trace(s): return s.dut.line_trace() -def mk_float_to_bits_fn( DataType, exp_nbits = 4, sig_nbits = 11 ): +def mk_float_to_bits_fn(DataType, exp_nbits = 4, sig_nbits = 11): return lambda f_value, predicate: ( - DataType( floatToFN( f_value, - precision = 1 + exp_nbits + sig_nbits ), - predicate ) ) + DataType(floatToFN(f_value, + precision = 1 + exp_nbits + sig_nbits), + predicate)) def test_add_basic(): FU = FpAddRTL exp_nbits = 4 sig_nbits = 11 - DataType = mk_data( 1 + exp_nbits + sig_nbits, 1 ) - f2b = mk_float_to_bits_fn( DataType, exp_nbits, sig_nbits ) - PredicateType = mk_predicate( 1, 1 ) + DataType = mk_data(1 + exp_nbits + sig_nbits, 1) + f2b = mk_float_to_bits_fn(DataType, exp_nbits, sig_nbits) + PredType = mk_predicate(1, 1) ConfigType = mk_ctrl() data_mem_size = 8 num_inports = 2 num_outports = 1 - FuInType = mk_bits( clog2( num_inports + 1 ) ) - pickRegister = [ FuInType( x+1 ) for x in range( num_inports ) ] - src_in0 = [ f2b(1.1, 1), f2b(7.7, 1), f2b(4.4, 1) ] - src_in1 = [ f2b(2.2, 1), f2b(3.3, 1), f2b(1.1, 1) ] - src_predicate = [ PredicateType(1, 0), PredicateType(1, 0), PredicateType(1, 1) ] - src_const = [ f2b(5.5, 1), f2b(0, 0), f2b(7.7, 1) ] - sink_out = [ f2b(6.602, 0), f2b(4.4, 0), f2b(12.1, 1) ] # 6.6 -> 6.602 - src_opt = [ ConfigType( OPT_FADD_CONST, b1( 1 ), pickRegister ), - ConfigType( OPT_FSUB, b1( 1 ), pickRegister ), - ConfigType( OPT_FADD_CONST, b1( 1 ), pickRegister ) ] - th = TestHarness( FU, DataType, PredicateType, ConfigType, + FuInType = mk_bits(clog2(num_inports + 1)) + pick_register = [ FuInType(x + 1) for x in range(num_inports) ] + src_predicate = [ PredType(1, 0), PredType(1, 0), PredType(1, 1) ] + src_in0 = [ f2b(1.1, 1), f2b(7.7, 1), f2b(4.4, 1) ] + src_in1 = [ f2b(3.3, 1), ] + src_const = [ f2b(5.5, 1), f2b(7.7, 1) ] + sink_out = [ f2b(6.602, 0), f2b(4.4, 0), f2b(12.1, 1) ] # 6.6 -> 6.602 + src_opt = [ ConfigType( OPT_FADD_CONST, b1(1), pick_register ), + ConfigType( OPT_FSUB, b1(1), pick_register ), + ConfigType( OPT_FADD_CONST, b1(1), pick_register ) ] + th = TestHarness( FU, DataType, PredType, ConfigType, num_inports, num_outports, data_mem_size, src_in0, src_in1, src_predicate, src_const, src_opt, sink_out ) - run_sim( th ) + run_sim(th) diff --git a/fu/float/test/FpMulRTL_test.py b/fu/float/test/FpMulRTL_test.py index e4af298..095e2fe 100644 --- a/fu/float/test/FpMulRTL_test.py +++ b/fu/float/test/FpMulRTL_test.py @@ -14,55 +14,56 @@ from ..FpMulRTL import FpMulRTL from ...pymtl3_hardfloat.HardFloat.converter_funcs import (floatToFN, fNToFloat) -from ....lib.basic.en_rdy.test_sinks import TestSinkRTL -from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.basic.val_rdy.SinkRTL import SinkRTL as TestSinkRTL +from ....lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL from ....lib.messages import * from ....lib.opt_type import * from ....mem.const.ConstQueueRTL import ConstQueueRTL round_near_even = 0b000 -def test_elaborate( cmdline_opts ): - DataType = mk_data( 16, 1 ) - PredicateType = mk_predicate( 1, 1 ) +def test_elaborate(cmdline_opts): + DataType = mk_data(16, 1) + PredType = mk_predicate(1, 1) ConfigType = mk_ctrl() data_mem_size = 8 num_inports = 2 num_outports = 1 - FuInType = mk_bits( clog2( num_inports + 1 ) ) - pickRegister = [ FuInType( x+1 ) for x in range( num_inports ) ] - src_in0 = [ DataType(2, 1), DataType(7, 1), DataType(4, 1) ] - src_in1 = [ DataType(1, 1), DataType(3, 1), DataType(1, 1) ] - src_predicate = [ PredicateType(1, 0), PredicateType(1, 0), PredicateType(1, 1) ] - src_const = [ DataType(5, 1), DataType(0, 0), DataType(7, 1) ] + FuInType = mk_bits(clog2(num_inports + 1)) + pick_register = [ FuInType(x + 1) for x in range(num_inports) ] + src_in0 = [ DataType(2, 1), DataType(7, 1), DataType(4, 1) ] + src_in1 = [ DataType(3, 1) ] + src_predicate = [ PredType(1, 0), PredType(1, 0), PredType(1, 1) ] + src_const = [ DataType(5, 1), DataType(7, 1) ] sink_out = [ DataType(10, 0), DataType(21, 0), DataType(28, 1) ] - src_opt = [ ConfigType( OPT_MUL_CONST, b1( 1 ), pickRegister ), - ConfigType( OPT_MUL, b1( 1 ), pickRegister ), - ConfigType( OPT_MUL_CONST, b1( 1 ), pickRegister ) ] - dut = FpMulRTL( DataType, PredicateType, ConfigType, num_inports, - num_outports, data_mem_size, exp_nbits=4, sig_nbits=11 ) - dut = config_model_with_cmdline_opts( dut, cmdline_opts, duts=[] ) + src_opt = [ ConfigType( OPT_MUL_CONST, b1(1), pick_register ), + ConfigType( OPT_MUL, b1(1), pick_register ), + ConfigType( OPT_MUL_CONST, b1(1), pick_register ) ] + dut = FpMulRTL(DataType, PredType, ConfigType, num_inports, + num_outports, data_mem_size, exp_nbits = 4, + sig_nbits = 11) + dut = config_model_with_cmdline_opts(dut, cmdline_opts, duts = []) #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- -class TestHarness( Component ): +class TestHarness(Component): - def construct( s, FunctionUnit, DataType, PredicateType, ConfigType, - num_inports, num_outports, data_mem_size, - src0_msgs, src1_msgs, src_predicate, src_const, - ctrl_msgs, sink_msgs ): + def construct(s, FunctionUnit, DataType, PredType, ConfigType, + num_inports, num_outports, data_mem_size, + src0_msgs, src1_msgs, src_predicate, src_const, + ctrl_msgs, sink_msgs): - s.src_in0 = TestSrcRTL( DataType, src0_msgs ) - s.src_in1 = TestSrcRTL( DataType, src1_msgs ) - s.src_predicate = TestSrcRTL( PredicateType, src_predicate ) - s.src_opt = TestSrcRTL( ConfigType, ctrl_msgs ) - s.sink_out = TestSinkRTL( DataType, sink_msgs ) + s.src_in0 = TestSrcRTL ( DataType, src0_msgs ) + s.src_in1 = TestSrcRTL ( DataType, src1_msgs ) + s.src_predicate = TestSrcRTL ( PredType, src_predicate ) + s.src_opt = TestSrcRTL ( ConfigType, ctrl_msgs ) + s.sink_out = TestSinkRTL( DataType, sink_msgs ) - s.const_queue = ConstQueueRTL( DataType, src_const ) - s.dut = FunctionUnit( DataType, PredicateType, ConfigType, - num_inports, num_outports, data_mem_size ) + s.const_queue = ConstQueueRTL(DataType, src_const) + s.dut = FunctionUnit(DataType, PredType, ConfigType, + num_inports, num_outports, data_mem_size) connect( s.src_in0.send, s.dut.recv_in[0] ) connect( s.src_in1.send, s.dut.recv_in[1] ) @@ -78,36 +79,36 @@ def done(s): def line_trace(s): return s.dut.line_trace() -def mk_float_to_bits_fn( DataType, exp_nbits = 4, sig_nbits = 11 ): +def mk_float_to_bits_fn(DataType, exp_nbits = 4, sig_nbits = 11): return lambda f_value, predicate: ( - DataType( floatToFN( f_value, - precision = 1 + exp_nbits + sig_nbits ), - predicate ) ) + DataType(floatToFN(f_value, + precision = 1 + exp_nbits + sig_nbits), + predicate)) def test_mul(): FU = FpMulRTL exp_nbits = 4 sig_nbits = 11 - DataType = mk_data( 1 + exp_nbits + sig_nbits, 1 ) - f2b = mk_float_to_bits_fn( DataType, exp_nbits, sig_nbits ) - PredicateType = mk_predicate( 1, 1 ) + DataType = mk_data(1 + exp_nbits + sig_nbits, 1) + f2b = mk_float_to_bits_fn(DataType, exp_nbits, sig_nbits) + PredType = mk_predicate(1, 1) ConfigType = mk_ctrl() data_mem_size = 8 num_inports = 2 num_outports = 1 - FuInType = mk_bits( clog2( num_inports + 1 ) ) - pickRegister = [ FuInType( x+1 ) for x in range( num_inports ) ] - src_in0 = [ f2b(2.2, 1), f2b(7.7, 1), f2b(4.4, 1) ] - src_in1 = [ f2b(1.1, 1), f2b(3.3, 1), f2b(1.1, 1) ] - src_predicate = [ PredicateType(1, 0), PredicateType(1, 0), PredicateType(1, 1) ] - src_const = [ f2b(5.5, 1), f2b(0, 0), f2b(7.7, 1) ] + FuInType = mk_bits(clog2(num_inports + 1)) + pick_register = [ FuInType(x + 1) for x in range(num_inports) ] + src_predicate = [ PredType(1, 0), PredType(1, 0), PredType(1, 1) ] + src_in0 = [ f2b(2.2, 1), f2b(7.7, 1), f2b(4.4, 1) ] + src_in1 = [ f2b(3.3, 1) ] + src_const = [ f2b(5.5, 1), f2b(7.7, 1) ] sink_out = [ f2b(12.1, 0), f2b(25.4, 0), f2b(33.88, 1) ] # 25.41 -> 25.4 - src_opt = [ ConfigType( OPT_FMUL_CONST, b1( 1 ), pickRegister ), - ConfigType( OPT_FMUL, b1( 1 ), pickRegister ), - ConfigType( OPT_FMUL_CONST, b1( 1 ), pickRegister ) ] - th = TestHarness( FU, DataType, PredicateType, ConfigType, - num_inports, num_outports, data_mem_size, - src_in0, src_in1, src_predicate, src_const, src_opt, - sink_out ) - run_sim( th ) + src_opt = [ ConfigType( OPT_FMUL_CONST, b1(1), pick_register ), + ConfigType( OPT_FMUL, b1(1), pick_register ), + ConfigType( OPT_FMUL_CONST, b1(1), pick_register ) ] + th = TestHarness(FU, DataType, PredType, ConfigType, + num_inports, num_outports, data_mem_size, + src_in0, src_in1, src_predicate, src_const, src_opt, + sink_out) + run_sim(th)