diff --git a/cgra/CGRAWithControllerRTL.py b/cgra/CGRAWithControllerRTL.py deleted file mode 100644 index 1695993..0000000 --- a/cgra/CGRAWithControllerRTL.py +++ /dev/null @@ -1,130 +0,0 @@ -""" -========================================================================= -CGRAWithControllerRTL.py -========================================================================= - -Author : Cheng Tan - Date : Dec 4, 2024 -""" - -from pymtl3 import * -from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.AdderRTL import AdderRTL -from ..lib.util.common import * -from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL -from ..lib.basic.val_rdy.ifcs import ValRdySendIfcRTL -from ..lib.basic.val_rdy.ifcs import ValRdyRecvIfcRTL -from ..lib.opt_type import * -from ..mem.data.DataMemScalableRTL import DataMemScalableRTL -from ..noc.ChannelNormalRTL import ChannelNormalRTL -from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL -from ..tile.TileSeparateCrossbarRTL import TileSeparateCrossbarRTL -from ..controller.ControllerRTL import ControllerRTL - - -class CGRAWithControllerRTL(Component): - - def construct(s, DataType, PredicateType, CtrlType, NocPktType, - width, height, ctrl_mem_size, data_mem_size, num_ctrl, - total_steps, FunctionUnit, FuList, preload_data = None, - preload_const = None): - - s.num_tiles = width * height - s.num_mesh_ports = 4 - AddrType = mk_bits(clog2(ctrl_mem_size)) - - # Interfaces - s.recv_waddr = [RecvIfcRTL(AddrType) for _ in range(s.num_tiles)] - s.recv_wopt = [RecvIfcRTL(CtrlType) for _ in range(s.num_tiles)] - - # Explicitly provides the ValRdyRecvIfcRTL in the library, as the - # translation pass sometimes not able to distinguish the - # EnRdyRecvIfcRTL from it. - s.recv_from_other = ValRdyRecvIfcRTL(NocPktType) - s.send_to_other = ValRdySendIfcRTL(NocPktType) - - # s.recv_towards_controller = RecvIfcRTL(DataType) - # s.send_from_controller = SendIfcRTL(DataType) - - - # Components - if preload_const == None: - preload_const = [[DataType(0, 0)] for _ in range(width*height)] - s.tile = [TileSeparateCrossbarRTL(DataType, PredicateType, CtrlType, - ctrl_mem_size, data_mem_size, num_ctrl, - total_steps, 4, 2, s.num_mesh_ports, - s.num_mesh_ports, const_list = preload_const[i]) - for i in range( s.num_tiles)] - s.data_mem = DataMemScalableRTL(DataType, data_mem_size, height, height, preload_data) - s.controller = ControllerRTL(NocPktType, DataType, AddrType) - - # Connections - - # Connects data memory with controller. - s.data_mem.recv_from_noc //= s.controller.send_to_master - s.data_mem.send_to_noc //= s.controller.recv_from_master - - s.recv_from_other //= s.controller.recv_from_other - s.send_to_other //= s.controller.send_to_other - - # s.recv_towards_controller //= s.controller.recv_from_master - # s.send_from_controller //= s.controller.send_to_master - - for i in range(s.num_tiles): - s.recv_waddr[i] //= s.tile[i].recv_waddr - s.recv_wopt[i] //= s.tile[i].recv_wopt - - if i // width > 0: - s.tile[i].send_data[PORT_SOUTH] //= s.tile[i-width].recv_data[PORT_NORTH] - - if i // width < height - 1: - s.tile[i].send_data[PORT_NORTH] //= s.tile[i+width].recv_data[PORT_SOUTH] - - if i % width > 0: - s.tile[i].send_data[PORT_WEST] //= s.tile[i-1].recv_data[PORT_EAST] - - if i % width < width - 1: - s.tile[i].send_data[PORT_EAST] //= s.tile[i+1].recv_data[PORT_WEST] - - if i // width == 0: - s.tile[i].send_data[PORT_SOUTH].rdy //= 0 - s.tile[i].recv_data[PORT_SOUTH].en //= 0 - s.tile[i].recv_data[PORT_SOUTH].msg //= DataType(0, 0) - - if i // width == height - 1: - s.tile[i].send_data[PORT_NORTH].rdy //= 0 - s.tile[i].recv_data[PORT_NORTH].en //= 0 - s.tile[i].recv_data[PORT_NORTH].msg //= DataType(0, 0) - - if i % width == 0: - s.tile[i].send_data[PORT_WEST].rdy //= 0 - s.tile[i].recv_data[PORT_WEST].en //= 0 - s.tile[i].recv_data[PORT_WEST].msg //= DataType(0, 0) - - if i % width == width - 1: - s.tile[i].send_data[PORT_EAST].rdy //= 0 - s.tile[i].recv_data[PORT_EAST].en //= 0 - s.tile[i].recv_data[PORT_EAST].msg //= DataType(0, 0) - - if i % width == 0: - s.tile[i].to_mem_raddr //= s.data_mem.recv_raddr[i//width] - s.tile[i].from_mem_rdata //= s.data_mem.send_rdata[i//width] - s.tile[i].to_mem_waddr //= s.data_mem.recv_waddr[i//width] - s.tile[i].to_mem_wdata //= s.data_mem.recv_wdata[i//width] - else: - s.tile[i].to_mem_raddr.rdy //= 0 - s.tile[i].from_mem_rdata.en //= 0 - s.tile[i].from_mem_rdata.msg //= DataType(0, 0) - s.tile[i].to_mem_waddr.rdy //= 0 - s.tile[i].to_mem_wdata.rdy //= 0 - - - # Line trace - def line_trace( s ): - # str = "||".join([ x.element.line_trace() for x in s.tile ]) - # str += " :: [" + s.data_mem.line_trace() + "]" - res = "||\n".join([ (("[tile"+str(i)+"]: ") + x.line_trace() + x.ctrl_mem.line_trace()) - for (i,x) in enumerate(s.tile) ]) - res += "\n :: [" + s.data_mem.line_trace() + "] \n" - return res diff --git a/cgra/test/CGRAWithControllerRTL_test.py b/cgra/test/CGRAWithControllerRTL_test.py deleted file mode 100644 index 945c012..0000000 --- a/cgra/test/CGRAWithControllerRTL_test.py +++ /dev/null @@ -1,158 +0,0 @@ -""" -========================================================================== -CGRAWithControllerRTL_test.py -========================================================================== -Test cases for CGRA with controller. - -Author : Cheng Tan - Date : Dec 4, 2024 -""" - - -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) -from pymtl3.passes.backends.verilog import (VerilogTranslationPass, - VerilogVerilatorImportPass) -from ..CGRAWithControllerRTL import CGRAWithControllerRTL -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...lib.messages import * -from ...lib.opt_type import * -from ...lib.basic.en_rdy.test_srcs import TestSrcRTL - - -#------------------------------------------------------------------------- -# Test harness -#------------------------------------------------------------------------- - -class TestHarness(Component): - - def construct(s, DUT, FunctionUnit, FuList, DataType, PredicateType, - CtrlType, NocPktType, width, height, ctrl_mem_size, - data_mem_size, src_opt, ctrl_waddr): - - s.num_tiles = width * height - AddrType = mk_bits(clog2(ctrl_mem_size)) - - s.src_opt = [TestSrcRTL(CtrlType, src_opt[i]) - for i in range(s.num_tiles)] - s.ctrl_waddr = [TestSrcRTL(AddrType, ctrl_waddr[i]) - for i in range(s.num_tiles)] - - s.dut = DUT(DataType, PredicateType, CtrlType, NocPktType, - width, height, ctrl_mem_size, data_mem_size, - len(src_opt[0]), len(src_opt[0]), FunctionUnit, FuList) - - # Connections - s.dut.send_to_other.rdy //= 0 - s.dut.recv_from_other.val //= 0 - s.dut.recv_from_other.msg //= NocPktType(0, 0, 0, 0, 0, 0) - - for i in range(s.num_tiles): - connect(s.src_opt[i].send, s.dut.recv_wopt[i]) - connect(s.ctrl_waddr[i].send, s.dut.recv_waddr[i]) - - def done(s): - done = True - for i in range(s.num_tiles): - if not s.src_opt[i].done(): - done = False - break - return done - - def line_trace(s): - return s.dut.line_trace() - -def test_homo_2x2(cmdline_opts): - num_tile_inports = 4 - num_tile_outports = 4 - num_fu_inports = 4 - num_fu_outports = 2 - num_routing_outports = num_tile_outports + num_fu_inports - ctrl_mem_size = 6 - data_mem_size = 8 - width = 2 - height = 2 - TileInType = mk_bits(clog2(num_tile_inports + 1)) - FuInType = mk_bits(clog2(num_fu_inports + 1)) - FuOutType = mk_bits(clog2(num_fu_outports + 1)) - addr_nbits = clog2(ctrl_mem_size) - AddrType = mk_bits(addr_nbits) - num_tiles = width * height - DUT = CGRAWithControllerRTL - FunctionUnit = FlexibleFuRTL - FuList = [MemUnitRTL, AdderRTL] - DataType = mk_data(32, 1) - PredicateType = mk_predicate(1, 1) - CtrlType = mk_separate_ctrl(num_fu_inports, num_fu_outports, - num_tile_inports, num_tile_outports) - NocPktType = mk_ring_multi_cgra_pkt(nrouters = 4, - addr_nbits = addr_nbits, - data_nbits = 32, - predicate_nbits = 1) - pickRegister = [FuInType(x + 1) for x in range(num_fu_inports)] - src_opt = [[ - CtrlType(OPT_INC, b1(0), - pickRegister, - [TileInType(4), TileInType(3), TileInType(2), TileInType(1), - # TODO: make below as TileInType(5) to double check. - TileInType(0), TileInType(0), TileInType(0), TileInType(0)], - - [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), - FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]), - CtrlType(OPT_INC, b1(0), - pickRegister, - [TileInType(4), TileInType(3), TileInType(2), TileInType(1), - TileInType(0), TileInType(0), TileInType(0), TileInType(0)], - - [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), - FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]), - - CtrlType(OPT_ADD, b1(0), - pickRegister, - [TileInType(4), TileInType(3), TileInType(2), TileInType(1), - TileInType(0), TileInType(0), TileInType(0), TileInType(0)], - - [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), - FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]), - - CtrlType(OPT_STR, b1(0), - pickRegister, - [TileInType(4), TileInType(3), TileInType(2), TileInType(1), - TileInType(0), TileInType(0), TileInType(0), TileInType(0)], - - [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), - FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]), - - CtrlType(OPT_ADD, b1(0), - pickRegister, - [TileInType(4), TileInType(3), TileInType(2), TileInType(1), - TileInType(0), TileInType(0), TileInType(0), TileInType(0)], - - [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), - FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]), - - CtrlType(OPT_ADD, b1(0), - pickRegister, - [TileInType(4), TileInType(3), TileInType(2), TileInType(1), - TileInType(0), TileInType(0), TileInType(0), TileInType(0)], - - [FuOutType(0), FuOutType(0), FuOutType(0), FuOutType(0), - FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]) - - ] for _ in range(num_tiles)] - ctrl_waddr = [[AddrType(0), AddrType(1), AddrType(2), AddrType(3), - AddrType(4), AddrType(5)] for _ in range(num_tiles)] - th = TestHarness(DUT, FunctionUnit, FuList, DataType, PredicateType, - CtrlType, NocPktType, width, height, ctrl_mem_size, - data_mem_size, src_opt, ctrl_waddr) - th.elaborate() - th.dut.set_metadata(VerilogVerilatorImportPass.vl_Wno_list, - ['UNSIGNED', 'UNOPTFLAT', 'WIDTH', 'WIDTHCONCAT', - 'ALWCOMBORDER']) - th = config_model_with_cmdline_opts(th, cmdline_opts, duts=['dut']) - run_sim(th) - diff --git a/controller/ControllerRTL.py b/controller/ControllerRTL.py index e88eea8..27edf76 100644 --- a/controller/ControllerRTL.py +++ b/controller/ControllerRTL.py @@ -8,7 +8,6 @@ Date : Dec 2, 2024 """ - from pymtl3 import * from pymtl3.stdlib.primitive import RegisterFile from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL @@ -19,7 +18,6 @@ from ..lib.cmd_type import * from ..lib.opt_type import * - class ControllerRTL(Component): def construct(s, ControllerIdType, CmdType, NocPktType, @@ -77,6 +75,23 @@ def construct(s, ControllerIdType, CmdType, NocPktType, # s.send_cmd = [SendIfcRTL(b2) for _ in range(s.num_tiles)] + # LUT for global data address mapping. + addr_offset_nbits = 0 + s.addr2controller_lut = [Wire(ControllerIdType) for _ in range(len(controller2addr_map))] + # Assumes the address range is contiguous within one CGRA's SPMs. + addr2controller_vector = [-1 for _ in range(len(controller2addr_map))] + s.addr_base_items = len(controller2addr_map) + for src_controller_id, address_range in controller2addr_map.items(): + begin_addr, end_addr = address_range[0], address_range[1] + address_length = end_addr - begin_addr + 1 + assert (address_length & (address_length - 1)) == 0, f"{adderss_length} is not a power of 2." + addr_offset_nbits = clog2(address_length) + addr_base = begin_addr >> addr_offset_nbits + assert addr2controller_vector[addr_base] == -1, f"address range [{begin_addr}, {end_addr}] overlaps with others." + addr2controller_vector[addr_base] = ControllerIdType(src_controller_id) + + s.addr2controller_lut[addr_base] //= ControllerIdType(src_controller_id) + # Connections # Requests towards others, 1 cycle delay to improve timing. s.recv_from_master_load_request_pkt_queue.recv //= s.recv_from_master_load_request_pkt @@ -89,18 +104,8 @@ def construct(s, ControllerIdType, CmdType, NocPktType, s.send_to_master_store_request_addr_queue.send //= s.send_to_master_store_request_addr s.send_to_master_store_request_data_queue.send //= s.send_to_master_store_request_data - - # FIXME: Probably not translatable. - def getDstId(target_address): - for src_controller_id, address_range in controller2addr_map.items(): - if target_address >= address_range[0] and target_address <= address_range[1]: - return src_controller_id - assert(False) - - @update def update_received_msg(): - kLoadRequestInportIdx = 0 kLoadResponseInportIdx = 1 kStoreRequestInportIdx = 2 @@ -180,7 +185,7 @@ def update_received_msg(): s.send_to_master_store_request_addr_queue.recv.msg @= \ CGRAAddrType(received_pkt.addr) s.send_to_master_store_request_data_queue.recv.msg @= \ - CGRADataType(received_pkt.data, received_pkt.predicate) + CGRADataType(received_pkt.data, received_pkt.predicate, 0, 0) s.send_to_master_store_request_addr_queue.recv.en @= 1 s.send_to_master_store_request_data_queue.recv.en @= 1 @@ -188,19 +193,19 @@ def update_received_msg(): if s.send_to_master_load_response_data_queue.recv.rdy: s.recv_from_noc.rdy @= 1 s.send_to_master_load_response_data_queue.recv.msg @= \ - CGRADataType(received_pkt.data, received_pkt.predicate) + CGRADataType(received_pkt.data, received_pkt.predicate, 0, 0) s.send_to_master_load_response_data_queue.recv.en @= 1 - else: - # TODO: Handle other cmd types. - assert(False) + # else: + # # TODO: Handle other cmd types. + # assert(False) @update def update_sending_to_noc_msg(): s.send_to_noc.val @= s.crossbar.send[0].val s.crossbar.send[0].rdy @= s.send_to_noc.rdy - addr_dst_id = getDstId(s.crossbar.send[0].msg.addr) + addr_dst_id = s.addr2controller_lut[trunc(s.crossbar.send[0].msg.addr >> addr_offset_nbits, ControllerIdType)] s.send_to_noc.msg @= \ NocPktType(s.crossbar.send[0].msg.src, addr_dst_id, diff --git a/mem/data/DataMemWithCrossbarRTL.py b/mem/data/DataMemWithCrossbarRTL.py index 12de1fa..724d5e7 100644 --- a/mem/data/DataMemWithCrossbarRTL.py +++ b/mem/data/DataMemWithCrossbarRTL.py @@ -56,6 +56,7 @@ def construct(s, NocPktType, DataType, LocalBankIndexType = mk_bits(clog2(num_banks)) s.num_rd_tiles = num_rd_tiles s.num_wr_tiles = num_wr_tiles + RdTileIdType = mk_bits(clog2(num_rd_tiles)) num_xbar_in_rd_ports = num_rd_tiles + 1 num_xbar_in_wr_ports = num_wr_tiles + 1 num_xbar_out_rd_ports = num_banks + 1 @@ -117,16 +118,19 @@ def construct(s, NocPktType, DataType, s.send_to_noc_load_pending = Wire(b1) if preload_data_per_bank != None: + preload_data_per_bank_size = data_mem_size_per_bank s.preload_data_per_bank = [[Wire(DataType) for _ in range(data_mem_size_per_bank)] for _ in range(num_banks)] for b in range(num_banks): for i in range(len(preload_data_per_bank[b])): s.preload_data_per_bank[b][i] //= preload_data_per_bank[b][i] else: - s.preload_data_per_bank = [[Wire(DataType) for _ in range(1)] + preload_data_per_bank_size = 1 + s.preload_data_per_bank = [[Wire(DataType) for _ in range(preload_data_per_bank_size)] for _ in range(num_banks)] for b in range(num_banks): s.preload_data_per_bank[b][0] //= DataType() + PreloadDataPerBankSizeType = mk_bits(max(1, clog2(preload_data_per_bank_size))) @update @@ -151,7 +155,7 @@ def assemble_xbar_pkt(): # Connects xbar with the sram. @update - def update_read_without_init(): + def update_all(): # Initializes the signals. for i in range(num_xbar_in_rd_ports): @@ -170,7 +174,7 @@ def update_read_without_init(): if s.init_mem_done == b1(0): for b in range(num_banks): s.reg_file[b].waddr[0] @= trunc(s.init_mem_addr, PerBankAddrType) - s.reg_file[b].wdata[0] @= s.preload_data_per_bank[b][s.init_mem_addr] + s.reg_file[b].wdata[0] @= s.preload_data_per_bank[b][trunc(s.init_mem_addr, PreloadDataPerBankSizeType)] s.reg_file[b].wen[0] @= b1(1) else: @@ -201,8 +205,11 @@ def update_read_without_init(): if (s.read_crossbar.send[arbitrated_rd_msg.dst].msg.src == i) & (arbitrated_rd_msg.dst < num_banks): loaded_msg = s.reg_file[trunc(arbitrated_rd_msg.dst, LocalBankIndexType)].rdata[0] if i <= s.num_rd_tiles: - s.send_rdata[i].msg @= loaded_msg # s.reg_file[trunc(arbitrated_rd_msg.dst, LocalBankIndexType)].rdata[0] - s.send_rdata[i].en @= s.read_crossbar.send[arbitrated_rd_msg.dst].val + index = RdTileIdType(i) + # s.send_rdata[trunc(i, RdTileIdType)].msg @= loaded_msg + # s.send_rdata[trunc(i, RdTileIdType)].en @= s.read_crossbar.send[arbitrated_rd_msg.dst].val + s.send_rdata[index].msg @= loaded_msg + s.send_rdata[index].en @= s.read_crossbar.send[arbitrated_rd_msg.dst].val # TODO: Check the translated Verilog to make sure the loop is flattened correctly with special out (NocPktType) towards NoC. else: assembled_noc_load_response_pkt_msg = \ @@ -220,10 +227,10 @@ def update_read_without_init(): # Request from NoC would never target a remote access, i.e., as long # as the request can come from the NoC, it meant to access this local # SRAM, which should be guarded by the controller and NoC routers. - assert(i < num_banks) - s.send_rdata[i].msg @= s.recv_from_noc_rdata.msg + # assert(i < num_banks) + s.send_rdata[trunc(i, RdTileIdType)].msg @= s.recv_from_noc_rdata.msg # TODO: https://github.com/tancheng/VectorCGRA/issues/26 -- Modify this part for non-blocking access. - s.send_rdata[i].en @= s.read_crossbar.send[arbitrated_rd_msg.dst].val & \ + s.send_rdata[trunc(i, RdTileIdType)].en @= s.read_crossbar.send[arbitrated_rd_msg.dst].val & \ s.recv_from_noc_rdata.en # FIXME: The msg would come back one by one in order, so no # need to check the src_tile, which can be improved. diff --git a/scale_out/translate/RingMultiCGRARTL_test.py b/scale_out/translate/RingMultiCGRARTL_test.py index ce1c24a..a73a2b9 100644 --- a/scale_out/translate/RingMultiCGRARTL_test.py +++ b/scale_out/translate/RingMultiCGRARTL_test.py @@ -31,23 +31,27 @@ class TestHarness(Component): def construct(s, DUT, FunctionUnit, FuList, DataType, PredicateType, - CtrlType, NocPktType, num_terminals, width, height, - ctrl_mem_size, data_mem_size, src_opt, ctrl_waddr): + CtrlType, NocPktType, CmdType, num_terminals, width, height, + ctrl_mem_size, data_mem_size_global, + data_mem_size_per_bank, num_banks_per_cgra, src_opt, + ctrl_waddr, controller2addr_map): s.num_terminals = num_terminals s.num_tiles = width * height - AddrType = mk_bits(clog2(ctrl_mem_size)) + CtrlAddrType = mk_bits(clog2(ctrl_mem_size)) s.src_opt = [[TestSrcRTL(CtrlType, src_opt[j]) for j in range(s.num_tiles)] for i in range(s.num_terminals)] - s.ctrl_waddr = [[TestSrcRTL(AddrType, ctrl_waddr[j]) + s.ctrl_waddr = [[TestSrcRTL(CtrlAddrType, ctrl_waddr[j]) for j in range(s.num_tiles)] for i in range(s.num_terminals)] - s.dut = DUT(DataType, AddrType, PredicateType, CtrlType, NocPktType, - num_terminals, width, height, ctrl_mem_size, data_mem_size, - len(src_opt[0]), len(src_opt[0]), FunctionUnit, FuList) + s.dut = DUT(DataType, PredicateType, CtrlType, NocPktType, CmdType, + num_terminals, width, height, ctrl_mem_size, + data_mem_size_global, data_mem_size_per_bank, + num_banks_per_cgra, len(src_opt[0]), len(src_opt[0]), + FunctionUnit, FuList, controller2addr_map) # Connections # s.dut.data_mem.recv_from_noc.rdy //= 0 @@ -82,25 +86,36 @@ def test_homo_2x2(cmdline_opts): num_fu_outports = 2 num_routing_outports = num_tile_outports + num_fu_inports ctrl_mem_size = 6 - data_mem_size = 8 + data_mem_size_global = 32 + data_mem_size_per_bank = 4 + num_banks_per_cgra = 2 num_terminals = 4 width = 2 height = 2 TileInType = mk_bits(clog2(num_tile_inports + 1)) FuInType = mk_bits(clog2(num_fu_inports + 1)) FuOutType = mk_bits(clog2(num_fu_outports + 1)) - addr_nbits = clog2(ctrl_mem_size) - AddrType = mk_bits(addr_nbits) + ctrl_addr_nbits = clog2(ctrl_mem_size) + CtrlAddrType = mk_bits(ctrl_addr_nbits) + data_addr_nbits = clog2(data_mem_size_global) + DataAddrType = mk_bits(clog2(data_mem_size_global)) num_tiles = width * height DUT = RingMultiCGRARTL FunctionUnit = FlexibleFuRTL FuList = [MemUnitRTL, AdderRTL] DataType = mk_data(32, 1) PredicateType = mk_predicate(1, 1) + CmdType = mk_bits(4) + controller2addr_map = { + 0: [0, 7], + 1: [8, 15], + 2: [16, 23], + 3: [24, 31], + } CtrlType = mk_separate_ctrl(num_fu_inports, num_fu_outports, num_tile_inports, num_tile_outports) NocPktType = mk_ring_multi_cgra_pkt(nrouters = num_terminals, - addr_nbits = addr_nbits, + addr_nbits = data_addr_nbits, data_nbits = 32, predicate_nbits = 1) pickRegister = [FuInType(x + 1) for x in range(num_fu_inports)] @@ -154,11 +169,12 @@ def test_homo_2x2(cmdline_opts): FuOutType(1), FuOutType(1), FuOutType(1), FuOutType(1)]) ] for _ in range(num_tiles)] - ctrl_waddr = [[AddrType(0), AddrType(1), AddrType(2), AddrType(3), - AddrType(4), AddrType(5)] for _ in range(num_tiles)] + ctrl_waddr = [[CtrlAddrType(0), CtrlAddrType(1), CtrlAddrType(2), CtrlAddrType(3), + CtrlAddrType(4), CtrlAddrType(5)] for _ in range(num_tiles)] th = TestHarness(DUT, FunctionUnit, FuList, DataType, PredicateType, - CtrlType, NocPktType, num_terminals, width, height, - ctrl_mem_size, data_mem_size, src_opt, ctrl_waddr) + CtrlType, NocPktType, CmdType, num_terminals, width, height, + ctrl_mem_size, data_mem_size_global, data_mem_size_per_bank, + num_banks_per_cgra, src_opt, ctrl_waddr, controller2addr_map) th.elaborate() th.dut.set_metadata(VerilogVerilatorImportPass.vl_Wno_list, ['UNSIGNED', 'UNOPTFLAT', 'WIDTH', 'WIDTHCONCAT',