From a66989507575c5b17e2dee4add92ac9dbb425cd9 Mon Sep 17 00:00:00 2001 From: tancheng Date: Sun, 1 Dec 2024 07:37:15 +0000 Subject: [PATCH 1/7] [refactor] Include val/rdy ifcs and re-organize the lib directory --- cgra/CGRACL.py | 15 +- cgra/CGRAFL.py | 3 +- cgra/CGRAKingMeshRTL.py | 23 +- cgra/CGRAMemBottomRTL.py | 22 +- cgra/CGRAMemRightAndBottomRTL.py | 23 +- cgra/CGRARTL.py | 23 +- cgra/CGRASeparateCrossbarRTL.py | 5 +- cgra/CGRATemplateRTL.py | 24 +- cgra/test/CGRACL_FIR_demo_test.py | 35 +- cgra/test/CGRACL_test.py | 26 +- cgra/test/CGRAFL_test.py | 9 +- cgra/test/CGRAKingMeshRTL_test.py | 25 +- cgra/test/CGRARTL_FIR_demo_test.py | 33 +- cgra/test/CGRARTL_test.py | 25 +- cgra/test/CGRASeparateCrossbarRTL_test.py | 5 +- cgra/test/CGRA_custom_test.py | 33 +- cgra/test/VectorCGRAKingMeshRTL_test.py | 40 +- fu/ALUgen_fusedALU_fixedp/ALUgenMACFU.py | 10 +- .../test/ALUgenMACFU_test.py | 22 +- fu/basic/Fu.py | 8 +- fu/basic/ReduceMulUnit.py | 3 + fu/basic/SumUnit.py | 3 + fu/basic/ThreeCombo.py | 9 +- fu/basic/TwoPrlCombo.py | 9 +- fu/basic/TwoSeqCombo.py | 9 +- fu/double/PrlMulAdderRTL.py | 13 +- fu/double/SeqMulAdderRTL.py | 13 +- fu/double/SeqMulShifterRTL.py | 11 +- fu/double/test/TwoPrlComboRTL_test.py | 13 +- fu/double/test/TwoSeqComboRTL_test.py | 16 +- fu/flexible/FlexibleFuRTL.py | 9 +- fu/flexible/FuFL.py | 6 +- .../test/FlexibleFuRTL_hypothesis_test.py | 37 +- fu/flexible/test/FlexibleFuRTL_test.py | 33 +- fu/flexible/translate/FlexibleFuRTL_test.py | 34 +- fu/float/FpAddRTL.py | 11 +- fu/float/FpMulRTL.py | 10 +- fu/float/test/FpAddRTL_test.py | 20 +- fu/pymtl3_fusedALU_fixedp/ALUgenMACRTL.py | 2 + .../test/ALUgenMACRTL_test.py | 8 +- fu/single/AdderCL.py | 11 +- fu/single/AdderRTL.py | 11 +- fu/single/BranchRTL.py | 11 +- fu/single/CompRTL.py | 11 +- fu/single/LogicRTL.py | 10 +- fu/single/MemUnitRTL.py | 11 +- fu/single/MulRTL.py | 10 +- fu/single/PhiRTL.py | 11 +- fu/single/RetRTL.py | 11 +- fu/single/SelRTL.py | 9 +- fu/single/ShifterRTL.py | 11 +- fu/single/test/AdderCL_test.py | 16 +- fu/single/test/AdderRTL_test.py | 16 +- fu/single/test/AluRTL_test.py | 24 +- fu/single/test/BranchRTL_test.py | 14 +- fu/single/test/CompRTL_test.py | 14 +- fu/single/test/MemRTL_test.py | 18 +- fu/single/test/MulRTL_test.py | 6 +- fu/single/test/PhiRTL_test.py | 7 +- fu/single/test/RetRTL_test.py | 6 +- fu/single/test/SelRTL_test.py | 6 +- fu/single/translate/CompRTL_test.py | 8 +- fu/triple/ThreeMulAdderShifterRTL.py | 7 +- fu/triple/test/ThreeMulAluShifterRTL_test.py | 6 +- fu/vector/VectorAdderComboRTL.py | 4 +- fu/vector/VectorAdderRTL.py | 4 +- fu/vector/VectorAllReduceRTL.py | 4 +- fu/vector/VectorMulComboRTL.py | 4 +- fu/vector/VectorMulRTL.py | 5 +- fu/vector/test/VectorAdderComboRTL_test.py | 6 +- fu/vector/test/VectorAdderRTL_test.py | 6 +- fu/vector/test/VectorAllReduceRTL_test.py | 6 +- fu/vector/test/VectorMulComboRTL_test.py | 5 +- fu/vector/test/VectorMulRTL_test.py | 6 +- .../translate/VectorAdderComboRTL_test.py | 2 + fu/vector/translate/VectorMulComboRTL_test.py | 2 + lib/basic/__init__.py | 0 lib/{ => basic/en_rdy}/ifcs.py | 0 lib/{ => basic/en_rdy}/test_sinks.py | 0 lib/{ => basic/en_rdy}/test_srcs.py | 0 lib/basic/val_rdy/SinkRTL.py | 121 ++++ lib/basic/val_rdy/SourceRTL.py | 65 ++ lib/basic/val_rdy/__init__.py | 0 lib/basic/val_rdy/ifcs.py | 61 ++ lib/basic/val_rdy/queues.py | 556 ++++++++++++++++++ lib/util/__init__.py | 0 lib/{ => util}/common.py | 0 lib/{ => util}/ctrl_helper.py | 6 +- lib/{ => util}/dfg_helper.py | 6 +- lib/{ => util}/map_helper.py | 25 +- mem/const/ConstQueueRTL.py | 6 +- mem/const/test/ConstQueueRTL_test.py | 16 +- mem/ctrl/CtrlMemCL.py | 8 +- mem/ctrl/CtrlMemRTL.py | 8 +- mem/ctrl/test/CtrlCL_test.py | 14 +- mem/ctrl/test/CtrlRTL_AdderCL_test.py | 18 +- mem/ctrl/test/CtrlRTL_test.py | 18 +- mem/data/DataMemCL.py | 12 +- mem/data/DataMemRTL.py | 10 +- mem/data/test/DataMemCL_test.py | 14 +- noc/BlockChannelRTL.py | 2 +- noc/BypassChannelRTL.py | 4 +- noc/ChannelNormalRTL.py | 3 +- noc/ChannelRTL.py | 2 +- noc/CrossbarRTL.py | 3 +- noc/CrossbarSeparateRTL.py | 2 +- noc/DelayChannelRTL.py | 3 +- noc/LinkOrRTL.py | 2 +- noc/MulticasterRTL.py | 2 +- noc/test/BlockChannelRTL_test.py | 4 +- noc/test/ChannelNormalRTL_test.py | 4 +- noc/test/ChannelRTL_test.py | 4 +- noc/test/CrossbarBlockRTL_test.py | 4 +- noc/test/CrossbarDelayRTL_test.py | 10 +- noc/test/CrossbarRTL_test.py | 4 +- noc/test/LinkOrRTL_test.py | 9 +- noc/test/Multicaster_test.py | 11 +- rf/RegFile.py | 8 +- rf/RegisterRTL.py | 25 +- rf/test/RegFile_test.py | 12 +- rf/test/RegisterRTL_test.py | 25 +- systolic/SystolicCL.py | 16 +- systolic/test/SystolicCL_test.py | 24 +- tile/TileCL.py | 18 +- tile/TileRTL.py | 28 +- tile/TileSeparateCrossbarRTL.py | 7 +- tile/test/TileCL_test.py | 22 +- tile/test/TileRTL_test.py | 33 +- tile/test/TileSeparateCrossbarRTL_test.py | 15 +- tile/translate/TileRTL_test.py | 37 +- 130 files changed, 1578 insertions(+), 726 deletions(-) create mode 100644 lib/basic/__init__.py rename lib/{ => basic/en_rdy}/ifcs.py (100%) rename lib/{ => basic/en_rdy}/test_sinks.py (100%) rename lib/{ => basic/en_rdy}/test_srcs.py (100%) create mode 100644 lib/basic/val_rdy/SinkRTL.py create mode 100644 lib/basic/val_rdy/SourceRTL.py create mode 100644 lib/basic/val_rdy/__init__.py create mode 100644 lib/basic/val_rdy/ifcs.py create mode 100644 lib/basic/val_rdy/queues.py create mode 100644 lib/util/__init__.py rename lib/{ => util}/common.py (100%) rename lib/{ => util}/ctrl_helper.py (96%) rename lib/{ => util}/dfg_helper.py (99%) rename lib/{ => util}/map_helper.py (83%) diff --git a/cgra/CGRACL.py b/cgra/CGRACL.py index 6a7227f..ff6d09c 100644 --- a/cgra/CGRACL.py +++ b/cgra/CGRACL.py @@ -7,14 +7,15 @@ Date : Dec 28, 2019 """ -from pymtl3 import * -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileCL import TileCL -from ..lib.opt_type import * -from ..lib.common import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL +from pymtl3 import * +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * +from ..lib.util.common import * +from ..noc.CrossbarRTL import CrossbarRTL +from ..noc.ChannelRTL import ChannelRTL from ..mem.data.DataMemCL import DataMemCL +from ..tile.TileCL import TileCL + class CGRACL( Component ): diff --git a/cgra/CGRAFL.py b/cgra/CGRAFL.py index ec524e9..e32ab0c 100644 --- a/cgra/CGRAFL.py +++ b/cgra/CGRAFL.py @@ -6,10 +6,9 @@ Author : Cheng Tan Date : Feb 13, 2020 - """ -from pymtl3 import * +from pymtl3 import * from ..lib.opt_type import * from ..lib.messages import * diff --git a/cgra/CGRAKingMeshRTL.py b/cgra/CGRAKingMeshRTL.py index 4cf1c80..e9e37b0 100644 --- a/cgra/CGRAKingMeshRTL.py +++ b/cgra/CGRAKingMeshRTL.py @@ -6,19 +6,20 @@ Date : Dec 15, 2019 """ -from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileRTL import TileRTL -from ..lib.opt_type import * -from ..lib.common import * -from ..mem.data.DataMemRTL import DataMemRTL -from ..mem.data.DataMemCL import DataMemCL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.AdderRTL import AdderRTL +from pymtl3 import * +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..noc.ChannelRTL import ChannelRTL +from ..tile.TileRTL import TileRTL +from ..lib.opt_type import * +from ..lib.util.common import * +from ..mem.data.DataMemRTL import DataMemRTL +from ..mem.data.DataMemCL import DataMemCL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..fu.single.AdderRTL import AdderRTL from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL + class CGRAKingMeshRTL( Component ): def construct( s, DataType, PredicateType, CtrlType, width, height, diff --git a/cgra/CGRAMemBottomRTL.py b/cgra/CGRAMemBottomRTL.py index 1130e8f..92c484f 100644 --- a/cgra/CGRAMemBottomRTL.py +++ b/cgra/CGRAMemBottomRTL.py @@ -8,18 +8,18 @@ Date : Nov 18, 2024 """ -from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileRTL import TileRTL -from ..lib.opt_type import * -from ..lib.common import * -from ..mem.data.DataMemRTL import DataMemRTL -from ..mem.data.DataMemCL import DataMemCL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.AdderRTL import AdderRTL +from pymtl3 import * from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..fu.single.AdderRTL import AdderRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * +from ..lib.util.common import * +from ..mem.data.DataMemRTL import DataMemRTL +from ..mem.data.DataMemCL import DataMemCL +from ..noc.ChannelRTL import ChannelRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..tile.TileRTL import TileRTL class CGRAMemBottomRTL(Component): diff --git a/cgra/CGRAMemRightAndBottomRTL.py b/cgra/CGRAMemRightAndBottomRTL.py index 5b600e5..1436276 100644 --- a/cgra/CGRAMemRightAndBottomRTL.py +++ b/cgra/CGRAMemRightAndBottomRTL.py @@ -11,18 +11,19 @@ Date : Nov 19, 2024 """ -from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileRTL import TileRTL -from ..lib.opt_type import * -from ..lib.common import * -from ..mem.data.DataMemRTL import DataMemRTL -from ..mem.data.DataMemCL import DataMemCL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.AdderRTL import AdderRTL +from pymtl3 import * from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..fu.single.AdderRTL import AdderRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * +from ..lib.util.common import * +from ..mem.data.DataMemRTL import DataMemRTL +from ..mem.data.DataMemCL import DataMemCL +from ..noc.ChannelRTL import ChannelRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..tile.TileRTL import TileRTL + class CGRAMemRightAndBottomRTL(Component): diff --git a/cgra/CGRARTL.py b/cgra/CGRARTL.py index 989bfd8..a7a0ec2 100644 --- a/cgra/CGRARTL.py +++ b/cgra/CGRARTL.py @@ -6,18 +6,19 @@ Date : Dec 15, 2019 """ -from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileRTL import TileRTL -from ..lib.opt_type import * -from ..lib.common import * -from ..mem.data.DataMemRTL import DataMemRTL -from ..mem.data.DataMemCL import DataMemCL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.AdderRTL import AdderRTL +from pymtl3 import * from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..fu.single.AdderRTL import AdderRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * +from ..lib.util.common import * +from ..mem.data.DataMemRTL import DataMemRTL +from ..mem.data.DataMemCL import DataMemCL +from ..noc.ChannelRTL import ChannelRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..tile.TileRTL import TileRTL + class CGRARTL( Component ): diff --git a/cgra/CGRASeparateCrossbarRTL.py b/cgra/CGRASeparateCrossbarRTL.py index eb837db..8ea53bf 100644 --- a/cgra/CGRASeparateCrossbarRTL.py +++ b/cgra/CGRASeparateCrossbarRTL.py @@ -11,8 +11,8 @@ from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL from ..fu.single.MemUnitRTL import MemUnitRTL from ..fu.single.AdderRTL import AdderRTL -from ..lib.common import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.util.common import * +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ..lib.opt_type import * from ..mem.data.DataMemCL import DataMemCL from ..mem.data.DataMemRTL import DataMemRTL @@ -20,6 +20,7 @@ from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL from ..tile.TileSeparateCrossbarRTL import TileSeparateCrossbarRTL + class CGRASeparateCrossbarRTL(Component): def construct(s, DataType, PredicateType, CtrlType, width, height, ctrl_mem_size, data_mem_size, num_ctrl, total_steps, diff --git a/cgra/CGRATemplateRTL.py b/cgra/CGRATemplateRTL.py index 4825ea2..30a279b 100644 --- a/cgra/CGRATemplateRTL.py +++ b/cgra/CGRATemplateRTL.py @@ -6,18 +6,20 @@ Date : Dec 15, 2019 """ -from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileRTL import TileRTL -from ..lib.opt_type import * -from ..lib.common import * -from ..mem.data.DataMemRTL import DataMemRTL -from ..mem.data.DataMemCL import DataMemCL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.AdderRTL import AdderRTL + +from pymtl3 import * from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..fu.single.AdderRTL import AdderRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * +from ..lib.util.common import * +from ..mem.data.DataMemRTL import DataMemRTL +from ..mem.data.DataMemCL import DataMemCL +from ..noc.ChannelRTL import ChannelRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..tile.TileRTL import TileRTL + class CGRATemplateRTL( Component ): diff --git a/cgra/test/CGRACL_FIR_demo_test.py b/cgra/test/CGRACL_FIR_demo_test.py index 436afd6..b9566d8 100644 --- a/cgra/test/CGRACL_FIR_demo_test.py +++ b/cgra/test/CGRACL_FIR_demo_test.py @@ -6,32 +6,29 @@ Author : Cheng Tan Date : Dec 28, 2019 - """ -from pymtl3 import * - -from ...lib.opt_type import * -from ...lib.messages import * +from pymtl3 import * +from ..CGRACL import CGRACL +from ..CGRAFL import CGRAFL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.LogicRTL import LogicRTL -from ...fu.single.CompRTL import CompRTL -from ...fu.single.BranchRTL import BranchRTL -from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ..CGRACL import CGRACL - -from ..CGRAFL import CGRAFL -from ...lib.dfg_helper import * -from ...lib.ctrl_helper import * - +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.ShifterRTL import ShifterRTL +from ...lib.util.ctrl_helper import * +from ...lib.util.dfg_helper import * +from ...lib.messages import * +from ...lib.opt_type import * import copy import os + #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- diff --git a/cgra/test/CGRACL_test.py b/cgra/test/CGRACL_test.py index 58230a5..2511f97 100644 --- a/cgra/test/CGRACL_test.py +++ b/cgra/test/CGRACL_test.py @@ -6,26 +6,24 @@ Author : Cheng Tan Date : Dec 28, 2019 - """ -from pymtl3 import * - -from ...lib.opt_type import * -from ...lib.messages import * -from ...lib.ctrl_helper import * +from pymtl3 import * +from ..CGRACL import CGRACL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL -from ...fu.single.BranchRTL import BranchRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ..CGRACL import CGRACL - +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...lib.opt_type import * +from ...lib.messages import * +from ...lib.util.ctrl_helper import * import os + #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- diff --git a/cgra/test/CGRAFL_test.py b/cgra/test/CGRAFL_test.py index 87df9b7..44a25e6 100644 --- a/cgra/test/CGRAFL_test.py +++ b/cgra/test/CGRAFL_test.py @@ -9,13 +9,14 @@ """ -from pymtl3 import * -from ...lib.messages import * -from ..CGRAFL import CGRAFL -from ...lib.dfg_helper import * +from pymtl3 import * +from ...lib.messages import * +from ..CGRAFL import CGRAFL +from ...lib.util.dfg_helper import * import os + def test_fl(): target_json = "dfg_fir.json" script_dir = os.path.dirname(__file__) diff --git a/cgra/test/CGRAKingMeshRTL_test.py b/cgra/test/CGRAKingMeshRTL_test.py index 8f60271..7553b54 100644 --- a/cgra/test/CGRAKingMeshRTL_test.py +++ b/cgra/test/CGRAKingMeshRTL_test.py @@ -6,24 +6,23 @@ Author : Cheng Tan Date : Dec 15, 2019 - """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) + +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) from pymtl3.passes.backends.verilog import (VerilogTranslationPass, VerilogVerilatorImportPass) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * - +from ..CGRAKingMeshRTL import CGRAKingMeshRTL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ..CGRAKingMeshRTL import CGRAKingMeshRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.ShifterRTL import ShifterRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/cgra/test/CGRARTL_FIR_demo_test.py b/cgra/test/CGRARTL_FIR_demo_test.py index fac9d60..de64112 100644 --- a/cgra/test/CGRARTL_FIR_demo_test.py +++ b/cgra/test/CGRARTL_FIR_demo_test.py @@ -6,32 +6,29 @@ Author : Cheng Tan Date : Dec 15, 2019 - """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) + +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) from pymtl3.passes.backends.verilog import (VerilogTranslationPass, VerilogVerilatorImportPass) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * - +from ..CGRAFL import CGRAFL +from ..CGRARTL import CGRARTL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ..CGRARTL import CGRARTL - -from ..CGRAFL import CGRAFL -from ...lib.dfg_helper import * -from ...lib.ctrl_helper import * - +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.ShifterRTL import ShifterRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * +from ...lib.util.dfg_helper import * +from ...lib.util.ctrl_helper import * import copy import os + #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- diff --git a/cgra/test/CGRARTL_test.py b/cgra/test/CGRARTL_test.py index 940cd73..5c34b4a 100644 --- a/cgra/test/CGRARTL_test.py +++ b/cgra/test/CGRARTL_test.py @@ -6,24 +6,23 @@ Author : Cheng Tan Date : Dec 15, 2019 - """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) + +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) from pymtl3.passes.backends.verilog import (VerilogTranslationPass, VerilogVerilatorImportPass) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * - +from ..CGRARTL import CGRARTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ..CGRARTL import CGRARTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.ShifterRTL import ShifterRTL + #------------------------------------------------------------------------- # Test harness diff --git a/cgra/test/CGRASeparateCrossbarRTL_test.py b/cgra/test/CGRASeparateCrossbarRTL_test.py index 4b9d12f..a80e20b 100644 --- a/cgra/test/CGRASeparateCrossbarRTL_test.py +++ b/cgra/test/CGRASeparateCrossbarRTL_test.py @@ -6,9 +6,9 @@ Author : Cheng Tan Date : Nov 29, 2024 - """ + from pymtl3 import * from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) @@ -21,7 +21,8 @@ from ...fu.single.ShifterRTL import ShifterRTL from ...lib.messages import * from ...lib.opt_type import * -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL + #------------------------------------------------------------------------- # Test harness diff --git a/cgra/test/CGRA_custom_test.py b/cgra/test/CGRA_custom_test.py index c6bd721..49c01b3 100644 --- a/cgra/test/CGRA_custom_test.py +++ b/cgra/test/CGRA_custom_test.py @@ -6,29 +6,26 @@ Author : Cheng Tan & Ron Jokai Date : Dec 24, 2023 - """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) -from pymtl3.passes.backends.verilog import (VerilogTranslationPass, - VerilogVerilatorImportPass) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * - -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ..CGRAKingMeshRTL import CGRAKingMeshRTL +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) +from pymtl3.passes.backends.verilog import (VerilogTranslationPass, + VerilogVerilatorImportPass) +from ..CGRAKingMeshRTL import CGRAKingMeshRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.opt_type import * +from ...lib.messages import * +from ...fu.ALUgen_fusedALU_fixedp.ALUgenMACFU import ALUgenMACFU +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.float.FpAddRTL import FpAddRTL from ...fu.pymtl3_hardfloat.HardFloat.AddFNRTL import AddFN -from ...fu.float.FpAddRTL import FpAddRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.ALUgen_fusedALU_fixedp.ALUgenMACFU import ALUgenMACFU #------------------------------------------------------------------------- # Test harness diff --git a/cgra/test/VectorCGRAKingMeshRTL_test.py b/cgra/test/VectorCGRAKingMeshRTL_test.py index 2cd999c..2019af5 100644 --- a/cgra/test/VectorCGRAKingMeshRTL_test.py +++ b/cgra/test/VectorCGRAKingMeshRTL_test.py @@ -6,33 +6,31 @@ Author : Cheng Tan Date : April 1, 2023 - """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) + +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) from pymtl3.passes.backends.verilog import (VerilogTranslationPass, VerilogVerilatorImportPass) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * - -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.SelRTL import SelRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.LogicRTL import LogicRTL -from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL -from ...fu.single.BranchRTL import BranchRTL -from ...fu.vector.VectorMulComboRTL import VectorMulComboRTL +from ..CGRAKingMeshRTL import CGRAKingMeshRTL +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.SelRTL import SelRTL +from ...fu.single.ShifterRTL import ShifterRTL +from ...fu.single.LogicRTL import LogicRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.vector.VectorMulComboRTL import VectorMulComboRTL from ...fu.vector.VectorAdderComboRTL import VectorAdderComboRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * -from ..CGRAKingMeshRTL import CGRAKingMeshRTL #------------------------------------------------------------------------- # Test harness diff --git a/fu/ALUgen_fusedALU_fixedp/ALUgenMACFU.py b/fu/ALUgen_fusedALU_fixedp/ALUgenMACFU.py index 4dd9f9c..26ec95a 100644 --- a/fu/ALUgen_fusedALU_fixedp/ALUgenMACFU.py +++ b/fu/ALUgen_fusedALU_fixedp/ALUgenMACFU.py @@ -8,11 +8,13 @@ Date : Jan 6, 2024 """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu from ..pymtl3_fusedALU_fixedp.ALUgenMACRTL import ALUgenMAC +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class ALUgenMACFU( Fu ): def construct( s, DataType, PredicateType, CtrlType, diff --git a/fu/ALUgen_fusedALU_fixedp/test/ALUgenMACFU_test.py b/fu/ALUgen_fusedALU_fixedp/test/ALUgenMACFU_test.py index 8ed5eba..46f7f8a 100644 --- a/fu/ALUgen_fusedALU_fixedp/test/ALUgenMACFU_test.py +++ b/fu/ALUgen_fusedALU_fixedp/test/ALUgenMACFU_test.py @@ -1,21 +1,23 @@ """ ========================================================================== -_test.py +ALUgenMACFU_test.py ========================================================================== Author : RJ Date : Jan 6, 2024 """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * -from ....mem.const.ConstQueueRTL import ConstQueueRTL -from ..ALUgenMACFU import ALUgenMACFU + +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) +from ..ALUgenMACFU import ALUgenMACFU +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....mem.const.ConstQueueRTL import ConstQueueRTL + def test_elaborate( cmdline_opts ): DataType = mk_data( 16, 1 ) diff --git a/fu/basic/Fu.py b/fu/basic/Fu.py index 2f1c30c..3b76723 100644 --- a/fu/basic/Fu.py +++ b/fu/basic/Fu.py @@ -9,9 +9,11 @@ Date : August 6, 2023 """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class Fu( Component ): diff --git a/fu/basic/ReduceMulUnit.py b/fu/basic/ReduceMulUnit.py index de33050..9bfe385 100644 --- a/fu/basic/ReduceMulUnit.py +++ b/fu/basic/ReduceMulUnit.py @@ -13,9 +13,12 @@ Date : Jul 30, 2023 ''' + from pymtl3 import * + class ReduceMulUnit( Component ): + def construct( s, DataType, num_inputs ): # Local parameter s.DataType = DataType diff --git a/fu/basic/SumUnit.py b/fu/basic/SumUnit.py index 0eb154b..b1374b7 100644 --- a/fu/basic/SumUnit.py +++ b/fu/basic/SumUnit.py @@ -12,9 +12,12 @@ Date : Jul 30, 2023 ''' + from pymtl3 import * + class SumUnit( Component ): + def construct( s, DataType, num_inputs ): # Local parameter s.DataType = DataType diff --git a/fu/basic/ThreeCombo.py b/fu/basic/ThreeCombo.py index 8155004..892ee49 100644 --- a/fu/basic/ThreeCombo.py +++ b/fu/basic/ThreeCombo.py @@ -7,12 +7,13 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class ThreeCombo( Component ): diff --git a/fu/basic/TwoPrlCombo.py b/fu/basic/TwoPrlCombo.py index 19685ff..420378d 100644 --- a/fu/basic/TwoPrlCombo.py +++ b/fu/basic/TwoPrlCombo.py @@ -6,12 +6,13 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class TwoPrlCombo( Component ): diff --git a/fu/basic/TwoSeqCombo.py b/fu/basic/TwoSeqCombo.py index ed02d5f..32ae75f 100644 --- a/fu/basic/TwoSeqCombo.py +++ b/fu/basic/TwoSeqCombo.py @@ -6,12 +6,13 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class TwoSeqCombo( Component ): diff --git a/fu/double/PrlMulAdderRTL.py b/fu/double/PrlMulAdderRTL.py index 28f5b0b..4ba88e8 100644 --- a/fu/double/PrlMulAdderRTL.py +++ b/fu/double/PrlMulAdderRTL.py @@ -6,15 +6,16 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * from ..basic.TwoPrlCombo import TwoPrlCombo -from ..single.MulRTL import MulRTL -from ..single.AdderRTL import AdderRTL +from ..single.MulRTL import MulRTL +from ..single.AdderRTL import AdderRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class PrlMulAdderRTL( TwoPrlCombo ): diff --git a/fu/double/SeqMulAdderRTL.py b/fu/double/SeqMulAdderRTL.py index e6cb9e1..c8953ed 100644 --- a/fu/double/SeqMulAdderRTL.py +++ b/fu/double/SeqMulAdderRTL.py @@ -6,15 +6,16 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * from ..basic.TwoSeqCombo import TwoSeqCombo -from ..single.MulRTL import MulRTL -from ..single.AdderRTL import AdderRTL +from ..single.MulRTL import MulRTL +from ..single.AdderRTL import AdderRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class SeqMulAdderRTL( TwoSeqCombo ): diff --git a/fu/double/SeqMulShifterRTL.py b/fu/double/SeqMulShifterRTL.py index 6f49540..1cccac1 100644 --- a/fu/double/SeqMulShifterRTL.py +++ b/fu/double/SeqMulShifterRTL.py @@ -6,15 +6,16 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * from ..basic.TwoSeqCombo import TwoSeqCombo -from ..single.MulRTL import MulRTL +from ..single.MulRTL import MulRTL from ..single.ShifterRTL import ShifterRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class SeqMulShifterRTL( TwoSeqCombo ): diff --git a/fu/double/test/TwoPrlComboRTL_test.py b/fu/double/test/TwoPrlComboRTL_test.py index 64bce90..ab2d66f 100644 --- a/fu/double/test/TwoPrlComboRTL_test.py +++ b/fu/double/test/TwoPrlComboRTL_test.py @@ -6,16 +6,15 @@ Author : Cheng Tan Date : November 29, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ..PrlMulAdderRTL import PrlMulAdderRTL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..PrlMulAdderRTL import PrlMulAdderRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * #------------------------------------------------------------------------- # Test harness diff --git a/fu/double/test/TwoSeqComboRTL_test.py b/fu/double/test/TwoSeqComboRTL_test.py index 160522e..8626744 100644 --- a/fu/double/test/TwoSeqComboRTL_test.py +++ b/fu/double/test/TwoSeqComboRTL_test.py @@ -6,17 +6,17 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ..SeqMulAdderRTL import SeqMulAdderRTL -from ..SeqMulShifterRTL import SeqMulShifterRTL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..SeqMulAdderRTL import SeqMulAdderRTL +from ..SeqMulShifterRTL import SeqMulShifterRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/fu/flexible/FlexibleFuRTL.py b/fu/flexible/FlexibleFuRTL.py index 8c048d1..2fdbadd 100644 --- a/fu/flexible/FlexibleFuRTL.py +++ b/fu/flexible/FlexibleFuRTL.py @@ -9,11 +9,12 @@ """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * +from pymtl3 import * from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.AdderRTL import AdderRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class FlexibleFuRTL( Component ): diff --git a/fu/flexible/FuFL.py b/fu/flexible/FuFL.py index 069522b..c06d8d7 100644 --- a/fu/flexible/FuFL.py +++ b/fu/flexible/FuFL.py @@ -7,16 +7,18 @@ Author : Cheng Tan Date : April 8, 2020 - """ -from pymtl3 import * + +from pymtl3 import * from ...lib.opt_type import * from ...lib.messages import * + #------------------------------------------------------------------------ # Assuming that the elements in FuDFG are already ordered well. #------------------------------------------------------------------------ + def FuFL( DataType, input_a, input_b, opt ): out_list = [] for i in range( len( input_a ) ): diff --git a/fu/flexible/test/FlexibleFuRTL_hypothesis_test.py b/fu/flexible/test/FlexibleFuRTL_hypothesis_test.py index 64f5318..ff9c7b6 100644 --- a/fu/flexible/test/FlexibleFuRTL_hypothesis_test.py +++ b/fu/flexible/test/FlexibleFuRTL_hypothesis_test.py @@ -6,30 +6,27 @@ Author : Cheng Tan Date : Dec 14, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL - -from ..FlexibleFuRTL import FlexibleFuRTL -from ....lib.opt_type import * -from ....lib.messages import * - -from ...single.AdderRTL import AdderRTL -from ...single.MulRTL import MulRTL -from ...single.ShifterRTL import ShifterRTL -from ...single.LogicRTL import LogicRTL -from ...single.PhiRTL import PhiRTL -from ...single.MemUnitRTL import MemUnitRTL -from ...single.CompRTL import CompRTL -from ...single.BranchRTL import BranchRTL - -from ..FuFL import * -import hypothesis +from pymtl3 import * from hypothesis import strategies as st +from ..FlexibleFuRTL import FlexibleFuRTL +from ..FuFL import * +from ...single.AdderRTL import AdderRTL +from ...single.BranchRTL import BranchRTL +from ...single.CompRTL import CompRTL +from ...single.LogicRTL import LogicRTL +from ...single.MemUnitRTL import MemUnitRTL +from ...single.MulRTL import MulRTL +from ...single.PhiRTL import PhiRTL +from ...single.ShifterRTL import ShifterRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.opt_type import * +from ....lib.messages import * +import hypothesis + #from pymtl3.passes.backends.verilog import TranslationImportPass diff --git a/fu/flexible/test/FlexibleFuRTL_test.py b/fu/flexible/test/FlexibleFuRTL_test.py index 124c53b..8de7144 100644 --- a/fu/flexible/test/FlexibleFuRTL_test.py +++ b/fu/flexible/test/FlexibleFuRTL_test.py @@ -6,25 +6,24 @@ Author : Cheng Tan Date : Dec 14, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL - -from ..FlexibleFuRTL import FlexibleFuRTL -from ....lib.opt_type import * -from ....lib.messages import * - -from ...single.AdderRTL import AdderRTL -from ...single.MulRTL import MulRTL -from ...single.ShifterRTL import ShifterRTL -from ...single.LogicRTL import LogicRTL -from ...single.PhiRTL import PhiRTL -from ...single.MemUnitRTL import MemUnitRTL -from ...single.CompRTL import CompRTL -from ...single.BranchRTL import BranchRTL + +from pymtl3 import * +from ..FlexibleFuRTL import FlexibleFuRTL +from ...single.AdderRTL import AdderRTL +from ...single.BranchRTL import BranchRTL +from ...single.CompRTL import CompRTL +from ...single.LogicRTL import LogicRTL +from ...single.MemUnitRTL import MemUnitRTL +from ...single.MulRTL import MulRTL +from ...single.PhiRTL import PhiRTL +from ...single.ShifterRTL import ShifterRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.opt_type import * +from ....lib.messages import * + #------------------------------------------------------------------------- # Test harness diff --git a/fu/flexible/translate/FlexibleFuRTL_test.py b/fu/flexible/translate/FlexibleFuRTL_test.py index b7e293d..d5ba865 100644 --- a/fu/flexible/translate/FlexibleFuRTL_test.py +++ b/fu/flexible/translate/FlexibleFuRTL_test.py @@ -6,28 +6,26 @@ Author : Cheng Tan Date : Dec 14, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL - -from ..FlexibleFuRTL import FlexibleFuRTL -from ....lib.opt_type import * -from ....lib.messages import * - -from ...single.AdderRTL import AdderRTL -from ...single.MulRTL import MulRTL -from ...single.ShifterRTL import ShifterRTL -from ...single.SelRTL import SelRTL -from ...single.LogicRTL import LogicRTL -from ...single.PhiRTL import PhiRTL -from ...single.MemUnitRTL import MemUnitRTL -from ...single.CompRTL import CompRTL -from ...single.BranchRTL import BranchRTL +from pymtl3 import * from pymtl3.stdlib.test_utils import run_sim, config_model_with_cmdline_opts +from ..FlexibleFuRTL import FlexibleFuRTL +from ...single.AdderRTL import AdderRTL +from ...single.BranchRTL import BranchRTL +from ...single.CompRTL import CompRTL +from ...single.LogicRTL import LogicRTL +from ...single.MemUnitRTL import MemUnitRTL +from ...single.MulRTL import MulRTL +from ...single.PhiRTL import PhiRTL +from ...single.SelRTL import SelRTL +from ...single.ShifterRTL import ShifterRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/fu/float/FpAddRTL.py b/fu/float/FpAddRTL.py index 90ec17a..e3e23b0 100644 --- a/fu/float/FpAddRTL.py +++ b/fu/float/FpAddRTL.py @@ -16,13 +16,16 @@ Date : Aug 8, 2023 """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu from ..pymtl3_hardfloat.HardFloat.AddFNRTL import AddFN +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class FpAddRTL( Fu ): + def construct( s, DataType, PredicateType, CtrlType, num_inports, num_outports, data_mem_size, exp_nbits = 4, sig_nbits = 11 ): diff --git a/fu/float/FpMulRTL.py b/fu/float/FpMulRTL.py index c6167b3..4194a19 100644 --- a/fu/float/FpMulRTL.py +++ b/fu/float/FpMulRTL.py @@ -16,11 +16,13 @@ Date : August 9, 2023 """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu from ..pymtl3_hardfloat.HardFloat.MulFNRTL import MulFN +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class FpMulRTL( Fu ): diff --git a/fu/float/test/FpAddRTL_test.py b/fu/float/test/FpAddRTL_test.py index 9b9ab6e..292fa4a 100644 --- a/fu/float/test/FpAddRTL_test.py +++ b/fu/float/test/FpAddRTL_test.py @@ -8,17 +8,19 @@ Date : Aug 8, 2023 """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * -from ....mem.const.ConstQueueRTL import ConstQueueRTL -from ..FpAddRTL import FpAddRTL + +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) +from ..FpAddRTL import FpAddRTL from ...pymtl3_hardfloat.HardFloat.converter_funcs import (floatToFN, fNToFloat) +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....mem.const.ConstQueueRTL import ConstQueueRTL + round_near_even = 0b000 diff --git a/fu/pymtl3_fusedALU_fixedp/ALUgenMACRTL.py b/fu/pymtl3_fusedALU_fixedp/ALUgenMACRTL.py index 231baad..0107d7b 100644 --- a/fu/pymtl3_fusedALU_fixedp/ALUgenMACRTL.py +++ b/fu/pymtl3_fusedALU_fixedp/ALUgenMACRTL.py @@ -2,9 +2,11 @@ # Wrapper for HardFloat's addition and subtraction module #========================================================================= + from pymtl3 import * from pymtl3.passes.backends.verilog import * + class ALUgenMAC( VerilogPlaceholder, Component ): # Constructor diff --git a/fu/pymtl3_fusedALU_fixedp/test/ALUgenMACRTL_test.py b/fu/pymtl3_fusedALU_fixedp/test/ALUgenMACRTL_test.py index 0b4d186..29f4736 100644 --- a/fu/pymtl3_fusedALU_fixedp/test/ALUgenMACRTL_test.py +++ b/fu/pymtl3_fusedALU_fixedp/test/ALUgenMACRTL_test.py @@ -2,17 +2,15 @@ # Unit testing for AddFNRTL PyMTL wrapper module #========================================================================= + from pymtl3 import * from pymtl3.stdlib.test_utils import run_test_vector_sim, TestVectorSimulator from pymtl3.passes.backends.verilog import * - -import hypothesis from hypothesis import given -from hypothesis import strategies as st from hypothesis import settings - +from hypothesis import strategies as st from ..ALUgenMACRTL import ALUgenMAC - +import hypothesis import random diff --git a/fu/single/AdderCL.py b/fu/single/AdderCL.py index 682ed91..19cd19e 100644 --- a/fu/single/AdderCL.py +++ b/fu/single/AdderCL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : Aug 5, 2023 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class AdderCL( Fu ): diff --git a/fu/single/AdderRTL.py b/fu/single/AdderRTL.py index dc076fe..cba43b9 100644 --- a/fu/single/AdderRTL.py +++ b/fu/single/AdderRTL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class AdderRTL( Fu ): diff --git a/fu/single/BranchRTL.py b/fu/single/BranchRTL.py index 0b13a88..bb0c6cf 100644 --- a/fu/single/BranchRTL.py +++ b/fu/single/BranchRTL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : December 1, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class BranchRTL( Fu ): diff --git a/fu/single/CompRTL.py b/fu/single/CompRTL.py index 6181c0a..978d683 100644 --- a/fu/single/CompRTL.py +++ b/fu/single/CompRTL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : December 2, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class CompRTL( Fu ): diff --git a/fu/single/LogicRTL.py b/fu/single/LogicRTL.py index a2814d3..466c45f 100644 --- a/fu/single/LogicRTL.py +++ b/fu/single/LogicRTL.py @@ -6,13 +6,13 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * class LogicRTL( Fu ): diff --git a/fu/single/MemUnitRTL.py b/fu/single/MemUnitRTL.py index 8bf3bf5..8e8a37d 100644 --- a/fu/single/MemUnitRTL.py +++ b/fu/single/MemUnitRTL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : November 29, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class MemUnitRTL( Component ): diff --git a/fu/single/MulRTL.py b/fu/single/MulRTL.py index 8b16dc3..466aff9 100644 --- a/fu/single/MulRTL.py +++ b/fu/single/MulRTL.py @@ -8,10 +8,12 @@ Date : November 28, 2019 """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class MulRTL( Fu ): diff --git a/fu/single/PhiRTL.py b/fu/single/PhiRTL.py index 1c253a0..e770a18 100644 --- a/fu/single/PhiRTL.py +++ b/fu/single/PhiRTL.py @@ -6,15 +6,16 @@ Author : Cheng Tan Date : November 30, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * import copy + class PhiRTL( Fu ): def construct( s, DataType, PredicateType, CtrlType, diff --git a/fu/single/RetRTL.py b/fu/single/RetRTL.py index 880935c..a9a45e4 100644 --- a/fu/single/RetRTL.py +++ b/fu/single/RetRTL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : September 21, 2021 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class RetRTL( Fu ): diff --git a/fu/single/SelRTL.py b/fu/single/SelRTL.py index b62a790..85eeab7 100644 --- a/fu/single/SelRTL.py +++ b/fu/single/SelRTL.py @@ -6,12 +6,13 @@ Author : Cheng Tan Date : May 23, 2020 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * + +from pymtl3 import * +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class SelRTL( Component ): diff --git a/fu/single/ShifterRTL.py b/fu/single/ShifterRTL.py index e2d2752..ed3e0fd 100644 --- a/fu/single/ShifterRTL.py +++ b/fu/single/ShifterRTL.py @@ -6,13 +6,14 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * -from ..basic.Fu import Fu + +from pymtl3 import * +from ..basic.Fu import Fu +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class ShifterRTL( Fu ): diff --git a/fu/single/test/AdderCL_test.py b/fu/single/test/AdderCL_test.py index c0d770d..e4e0842 100644 --- a/fu/single/test/AdderCL_test.py +++ b/fu/single/test/AdderCL_test.py @@ -6,17 +6,17 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ..AdderCL import AdderCL -from ....mem.const.ConstQueueRTL import ConstQueueRTL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..AdderCL import AdderCL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....mem.const.ConstQueueRTL import ConstQueueRTL + #------------------------------------------------------------------------- # Test harness diff --git a/fu/single/test/AdderRTL_test.py b/fu/single/test/AdderRTL_test.py index e01d3cc..cd30f50 100644 --- a/fu/single/test/AdderRTL_test.py +++ b/fu/single/test/AdderRTL_test.py @@ -6,17 +6,17 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ..AdderRTL import AdderRTL -from ....mem.const.ConstQueueRTL import ConstQueueRTL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..AdderRTL import AdderRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....mem.const.ConstQueueRTL import ConstQueueRTL + #------------------------------------------------------------------------- # Test harness diff --git a/fu/single/test/AluRTL_test.py b/fu/single/test/AluRTL_test.py index f24cb63..23aca44 100644 --- a/fu/single/test/AluRTL_test.py +++ b/fu/single/test/AluRTL_test.py @@ -6,20 +6,20 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL - -from ..AdderRTL import AdderRTL -from ..ShifterRTL import ShifterRTL -from ..MulRTL import MulRTL -from ..LogicRTL import LogicRTL -from ....mem.const.ConstQueueRTL import ConstQueueRTL -from ....lib.opt_type import * -from ....lib.messages import * + +from pymtl3 import * +from ..AdderRTL import AdderRTL +from ..LogicRTL import LogicRTL +from ..MulRTL import MulRTL +from ..ShifterRTL import ShifterRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....mem.const.ConstQueueRTL import ConstQueueRTL + #------------------------------------------------------------------------- # Test harness diff --git a/fu/single/test/BranchRTL_test.py b/fu/single/test/BranchRTL_test.py index cc5a48b..d724f45 100644 --- a/fu/single/test/BranchRTL_test.py +++ b/fu/single/test/BranchRTL_test.py @@ -6,16 +6,16 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ..BranchRTL import BranchRTL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..BranchRTL import BranchRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/fu/single/test/CompRTL_test.py b/fu/single/test/CompRTL_test.py index 9bf2825..d5b62f6 100644 --- a/fu/single/test/CompRTL_test.py +++ b/fu/single/test/CompRTL_test.py @@ -6,19 +6,19 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * + +from pymtl3 import * # TODO: use `config_model_with_cmdline_opts` # from pymtl3.stdlib.test_utils import config_model_with_cmdline_opts -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * +from ..CompRTL import CompRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * -from ..CompRTL import CompRTL #------------------------------------------------------------------------- # Test harness diff --git a/fu/single/test/MemRTL_test.py b/fu/single/test/MemRTL_test.py index 5ab6f9c..dc9f36d 100644 --- a/fu/single/test/MemRTL_test.py +++ b/fu/single/test/MemRTL_test.py @@ -6,19 +6,19 @@ Author : Cheng Tan Date : November 27, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * + +from ..MemUnitRTL import MemUnitRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....mem.data.DataMemCL import DataMemCL +from ....mem.data.DataMemRTL import DataMemRTL -from ..MemUnitRTL import MemUnitRTL -from ....mem.data.DataMemRTL import DataMemRTL -from ....mem.data.DataMemCL import DataMemCL #------------------------------------------------------------------------- # Test harness diff --git a/fu/single/test/MulRTL_test.py b/fu/single/test/MulRTL_test.py index 9825a23..c3320e6 100644 --- a/fu/single/test/MulRTL_test.py +++ b/fu/single/test/MulRTL_test.py @@ -6,13 +6,13 @@ Author : Cheng Tan Date : November 27, 2019 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..AdderRTL import AdderRTL from ..ShifterRTL import ShifterRTL diff --git a/fu/single/test/PhiRTL_test.py b/fu/single/test/PhiRTL_test.py index e5d5fb0..215ad9b 100644 --- a/fu/single/test/PhiRTL_test.py +++ b/fu/single/test/PhiRTL_test.py @@ -6,17 +6,18 @@ Author : Cheng Tan Date : November 27, 2019 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..PhiRTL import PhiRTL from ....lib.opt_type import * from ....lib.messages import * + #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- diff --git a/fu/single/test/RetRTL_test.py b/fu/single/test/RetRTL_test.py index 8f6d185..5c0ee2b 100644 --- a/fu/single/test/RetRTL_test.py +++ b/fu/single/test/RetRTL_test.py @@ -6,18 +6,18 @@ Author : Cheng Tan Date : September 21, 2021 - """ from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..RetRTL import RetRTL from ....lib.opt_type import * from ....lib.messages import * + #------------------------------------------------------------------------- # Test harness #------------------------------------------------------------------------- diff --git a/fu/single/test/SelRTL_test.py b/fu/single/test/SelRTL_test.py index 0ffeb06..191f15e 100644 --- a/fu/single/test/SelRTL_test.py +++ b/fu/single/test/SelRTL_test.py @@ -6,13 +6,13 @@ Author : Cheng Tan Date : November 27, 2019 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ....lib.opt_type import * from ....lib.messages import * diff --git a/fu/single/translate/CompRTL_test.py b/fu/single/translate/CompRTL_test.py index 8b5c10c..ada301a 100644 --- a/fu/single/translate/CompRTL_test.py +++ b/fu/single/translate/CompRTL_test.py @@ -6,14 +6,16 @@ Author: Yanghui Ou Date: July 11, 2023 ''' + + from pymtl3 import * from pymtl3.passes.backends.verilog import VerilogTranslationPass from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) - from ..CompRTL import CompRTL -from ....lib.opt_type import * -from ....lib.messages import * +from ....lib.messages import * +from ....lib.opt_type import * + DataType = mk_data( 32, 1 ) PredicateType = mk_predicate( 1, 1 ) diff --git a/fu/triple/ThreeMulAdderShifterRTL.py b/fu/triple/ThreeMulAdderShifterRTL.py index 0e1ec71..5370898 100644 --- a/fu/triple/ThreeMulAdderShifterRTL.py +++ b/fu/triple/ThreeMulAdderShifterRTL.py @@ -6,17 +6,18 @@ Author : Cheng Tan Date : November 28, 2019 - """ -from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL + +from pymtl3 import * +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * from ..basic.ThreeCombo import ThreeCombo from ..single.MulRTL import MulRTL from ..single.AdderRTL import AdderRTL from ..single.ShifterRTL import ShifterRTL + class ThreeMulAdderShifterRTL( ThreeCombo ): def construct( s, DataType, PredicateType, CtrlType, diff --git a/fu/triple/test/ThreeMulAluShifterRTL_test.py b/fu/triple/test/ThreeMulAluShifterRTL_test.py index b3b175d..010b0fc 100644 --- a/fu/triple/test/ThreeMulAluShifterRTL_test.py +++ b/fu/triple/test/ThreeMulAluShifterRTL_test.py @@ -7,12 +7,12 @@ Author : Cheng Tan Date : November 29, 2019 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..ThreeMulAdderShifterRTL import ThreeMulAdderShifterRTL from ....lib.opt_type import * diff --git a/fu/vector/VectorAdderComboRTL.py b/fu/vector/VectorAdderComboRTL.py index d1e2573..a024a90 100644 --- a/fu/vector/VectorAdderComboRTL.py +++ b/fu/vector/VectorAdderComboRTL.py @@ -10,11 +10,11 @@ Author : Cheng Tan Date : March 28, 2022 - """ + from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from .VectorAdderRTL import VectorAdderRTL from ...lib.opt_type import * diff --git a/fu/vector/VectorAdderRTL.py b/fu/vector/VectorAdderRTL.py index a66588f..a0c8610 100644 --- a/fu/vector/VectorAdderRTL.py +++ b/fu/vector/VectorAdderRTL.py @@ -9,11 +9,11 @@ Author : Cheng Tan Date : March 27, 2022 - """ + from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * class VectorAdderRTL( Component ): diff --git a/fu/vector/VectorAllReduceRTL.py b/fu/vector/VectorAllReduceRTL.py index 9bbdabf..7b30e00 100644 --- a/fu/vector/VectorAllReduceRTL.py +++ b/fu/vector/VectorAllReduceRTL.py @@ -5,11 +5,11 @@ Author : Cheng Tan Date : April 23, 2022 - """ + from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * from ..basic.SumUnit import SumUnit from ..basic.ReduceMulUnit import ReduceMulUnit diff --git a/fu/vector/VectorMulComboRTL.py b/fu/vector/VectorMulComboRTL.py index 20acb3c..ea27fdc 100644 --- a/fu/vector/VectorMulComboRTL.py +++ b/fu/vector/VectorMulComboRTL.py @@ -8,11 +8,11 @@ Author : Cheng Tan Date : April 17, 2022 - """ + from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from .VectorMulRTL import VectorMulRTL from ...lib.opt_type import * from ..basic.SumUnit import SumUnit diff --git a/fu/vector/VectorMulRTL.py b/fu/vector/VectorMulRTL.py index 2324c36..e52d105 100644 --- a/fu/vector/VectorMulRTL.py +++ b/fu/vector/VectorMulRTL.py @@ -9,13 +9,14 @@ Author : Cheng Tan Date : APril 17, 2022 - """ + from pymtl3 import * -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * + class VectorMulRTL( Component ): def construct( s, bw, CtrlType, diff --git a/fu/vector/test/VectorAdderComboRTL_test.py b/fu/vector/test/VectorAdderComboRTL_test.py index 8787a37..195904e 100644 --- a/fu/vector/test/VectorAdderComboRTL_test.py +++ b/fu/vector/test/VectorAdderComboRTL_test.py @@ -6,12 +6,12 @@ Author : Cheng Tan Date : April 17, 2022 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..VectorAdderComboRTL import VectorAdderComboRTL from ....lib.opt_type import * diff --git a/fu/vector/test/VectorAdderRTL_test.py b/fu/vector/test/VectorAdderRTL_test.py index f24a5cf..096cb52 100644 --- a/fu/vector/test/VectorAdderRTL_test.py +++ b/fu/vector/test/VectorAdderRTL_test.py @@ -6,12 +6,12 @@ Author : Cheng Tan Date : March 13, 2022 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..VectorAdderRTL import VectorAdderRTL from ....mem.const.ConstQueueRTL import ConstQueueRTL diff --git a/fu/vector/test/VectorAllReduceRTL_test.py b/fu/vector/test/VectorAllReduceRTL_test.py index a397ea3..6fe86fb 100644 --- a/fu/vector/test/VectorAllReduceRTL_test.py +++ b/fu/vector/test/VectorAllReduceRTL_test.py @@ -6,12 +6,12 @@ Author : Cheng Tan Date : April 23, 2022 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..VectorAllReduceRTL import VectorAllReduceRTL from ....lib.opt_type import * diff --git a/fu/vector/test/VectorMulComboRTL_test.py b/fu/vector/test/VectorMulComboRTL_test.py index 718e121..ee78a9b 100644 --- a/fu/vector/test/VectorMulComboRTL_test.py +++ b/fu/vector/test/VectorMulComboRTL_test.py @@ -6,12 +6,11 @@ Author : Cheng Tan Date : April 17, 2022 - """ from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..VectorMulComboRTL import VectorMulComboRTL from ....lib.opt_type import * diff --git a/fu/vector/test/VectorMulRTL_test.py b/fu/vector/test/VectorMulRTL_test.py index f33577a..10b789d 100644 --- a/fu/vector/test/VectorMulRTL_test.py +++ b/fu/vector/test/VectorMulRTL_test.py @@ -6,12 +6,12 @@ Author : Cheng Tan Date : March 13, 2022 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL from ..VectorMulRTL import VectorMulRTL from ....mem.const.ConstQueueRTL import ConstQueueRTL diff --git a/fu/vector/translate/VectorAdderComboRTL_test.py b/fu/vector/translate/VectorAdderComboRTL_test.py index 79c6bca..dcfe036 100644 --- a/fu/vector/translate/VectorAdderComboRTL_test.py +++ b/fu/vector/translate/VectorAdderComboRTL_test.py @@ -6,6 +6,8 @@ Author: Yanghui Ou Date: July 11, 2023 ''' + + from pymtl3 import * from pymtl3.passes.backends.verilog import VerilogTranslationPass from pymtl3.stdlib.test_utils import (run_sim, diff --git a/fu/vector/translate/VectorMulComboRTL_test.py b/fu/vector/translate/VectorMulComboRTL_test.py index 5d0e2a3..88efb3c 100644 --- a/fu/vector/translate/VectorMulComboRTL_test.py +++ b/fu/vector/translate/VectorMulComboRTL_test.py @@ -6,6 +6,8 @@ Author: Yanghui Ou Date: July 11, 2023 ''' + + from pymtl3 import * from pymtl3.passes.backends.verilog import VerilogTranslationPass from pymtl3.stdlib.test_utils import (run_sim, diff --git a/lib/basic/__init__.py b/lib/basic/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/lib/ifcs.py b/lib/basic/en_rdy/ifcs.py similarity index 100% rename from lib/ifcs.py rename to lib/basic/en_rdy/ifcs.py diff --git a/lib/test_sinks.py b/lib/basic/en_rdy/test_sinks.py similarity index 100% rename from lib/test_sinks.py rename to lib/basic/en_rdy/test_sinks.py diff --git a/lib/test_srcs.py b/lib/basic/en_rdy/test_srcs.py similarity index 100% rename from lib/test_srcs.py rename to lib/basic/en_rdy/test_srcs.py diff --git a/lib/basic/val_rdy/SinkRTL.py b/lib/basic/val_rdy/SinkRTL.py new file mode 100644 index 0000000..2506868 --- /dev/null +++ b/lib/basic/val_rdy/SinkRTL.py @@ -0,0 +1,121 @@ +""" +======================================================================== +SinkRTL +======================================================================== +Test sinks with RTL interfaces. + +Author : Shunning Jiang + Date : Feb 12, 2021 +""" + +from pymtl3 import * +from .ifcs import RecvIfcRTL + + +class PyMTLTestSinkError( Exception ): pass + +#------------------------------------------------------------------------- +# TestSinkRTL +#------------------------------------------------------------------------- + +class SinkRTL( Component ): + + def construct( s, Type, msgs, initial_delay=0, interval_delay=0, + arrival_time=None, cmp_fn=lambda a, b : a == b ): + + # Interface + + s.recv = RecvIfcRTL( Type ) + + # Data + + # [msgs] and [arrival_time] must have the same length. + if arrival_time is None: + s.arrival_time = None + else: + assert len( msgs ) == len( arrival_time ) + s.arrival_time = list( arrival_time ) + + s.idx = 0 + s.count = 0 + s.cycle_count = 0 + s.msgs = list( msgs ) + + s.error_msg = '' + + s.received = False + s.all_msg_recved = False + s.done_flag = False + + @update_ff + def up_sink(): + # Raise exception at the start of next cycle so that the errored + # line trace gets printed out + if s.error_msg: + raise PyMTLTestSinkError( s.error_msg ) + + # Tick one more cycle after all message is received so that the + # exception gets thrown + if s.all_msg_recved: + s.done_flag = True + + if s.idx >= len(s.msgs): + s.all_msg_recved = True + + s.received = False + + if s.reset: + s.cycle_count = 0 + + s.idx = 0 + s.count = initial_delay + s.recv.rdy <<= (s.idx < len(s.msgs)) & (s.count == 0) + + else: + s.cycle_count += 1 + + # This means at least previous cycle count = 0 + if s.recv.val & s.recv.rdy: + msg = s.recv.msg + + # Sanity check + if s.idx >= len(s.msgs): + s.error_msg = ( 'Test Sink received more msgs than expected!\n' + f'Received : {msg}' ) + + else: + # Check correctness first + if not cmp_fn( msg, s.msgs[ s.idx ] ): + s.error_msg = ( + f'Test sink {s} received WRONG message!\n' + f'Expected : { s.msgs[ s.idx ] }\n' + f'Received : { msg }' + ) + + # Check timing if performance regeression is turned on + elif s.arrival_time and s.cycle_count > s.arrival_time[ s.idx ]: + s.error_msg = ( + f'Test sink {s} received message LATER than expected!\n' + f'Expected msg : {s.msgs[ s.idx ]}\n' + f'Expected at : {s.arrival_time[ s.idx ]}\n' + f'Received msg : {msg}\n' + f'Received at : {s.cycle_count}' + ) + + s.idx += 1 + s.count = interval_delay + + if s.count > 0: + s.count -= 1 + s.recv.rdy <<= 0 + else: # s.count == 0 + s.recv.rdy <<= (s.idx < len(s.msgs)) + + def done( s ): + return s.done_flag + + # Line trace + + def line_trace( s ): + return f"{s.recv}" + diff --git a/lib/basic/val_rdy/SourceRTL.py b/lib/basic/val_rdy/SourceRTL.py new file mode 100644 index 0000000..96695c7 --- /dev/null +++ b/lib/basic/val_rdy/SourceRTL.py @@ -0,0 +1,65 @@ +""" +======================================================================== +SourceRTL +======================================================================== +Test sources with RTL interfaces. + +Author : Shunning Jiang + Date : Feb 12, 2021 +""" + +from collections import deque +from copy import deepcopy + +from pymtl3 import * +from .ifcs import SendIfcRTL + + +class SourceRTL( Component ): + + def construct( s, Type, msgs, initial_delay=0, interval_delay=0 ): + + # Interface + + s.send = SendIfcRTL( Type ) + + # Data + + s.msgs = deepcopy(msgs) + + # TODO: use wires and ROM to make it translatable + s.idx = 0 + s.count = 0 + + @update_ff + def up_src(): + if s.reset: + s.idx = 0 + s.count = initial_delay + s.send.val <<= 0 + + else: + if s.send.val & s.send.rdy: + s.idx += 1 + s.count = interval_delay + + if s.count > 0: + s.count -= 1 + s.send.val <<= 0 + + else: # s.count == 0 + if s.idx < len(s.msgs): + s.send.val <<= 1 + s.send.msg <<= s.msgs[s.idx] + else: + s.send.val <<= 0 + + + def done( s ): + return s.idx >= len(s.msgs) + + # Line trace + + def line_trace( s ): + return f"{s.send}" + diff --git a/lib/basic/val_rdy/__init__.py b/lib/basic/val_rdy/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/lib/basic/val_rdy/ifcs.py b/lib/basic/val_rdy/ifcs.py new file mode 100644 index 0000000..0912b51 --- /dev/null +++ b/lib/basic/val_rdy/ifcs.py @@ -0,0 +1,61 @@ +""" +======================================================================== +ValRdyIfc +======================================================================== +RTL val/rdy interface. + +Author : Shunning Jiang + Date : Apr 5, 2019 +""" +from pymtl3 import * + + +def valrdy_to_str( msg, val, rdy, trace_len=15 ): + if val and not rdy: return "#".ljust( trace_len ) + if not val and rdy: return " ".ljust( trace_len ) + if not val and not rdy: return ".".ljust( trace_len ) + return f"{msg}".ljust( trace_len ) # val and rdy + +class RecvIfcRTL( Interface ): + + def construct( s, Type ): + + s.msg = InPort( Type ) + s.val = InPort() + s.rdy = OutPort() + + s.trace_len = len(str(Type())) + + def __str__( s ): + return valrdy_to_str( s.msg, s.val, s.rdy, s.trace_len ) + +class SendIfcRTL( Interface ): + + def construct( s, Type ): + + s.msg = OutPort( Type ) + s.val = OutPort() + s.rdy = InPort() + + s.trace_len = len(str(Type())) + + def __str__( s ): + return valrdy_to_str( s.msg, s.val, s.rdy, s.trace_len ) + +class MasterIfcRTL( Interface ): + def construct( s, ReqType, RespType ): + s.ReqType = ReqType + s.RespType = RespType + s.req = SendIfcRTL( Type=ReqType ) + s.resp = RecvIfcRTL( Type=RespType ) + def __str__( s ): + return f"{s.req}|{s.resp}" + +class MinionIfcRTL( Interface ): + def construct( s, ReqType, RespType ): + s.ReqType = ReqType + s.RespType = RespType + s.req = RecvIfcRTL( Type=ReqType ) + s.resp = SendIfcRTL( Type=RespType ) + def __str__( s ): + return f"{s.req}|{s.resp}" diff --git a/lib/basic/val_rdy/queues.py b/lib/basic/val_rdy/queues.py new file mode 100644 index 0000000..a15bd61 --- /dev/null +++ b/lib/basic/val_rdy/queues.py @@ -0,0 +1,556 @@ +""" +------------------------------------------------------------------------- +Library of RTL queues +------------------------------------------------------------------------- + +Author : Yanghui Ou + Date : Feb 22, 2021 +""" + + +from pymtl3 import * +from pymtl3.stdlib.primitive import Mux, RegisterFile + +from .ifcs import RecvIfcRTL, SendIfcRTL + +#------------------------------------------------------------------------- +# NormalQueue1EntryRTL +#------------------------------------------------------------------------- + +class NormalQueue1EntryRTL( Component ): + + def construct( s, EntryType ): + + # Interface + + s.recv = RecvIfcRTL( EntryType ) + s.send = SendIfcRTL( EntryType ) + s.count = OutPort() + + # Components + + s.full = Wire() + s.entry = Wire( EntryType ) + + # Logic + + s.count //= s.full + + s.send.msg //= s.entry + s.send.val //= s.full + s.recv.rdy //= lambda: ~s.full + + @update_ff + def ff_normal1(): + if s.reset: + s.full <<= 0 + else: + s.full <<= (s.recv.val & ~s.full) | (s.full & ~s.send.rdy) + + if s.recv.val & ~s.full: + s.entry <<= s.recv.msg + + def line_trace( s ): + return f"{s.recv}({s.full}){s.send}" + +#------------------------------------------------------------------------- +# Dpath and Ctrl for NormalQueueRTL +#------------------------------------------------------------------------- + +class NormalQueueDpathRTL( Component ): + + def construct( s, EntryType, num_entries=2 ): + assert num_entries >= 2 + + # Interface + + s.recv_msg = InPort( EntryType ) + s.send_msg = OutPort( EntryType ) + + s.wen = InPort() + s.waddr = InPort( clog2( num_entries ) ) + s.raddr = InPort( clog2( num_entries ) ) + + # Component + + s.rf = m = RegisterFile( EntryType, num_entries ) + m.raddr[0] //= s.raddr + m.rdata[0] //= s.send_msg + m.wen[0] //= s.wen + m.waddr[0] //= s.waddr + m.wdata[0] //= s.recv_msg + +class NormalQueueCtrlRTL( Component ): + + def construct( s, num_entries=2 ): + assert num_entries >= 2 + + # Constants + + addr_nbits = clog2( num_entries ) + count_nbits = clog2( num_entries+1 ) + + # Interface + + s.recv_val = InPort() + s.recv_rdy = OutPort() + s.send_val = OutPort() + s.send_rdy = InPort() + + s.count = OutPort( count_nbits ) + s.wen = OutPort() + s.waddr = OutPort( addr_nbits ) + s.raddr = OutPort( addr_nbits ) + + # Registers + + s.head = Wire( addr_nbits ) + s.tail = Wire( addr_nbits ) + + # Wires + + s.recv_xfer = Wire() + s.send_xfer = Wire() + + # Connections + + s.wen //= s.recv_xfer + s.waddr //= s.tail + s.raddr //= s.head + + s.recv_rdy //= lambda: s.count < num_entries + s.send_val //= lambda: s.count > 0 + + s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + s.send_xfer //= lambda: s.send_val & s.send_rdy + + @update_ff + def up_reg(): + + if s.reset: + s.head <<= 0 + s.tail <<= 0 + s.count <<= 0 + + else: + if s.recv_xfer: + s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + + if s.send_xfer: + s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + + if s.recv_xfer & ~s.send_xfer: + s.count <<= s.count + 1 + elif ~s.recv_xfer & s.send_xfer: + s.count <<= s.count - 1 + +#------------------------------------------------------------------------- +# NormalQueueRTL +#------------------------------------------------------------------------- + +class NormalQueueRTL( Component ): + + def construct( s, EntryType, num_entries=2 ): + + # Interface + + s.recv = RecvIfcRTL( EntryType ) + s.send = SendIfcRTL( EntryType ) + s.count = OutPort( clog2( num_entries+1 ) ) + + # Components + + assert num_entries > 0 + + if num_entries == 1: + s.q = NormalQueue1EntryRTL( EntryType ) + s.recv //= s.q.recv + s.send //= s.q.send + s.count //= s.q.count + + else: + s.ctrl = NormalQueueCtrlRTL ( num_entries ) + s.dpath = NormalQueueDpathRTL( EntryType, num_entries ) + + # Connect ctrl to data path + + s.ctrl.wen //= s.dpath.wen + s.ctrl.waddr //= s.dpath.waddr + s.ctrl.raddr //= s.dpath.raddr + + # Connect to interface + + s.recv.val //= s.ctrl.recv_val + s.recv.rdy //= s.ctrl.recv_rdy + s.recv.msg //= s.dpath.recv_msg + + s.send.val //= s.ctrl.send_val + s.send.rdy //= s.ctrl.send_rdy + s.send.msg //= s.dpath.send_msg + s.count //= s.ctrl.count + + # Line trace + + def line_trace( s ): + return f"{s.recv}({s.count}){s.send}" + +#------------------------------------------------------------------------- +# PipeQueue1EntryRTL +#------------------------------------------------------------------------- + +class PipeQueue1EntryRTL( Component ): + + def construct( s, EntryType ): + + # Interface + + s.recv = RecvIfcRTL( EntryType ) + s.send = SendIfcRTL( EntryType ) + s.count = OutPort() + + # Components + + s.full = Wire() + s.entry = Wire( EntryType ) + + # Logic + + s.count //= s.full + + s.send.msg //= s.entry + s.send.val //= s.full + + # If send is rdy, either the entry will be sent out to free up space + # for recv, or entry is already available for send. Then if not full + # entry can always buffer up a message. rdy path is elongated + s.recv.rdy //= lambda: s.send.rdy | ~s.full + + @update_ff + def ff_pipe1(): + if s.reset: + s.full <<= 0 + else: + # The pipe queue is full if in this cycle it cannot receive a + # message due to back pressure and the entry is already full. + # Otherwise it is not full and it becomes full only if there is + # a valid incoming message. + s.full <<= ~s.recv.rdy | s.recv.val + + # AND rdy and val to buffer the incoming message + if s.recv.rdy & s.recv.val: + s.entry <<= s.recv.msg + + def line_trace( s ): + return f"{s.recv}({s.full}){s.send}" + +#------------------------------------------------------------------------- +# Ctrl for PipeQueue +#------------------------------------------------------------------------- + +class PipeQueueCtrlRTL( Component ): + + def construct( s, num_entries=2 ): + assert num_entries >= 2 + + # Constants + + addr_nbits = clog2( num_entries ) + count_nbits = clog2( num_entries+1 ) + + # Interface + + s.recv_val = InPort () + s.recv_rdy = OutPort() + s.send_val = OutPort() + s.send_rdy = InPort () + s.count = OutPort( count_nbits ) + + s.wen = OutPort() + s.waddr = OutPort( addr_nbits ) + s.raddr = OutPort( addr_nbits ) + + # Registers + + s.head = Wire( addr_nbits ) + s.tail = Wire( addr_nbits ) + + # Wires + + s.recv_xfer = Wire() + s.send_xfer = Wire() + + # Connections + + s.wen //= s.recv_xfer + s.waddr //= s.tail + s.raddr //= s.head + + s.send_val //= lambda: s.count > 0 + s.recv_rdy //= lambda: ( s.count < num_entries ) | s.send_rdy + + s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + s.send_xfer //= lambda: s.send_val & s.send_rdy + + @update_ff + def up_reg(): + + if s.reset: + s.head <<= 0 + s.tail <<= 0 + s.count <<= 0 + + else: + if s.recv_xfer: + s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + + if s.send_xfer: + s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + + if s.recv_xfer & ~s.send_xfer: + s.count <<= s.count + 1 + elif ~s.recv_xfer & s.send_xfer: + s.count <<= s.count - 1 + +#------------------------------------------------------------------------- +# PipeQueueRTL +#------------------------------------------------------------------------- + +class PipeQueueRTL( Component ): + + def construct( s, EntryType, num_entries=2 ): + + # Interface + + s.recv = RecvIfcRTL( EntryType ) + s.send = SendIfcRTL( EntryType ) + s.count = OutPort( clog2( num_entries+1 ) ) + + # Components + + assert num_entries > 0 + if num_entries == 1: + s.q = PipeQueue1EntryRTL( EntryType ) + s.recv //= s.q.recv + s.send //= s.q.send + s.count //= s.q.count + + else: + s.ctrl = PipeQueueCtrlRTL ( num_entries ) + s.dpath = NormalQueueDpathRTL( EntryType, num_entries ) + + # Connect ctrl to data path + + s.ctrl.wen //= s.dpath.wen + s.ctrl.waddr //= s.dpath.waddr + s.ctrl.raddr //= s.dpath.raddr + + # Connect to interface + + s.recv.val //= s.ctrl.recv_val + s.recv.rdy //= s.ctrl.recv_rdy + s.send.val //= s.ctrl.send_val + s.send.rdy //= s.ctrl.send_rdy + s.count //= s.ctrl.count + s.recv.msg //= s.dpath.recv_msg + s.send.msg //= s.dpath.send_msg + + # Line trace + + def line_trace( s ): + return f"{s.recv}({s.count}){s.send}" + +#------------------------------------------------------------------------- +# BypassQueue1EntryRTL +#------------------------------------------------------------------------- + +class BypassQueue1EntryRTL( Component ): + + def construct( s, EntryType ): + + # Interface + + s.recv = RecvIfcRTL( EntryType ) + s.send = SendIfcRTL( EntryType ) + s.count = OutPort() + + # Components + + s.full = Wire() + s.entry = Wire( EntryType ) + + s.bypass_mux = m = Mux( EntryType, 2 ) + m.in_[0] //= s.recv.msg + m.in_[1] //= s.entry + m.out //= s.send.msg + m.sel //= s.full + + # Logic + + s.count //= s.full + + s.send.val //= lambda: s.full | s.recv.val + s.recv.rdy //= lambda: ~s.full + + @update_ff + def ff_bypass1(): + if s.reset: + s.full <<= 0 + else: + s.full <<= ~s.send.rdy & (s.full | s.recv.val) + + # buffer the incoming message if we cannot directly send it out + if ~s.send.rdy & ~s.full & s.recv.val: + s.entry <<= s.recv.msg + + def line_trace( s ): + return f"{s.recv}({s.full}){s.send}" +#------------------------------------------------------------------------- +# Ctrl and Dpath for BypassQueue +#------------------------------------------------------------------------- + +class BypassQueueDpathRTL( Component ): + + def construct( s, EntryType, num_entries=2 ): + assert num_entries >= 2 + + # Interface + + s.recv_msg = InPort( EntryType ) + s.send_msg = OutPort( EntryType ) + + s.wen = InPort() + s.waddr = InPort( clog2( num_entries ) ) + s.raddr = InPort( clog2( num_entries ) ) + s.mux_sel = InPort() + + # Component + + s.rf = m = RegisterFile( EntryType, num_entries ) + m.raddr[0] //= s.raddr + m.wen[0] //= s.wen + m.waddr[0] //= s.waddr + m.wdata[0] //= s.recv_msg + + s.mux = m = Mux( EntryType, 2 ) + m.sel //= s.mux_sel + m.in_[0] //= s.rf.rdata[0] + m.in_[1] //= s.recv_msg + m.out //= s.send_msg + +class BypassQueueCtrlRTL( Component ): + + def construct( s, num_entries=2 ): + assert num_entries >= 2 + + # Constants + + addr_nbits = clog2( num_entries ) + count_nbits = clog2( num_entries+1 ) + + last_idx = num_entries-1 + + # Interface + + s.recv_val = InPort () + s.recv_rdy = OutPort() + s.send_val = OutPort() + s.send_rdy = InPort() + s.count = OutPort( count_nbits ) + + s.wen = OutPort() + s.waddr = OutPort( addr_nbits ) + s.raddr = OutPort( addr_nbits ) + s.mux_sel = OutPort() + + # Registers + + s.head = Wire( addr_nbits ) + s.tail = Wire( addr_nbits ) + + # Wires + + s.recv_xfer = Wire() + s.send_xfer = Wire() + + # Connections + + s.wen //= s.recv_xfer + s.waddr //= s.tail + s.raddr //= s.head + + s.recv_rdy //= lambda: s.count < num_entries + s.send_val //= lambda: (s.count > 0) | s.recv_val + + s.mux_sel //= lambda: s.count == 0 + + s.recv_xfer //= lambda: s.recv_val & s.recv_rdy + s.send_xfer //= lambda: s.send_val & s.send_rdy + + @update_ff + def up_reg(): + + if s.reset: + s.head <<= 0 + s.tail <<= 0 + s.count <<= 0 + + else: + if s.recv_xfer: + s.tail <<= s.tail + 1 if ( s.tail < num_entries - 1 ) else 0 + + if s.send_xfer: + s.head <<= s.head + 1 if ( s.head < num_entries -1 ) else 0 + + if s.recv_xfer & ~s.send_xfer: + s.count <<= s.count + 1 + if ~s.recv_xfer & s.send_xfer: + s.count <<= s.count - 1 + +#------------------------------------------------------------------------- +# BypassQueueRTL +#------------------------------------------------------------------------- + +class BypassQueueRTL( Component ): + + def construct( s, EntryType, num_entries=2 ): + + # Interface + + s.recv = RecvIfcRTL( EntryType ) + s.send = SendIfcRTL( EntryType ) + s.count = OutPort( clog2( num_entries+1 ) ) + + # Components + + assert num_entries > 0 + if num_entries == 1: + s.q = BypassQueue1EntryRTL( EntryType ) + s.recv //= s.q.recv + s.send //= s.q.send + s.count //= s.q.count + + else: + s.ctrl = BypassQueueCtrlRTL ( num_entries ) + s.dpath = BypassQueueDpathRTL( EntryType, num_entries ) + + # Connect ctrl to data path + + s.ctrl.wen //= s.dpath.wen + s.ctrl.waddr //= s.dpath.waddr + s.ctrl.raddr //= s.dpath.raddr + s.ctrl.mux_sel //= s.dpath.mux_sel + + # Connect to interface + + s.recv.val //= s.ctrl.recv_val + s.recv.rdy //= s.ctrl.recv_rdy + s.send.val //= s.ctrl.send_val + s.send.rdy //= s.ctrl.send_rdy + s.count //= s.ctrl.count + s.recv.msg //= s.dpath.recv_msg + s.send.msg //= s.dpath.send_msg + + # Line trace + + def line_trace( s ): + return f"{s.recv}({s.count}){s.send}" diff --git a/lib/util/__init__.py b/lib/util/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/lib/common.py b/lib/util/common.py similarity index 100% rename from lib/common.py rename to lib/util/common.py diff --git a/lib/ctrl_helper.py b/lib/util/ctrl_helper.py similarity index 96% rename from lib/ctrl_helper.py rename to lib/util/ctrl_helper.py index aa6e8af..d6d2e0b 100644 --- a/lib/ctrl_helper.py +++ b/lib/util/ctrl_helper.py @@ -10,10 +10,10 @@ """ -from .messages import * -from .map_helper import * -from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from .map_helper import * +from ..messages import * +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL import json class TileCtrl: diff --git a/lib/dfg_helper.py b/lib/util/dfg_helper.py similarity index 99% rename from lib/dfg_helper.py rename to lib/util/dfg_helper.py index 0007bd5..ae9deb7 100644 --- a/lib/dfg_helper.py +++ b/lib/util/dfg_helper.py @@ -7,14 +7,14 @@ Author : Cheng Tan Date : Feb 14, 2020 - """ -from .messages import * -from .map_helper import * +from .map_helper import * +from ..messages import * import json + class Node: def __init__( s, id, FuType, opt, opt_predicate, const_index, input_node, diff --git a/lib/map_helper.py b/lib/util/map_helper.py similarity index 83% rename from lib/map_helper.py rename to lib/util/map_helper.py index c495e6d..de55b09 100644 --- a/lib/map_helper.py +++ b/lib/util/map_helper.py @@ -6,20 +6,21 @@ Author : Cheng Tan Date : Feb 22, 2020 - """ -from .opt_type import * -from ..fu.single.AdderRTL import AdderRTL -from ..fu.single.ShifterRTL import ShifterRTL -from ..fu.single.LogicRTL import LogicRTL -from ..fu.single.MulRTL import MulRTL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..fu.single.CompRTL import CompRTL -from ..fu.single.PhiRTL import PhiRTL -from ..fu.single.RetRTL import RetRTL -from ..fu.single.BranchRTL import BranchRTL -from ..fu.single.SelRTL import SelRTL + +from ..opt_type import * +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.RetRTL import RetRTL +from ...fu.single.SelRTL import SelRTL +from ...fu.single.ShifterRTL import ShifterRTL + # ----------------------------------------------------------------------- # Global dictionary for UnitType and OptType diff --git a/mem/const/ConstQueueRTL.py b/mem/const/ConstQueueRTL.py index 6c8cb6e..253b5ee 100644 --- a/mem/const/ConstQueueRTL.py +++ b/mem/const/ConstQueueRTL.py @@ -6,15 +6,15 @@ Author : Cheng Tan Date : Jan 20, 2020 - """ + from pymtl3 import * from pymtl3.stdlib.primitive import RegisterFile - -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * + class ConstQueueRTL( Component ): def construct( s, DataType, const_list=None ): diff --git a/mem/const/test/ConstQueueRTL_test.py b/mem/const/test/ConstQueueRTL_test.py index ca229ba..f468186 100644 --- a/mem/const/test/ConstQueueRTL_test.py +++ b/mem/const/test/ConstQueueRTL_test.py @@ -6,17 +6,17 @@ Author : Cheng Tan Date : Jan 20, 2020 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....fu.single.AdderRTL import AdderRTL -from ....lib.opt_type import * -from ....lib.messages import * -from ..ConstQueueRTL import ConstQueueRTL +from pymtl3 import * +from ..ConstQueueRTL import ConstQueueRTL +from ....fu.single.AdderRTL import AdderRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.opt_type import * +from ....lib.messages import * + #------------------------------------------------------------------------- # Test harness diff --git a/mem/ctrl/CtrlMemCL.py b/mem/ctrl/CtrlMemCL.py index 2d7a965..49579fb 100644 --- a/mem/ctrl/CtrlMemCL.py +++ b/mem/ctrl/CtrlMemCL.py @@ -6,15 +6,15 @@ Author : Cheng Tan Date : Dec 27, 2019 - """ -from pymtl3 import * -from pymtl3.stdlib.primitive import RegisterFile -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from pymtl3 import * +from pymtl3.stdlib.primitive import RegisterFile +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * + class CtrlMemCL( Component ): def construct( s, CtrlType, ctrl_mem_size, ctrl_count_per_iter = 4, diff --git a/mem/ctrl/CtrlMemRTL.py b/mem/ctrl/CtrlMemRTL.py index 44f5b72..644882f 100644 --- a/mem/ctrl/CtrlMemRTL.py +++ b/mem/ctrl/CtrlMemRTL.py @@ -6,15 +6,15 @@ Author : Cheng Tan Date : Dec 21, 2019 - """ -from pymtl3 import * -from pymtl3.stdlib.primitive import RegisterFile -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL +from pymtl3 import * +from pymtl3.stdlib.primitive import RegisterFile +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ...lib.opt_type import * + class CtrlMemRTL( Component ): def construct( s, CtrlType, ctrl_mem_size, ctrl_count_per_iter = 4, diff --git a/mem/ctrl/test/CtrlCL_test.py b/mem/ctrl/test/CtrlCL_test.py index ff63f01..3200c4c 100644 --- a/mem/ctrl/test/CtrlCL_test.py +++ b/mem/ctrl/test/CtrlCL_test.py @@ -6,17 +6,17 @@ Author : Cheng Tan Date : Dec 21, 2019 - """ + from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL +from ..CtrlMemCL import CtrlMemCL +from ....fu.single.AdderCL import AdderCL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.opt_type import * +from ....lib.messages import * -from ....fu.single.AdderCL import AdderCL -from ..CtrlMemCL import CtrlMemCL -from ....lib.opt_type import * -from ....lib.messages import * #------------------------------------------------------------------------- # Test harness diff --git a/mem/ctrl/test/CtrlRTL_AdderCL_test.py b/mem/ctrl/test/CtrlRTL_AdderCL_test.py index 2d68af0..2ac1bbc 100644 --- a/mem/ctrl/test/CtrlRTL_AdderCL_test.py +++ b/mem/ctrl/test/CtrlRTL_AdderCL_test.py @@ -6,18 +6,18 @@ Author : Cheng Tan Date : Dec 21, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....fu.single.AdderCL import AdderCL -from ..CtrlMemRTL import CtrlMemRTL -from ..CtrlMemCL import CtrlMemCL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..CtrlMemRTL import CtrlMemRTL +from ..CtrlMemCL import CtrlMemCL +from ....fu.single.AdderCL import AdderCL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/mem/ctrl/test/CtrlRTL_test.py b/mem/ctrl/test/CtrlRTL_test.py index 8caf4b8..049b62b 100644 --- a/mem/ctrl/test/CtrlRTL_test.py +++ b/mem/ctrl/test/CtrlRTL_test.py @@ -6,18 +6,18 @@ Author : Cheng Tan Date : Dec 21, 2019 - """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....fu.single.AdderRTL import AdderRTL -from ..CtrlMemRTL import CtrlMemRTL -from ..CtrlMemCL import CtrlMemCL -from ....lib.opt_type import * -from ....lib.messages import * +from pymtl3 import * +from ..CtrlMemCL import CtrlMemCL +from ..CtrlMemRTL import CtrlMemRTL +from ....fu.single.AdderRTL import AdderRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/mem/data/DataMemCL.py b/mem/data/DataMemCL.py index fc3d012..b06e4d2 100644 --- a/mem/data/DataMemCL.py +++ b/mem/data/DataMemCL.py @@ -6,13 +6,15 @@ Author : Cheng Tan Date : Dec 27, 2019 - """ + + from copy import deepcopy -from pymtl3 import * -from pymtl3.stdlib.primitive import RegisterFile -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * +from pymtl3 import * +from pymtl3.stdlib.primitive import RegisterFile +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class DataMemCL( Component ): diff --git a/mem/data/DataMemRTL.py b/mem/data/DataMemRTL.py index 9929cea..ac7bda0 100644 --- a/mem/data/DataMemRTL.py +++ b/mem/data/DataMemRTL.py @@ -3,15 +3,17 @@ DataMemRTL.py ========================================================================== Data memory for CGRA. + Author : Cheng Tan Date : Dec 20, 2019 """ -from pymtl3 import * -from pymtl3.stdlib.primitive import RegisterFile -from ...lib.ifcs import SendIfcRTL, RecvIfcRTL -from ...lib.opt_type import * +from pymtl3 import * +from pymtl3.stdlib.primitive import RegisterFile +from ...lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ...lib.opt_type import * + class DataMemRTL( Component ): diff --git a/mem/data/test/DataMemCL_test.py b/mem/data/test/DataMemCL_test.py index 0c7a338..1ab9456 100644 --- a/mem/data/test/DataMemCL_test.py +++ b/mem/data/test/DataMemCL_test.py @@ -3,17 +3,19 @@ DataMemCL_test.py ========================================================================== Test cases for DataMemCL. + Author : Cheng Tan Date : Nov 26, 2022 """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * -from ..DataMemCL import DataMemCL +from pymtl3 import * +from ..DataMemCL import DataMemCL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/noc/BlockChannelRTL.py b/noc/BlockChannelRTL.py index bf6d7c8..63d5b8d 100644 --- a/noc/BlockChannelRTL.py +++ b/noc/BlockChannelRTL.py @@ -9,7 +9,7 @@ from pymtl3 import * from pymtl3.stdlib.dstruct.queues import BypassQueue, NormalQueue -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL class BlockChannelRTL( Component ): diff --git a/noc/BypassChannelRTL.py b/noc/BypassChannelRTL.py index 3af70a4..9cf6aaa 100644 --- a/noc/BypassChannelRTL.py +++ b/noc/BypassChannelRTL.py @@ -7,9 +7,9 @@ # Author : Cheng Tan # Date : Feb 22, 2020 -from pymtl3 import * +from pymtl3 import * from pymtl3.stdlib.dstruct.queues import BypassQueue -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL class BypassChannelRTL( Component ): diff --git a/noc/ChannelNormalRTL.py b/noc/ChannelNormalRTL.py index 5f35b06..c2cc9e7 100644 --- a/noc/ChannelNormalRTL.py +++ b/noc/ChannelNormalRTL.py @@ -12,7 +12,8 @@ from pymtl3 import * from pymtl3.stdlib.dstruct.queues import NormalQueue -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL + class ChannelNormalRTL( Component ): def construct(s, DataType, latency = 1, num_entries = 2): diff --git a/noc/ChannelRTL.py b/noc/ChannelRTL.py index 9804cc0..18903d9 100644 --- a/noc/ChannelRTL.py +++ b/noc/ChannelRTL.py @@ -9,7 +9,7 @@ from pymtl3 import * from pymtl3.stdlib.dstruct.queues import BypassQueue, NormalQueue -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL class ChannelRTL( Component ): diff --git a/noc/CrossbarRTL.py b/noc/CrossbarRTL.py index ecac9d3..546bfcb 100644 --- a/noc/CrossbarRTL.py +++ b/noc/CrossbarRTL.py @@ -9,8 +9,7 @@ """ from pymtl3 import * - -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ..lib.opt_type import * class CrossbarRTL( Component ): diff --git a/noc/CrossbarSeparateRTL.py b/noc/CrossbarSeparateRTL.py index 376d691..10aefc9 100644 --- a/noc/CrossbarSeparateRTL.py +++ b/noc/CrossbarSeparateRTL.py @@ -10,7 +10,7 @@ """ from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ..lib.opt_type import * class CrossbarSeparateRTL(Component): diff --git a/noc/DelayChannelRTL.py b/noc/DelayChannelRTL.py index f78aac4..b6dc88f 100644 --- a/noc/DelayChannelRTL.py +++ b/noc/DelayChannelRTL.py @@ -11,8 +11,7 @@ from pymtl3 import * from pymtl3.stdlib.dstruct.queues import BypassQueue, NormalQueue -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL - +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL class DelayChannelRTL( Component ): def construct(s, DataType, delay = 5 ): diff --git a/noc/LinkOrRTL.py b/noc/LinkOrRTL.py index 9fc45e8..a269ed9 100644 --- a/noc/LinkOrRTL.py +++ b/noc/LinkOrRTL.py @@ -11,7 +11,7 @@ # Date : April 19, 2024 from pymtl3 import * -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL class LinkOrRTL(Component): diff --git a/noc/MulticasterRTL.py b/noc/MulticasterRTL.py index 1bf2ba3..4fb5c5a 100644 --- a/noc/MulticasterRTL.py +++ b/noc/MulticasterRTL.py @@ -9,7 +9,7 @@ from pymtl3 import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ..lib.opt_type import * class MulticasterRTL( Component ): diff --git a/noc/test/BlockChannelRTL_test.py b/noc/test/BlockChannelRTL_test.py index b78c97d..fbdfaf3 100644 --- a/noc/test/BlockChannelRTL_test.py +++ b/noc/test/BlockChannelRTL_test.py @@ -10,8 +10,8 @@ from pymtl3 import * from pymtl3.stdlib.test_utils import TestVectorSimulator -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL from ...lib.messages import * from ..BlockChannelRTL import BlockChannelRTL diff --git a/noc/test/ChannelNormalRTL_test.py b/noc/test/ChannelNormalRTL_test.py index 37d1d12..93bcaef 100644 --- a/noc/test/ChannelNormalRTL_test.py +++ b/noc/test/ChannelNormalRTL_test.py @@ -11,8 +11,8 @@ from pymtl3 import * from pymtl3.stdlib.test_utils import TestVectorSimulator -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL from ...lib.messages import * from ..ChannelNormalRTL import ChannelNormalRTL diff --git a/noc/test/ChannelRTL_test.py b/noc/test/ChannelRTL_test.py index 53a59c1..6241d4e 100644 --- a/noc/test/ChannelRTL_test.py +++ b/noc/test/ChannelRTL_test.py @@ -10,8 +10,8 @@ from pymtl3 import * from pymtl3.stdlib.test_utils import TestVectorSimulator -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL from ...lib.messages import * from ..ChannelRTL import ChannelRTL diff --git a/noc/test/CrossbarBlockRTL_test.py b/noc/test/CrossbarBlockRTL_test.py index 645ad8a..2ed94f7 100644 --- a/noc/test/CrossbarBlockRTL_test.py +++ b/noc/test/CrossbarBlockRTL_test.py @@ -10,8 +10,8 @@ """ from pymtl3 import * -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL from ..CrossbarRTL import CrossbarRTL from ..BlockChannelRTL import BlockChannelRTL diff --git a/noc/test/CrossbarDelayRTL_test.py b/noc/test/CrossbarDelayRTL_test.py index d85ca1c..9086614 100644 --- a/noc/test/CrossbarDelayRTL_test.py +++ b/noc/test/CrossbarDelayRTL_test.py @@ -14,13 +14,13 @@ """ from pymtl3 import * -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL -from ..CrossbarRTL import CrossbarRTL +from ..CrossbarRTL import CrossbarRTL from ..DelayChannelRTL import DelayChannelRTL -from ...lib.opt_type import * -from ...lib.messages import * +from ...lib.opt_type import * +from ...lib.messages import * #------------------------------------------------------------------------- # Test harness diff --git a/noc/test/CrossbarRTL_test.py b/noc/test/CrossbarRTL_test.py index da40027..23938e0 100644 --- a/noc/test/CrossbarRTL_test.py +++ b/noc/test/CrossbarRTL_test.py @@ -10,8 +10,8 @@ """ from pymtl3 import * -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL from ..CrossbarRTL import CrossbarRTL from ...lib.opt_type import * diff --git a/noc/test/LinkOrRTL_test.py b/noc/test/LinkOrRTL_test.py index 0c785c3..8d919f0 100644 --- a/noc/test/LinkOrRTL_test.py +++ b/noc/test/LinkOrRTL_test.py @@ -7,13 +7,12 @@ # Date : April 19, 2024 import pytest -from pymtl3 import * +from pymtl3 import * from pymtl3.stdlib.test_utils import TestVectorSimulator - -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.messages import * from ..LinkOrRTL import LinkOrRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * #------------------------------------------------------------------------- # TestHarness diff --git a/noc/test/Multicaster_test.py b/noc/test/Multicaster_test.py index 1fb4603..394dd09 100644 --- a/noc/test/Multicaster_test.py +++ b/noc/test/Multicaster_test.py @@ -10,12 +10,11 @@ """ from pymtl3 import * - -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ..MulticasterRTL import MulticasterRTL +from ..MulticasterRTL import MulticasterRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.opt_type import * +from ...lib.messages import * #------------------------------------------------------------------------- # Test harness diff --git a/rf/RegFile.py b/rf/RegFile.py index 8ff8648..89e37f8 100644 --- a/rf/RegFile.py +++ b/rf/RegFile.py @@ -6,14 +6,14 @@ Author : Cheng Tan Date : Dec 10, 2019 - """ -from pymtl3 import * + +from pymtl3 import * from pymtl3.stdlib.primitive import RegisterFile +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..lib.opt_type import * class RegFile( Component ): diff --git a/rf/RegisterRTL.py b/rf/RegisterRTL.py index 9ed86fc..d6f2e1f 100644 --- a/rf/RegisterRTL.py +++ b/rf/RegisterRTL.py @@ -1,18 +1,21 @@ -#========================================================================= -# RegisterRTL.py -#========================================================================= -# RTL register module specifically for predication. -# -# Author : Cheng Tan -# Date : Aug 22, 2021 - -from pymtl3 import * -from pymtl3.stdlib.dstruct.queues import NormalQueue +''' +========================================================================= +RegisterRTL.py +========================================================================= +RTL register module specifically for predication. + +Author : Cheng Tan + Date : Aug 22, 2021 +''' -from ..lib.ifcs import RecvIfcRTL, SendIfcRTL + +from pymtl3 import * +from pymtl3.stdlib.dstruct.queues import NormalQueue +from ..lib.basic.en_rdy.ifcs import RecvIfcRTL, SendIfcRTL class RegisterRTL( Component ): + def construct(s, DataType, latency = 1 ): # Constant diff --git a/rf/test/RegFile_test.py b/rf/test/RegFile_test.py index b4df09e..14eabb1 100644 --- a/rf/test/RegFile_test.py +++ b/rf/test/RegFile_test.py @@ -6,16 +6,16 @@ Author : Cheng Tan Date : November 27, 2019 - """ + from pymtl3 import * +from ..RegFile import RegFile +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ..RegFile import RegFile #------------------------------------------------------------------------- # Test harness diff --git a/rf/test/RegisterRTL_test.py b/rf/test/RegisterRTL_test.py index c1c6849..0b845d9 100644 --- a/rf/test/RegisterRTL_test.py +++ b/rf/test/RegisterRTL_test.py @@ -1,19 +1,22 @@ -#========================================================================= -# ChannelRTL_test.py -#========================================================================= -# Simple test for Channel -# -# Author : Cheng Tan -# Date : Dec 11, 2019 +''' +========================================================================= +ChannelRTL_test.py +========================================================================= +Simple test for Channel + +Author : Cheng Tan + Date : Dec 11, 2019 +''' + import pytest from pymtl3 import * from pymtl3.stdlib.test_utils import TestVectorSimulator +from ..RegisterRTL import RegisterRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.messages import * -from ..RegisterRTL import RegisterRTL #------------------------------------------------------------------------- # TestHarness diff --git a/systolic/SystolicCL.py b/systolic/SystolicCL.py index df29fb4..4600171 100644 --- a/systolic/SystolicCL.py +++ b/systolic/SystolicCL.py @@ -7,13 +7,15 @@ Date : May 24, 2020 """ -from pymtl3 import * -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..tile.TileCL import TileCL -from ..lib.opt_type import * -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..mem.data.DataMemCL import DataMemCL + +from pymtl3 import * +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.opt_type import * +from ..mem.data.DataMemCL import DataMemCL +from ..noc.CrossbarRTL import CrossbarRTL +from ..noc.ChannelRTL import ChannelRTL +from ..tile.TileCL import TileCL + class SystolicCL( Component ): diff --git a/systolic/test/SystolicCL_test.py b/systolic/test/SystolicCL_test.py index 366b52e..36eecf3 100644 --- a/systolic/test/SystolicCL_test.py +++ b/systolic/test/SystolicCL_test.py @@ -6,25 +6,23 @@ Author : Cheng Tan Date : Dec 28, 2019 - """ -from pymtl3 import * - -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ...lib.ctrl_helper import * +from pymtl3 import * +from ..SystolicCL import SystolicCL +from ...fu.double.SeqMulAdderRTL import SeqMulAdderRTL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.double.SeqMulAdderRTL import SeqMulAdderRTL -from ..SystolicCL import SystolicCL - +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * +from ...lib.util.ctrl_helper import * import os + kMaxCycles = 6 #------------------------------------------------------------------------- diff --git a/tile/TileCL.py b/tile/TileCL.py index bae693a..13c4b00 100644 --- a/tile/TileCL.py +++ b/tile/TileCL.py @@ -7,15 +7,17 @@ Date : Dec 28, 2019 """ -from pymtl3 import * + +from pymtl3 import * from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ..fu.single.MemUnitRTL import MemUnitRTL -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..mem.ctrl.CtrlMemCL import CtrlMemCL -from ..mem.const.ConstQueueRTL import ConstQueueRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..rf.RegisterRTL import RegisterRTL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..mem.ctrl.CtrlMemCL import CtrlMemCL +from ..mem.const.ConstQueueRTL import ConstQueueRTL +from ..noc.ChannelRTL import ChannelRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..rf.RegisterRTL import RegisterRTL + class TileCL( Component ): diff --git a/tile/TileRTL.py b/tile/TileRTL.py index cc5bc26..dd68900 100644 --- a/tile/TileRTL.py +++ b/tile/TileRTL.py @@ -2,27 +2,29 @@ ========================================================================= TileRTL.py ========================================================================= + Author : Cheng Tan Date : Dec 11, 2019 """ -from pymtl3 import * -from ..fu.single.MemUnitRTL import MemUnitRTL +from pymtl3 import * from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ..fu.single.AdderRTL import AdderRTL -from ..fu.single.PhiRTL import PhiRTL -from ..fu.single.CompRTL import CompRTL -from ..fu.single.MulRTL import MulRTL -from ..fu.single.BranchRTL import BranchRTL -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL -from ..mem.const.ConstQueueRTL import ConstQueueRTL -from ..mem.ctrl.CtrlMemRTL import CtrlMemRTL -from ..noc.CrossbarRTL import CrossbarRTL -from ..noc.ChannelRTL import ChannelRTL -from ..rf.RegisterRTL import RegisterRTL +from ..fu.single.AdderRTL import AdderRTL +from ..fu.single.BranchRTL import BranchRTL +from ..fu.single.CompRTL import CompRTL +from ..fu.single.MemUnitRTL import MemUnitRTL +from ..fu.single.MulRTL import MulRTL +from ..fu.single.PhiRTL import PhiRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL +from ..mem.const.ConstQueueRTL import ConstQueueRTL +from ..mem.ctrl.CtrlMemRTL import CtrlMemRTL +from ..noc.CrossbarRTL import CrossbarRTL +from ..noc.ChannelRTL import ChannelRTL +from ..rf.RegisterRTL import RegisterRTL # from ..noc.BypassChannelRTL import BypassChannelRTL + class TileRTL( Component ): def construct( s, DataType, PredicateType, CtrlType, diff --git a/tile/TileSeparateCrossbarRTL.py b/tile/TileSeparateCrossbarRTL.py index 193ad79..4dff881 100644 --- a/tile/TileSeparateCrossbarRTL.py +++ b/tile/TileSeparateCrossbarRTL.py @@ -14,16 +14,17 @@ Date : Nov 26, 2024 """ + from pymtl3 import * -from ..fu.single.MemUnitRTL import MemUnitRTL from ..fu.flexible.FlexibleFuRTL import FlexibleFuRTL from ..fu.single.AdderRTL import AdderRTL +from ..fu.single.BranchRTL import BranchRTL from ..fu.single.PhiRTL import PhiRTL from ..fu.single.CompRTL import CompRTL +from ..fu.single.MemUnitRTL import MemUnitRTL from ..fu.single.MulRTL import MulRTL -from ..fu.single.BranchRTL import BranchRTL -from ..lib.ifcs import SendIfcRTL, RecvIfcRTL +from ..lib.basic.en_rdy.ifcs import SendIfcRTL, RecvIfcRTL from ..mem.const.ConstQueueRTL import ConstQueueRTL from ..mem.ctrl.CtrlMemRTL import CtrlMemRTL from ..noc.CrossbarSeparateRTL import CrossbarSeparateRTL diff --git a/tile/test/TileCL_test.py b/tile/test/TileCL_test.py index 14c5e65..4538b98 100644 --- a/tile/test/TileCL_test.py +++ b/tile/test/TileCL_test.py @@ -6,21 +6,21 @@ Author : Cheng Tan Date : Dec 28, 2019 - """ -from pymtl3 import * -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL +from pymtl3 import * +from ..TileCL import TileCL +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL from ...fu.triple.ThreeMulAdderShifterRTL import ThreeMulAdderShifterRTL -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...mem.ctrl.CtrlMemCL import CtrlMemCL -from ..TileCL import TileCL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * +from ...mem.ctrl.CtrlMemCL import CtrlMemCL + #------------------------------------------------------------------------- # Test harness diff --git a/tile/test/TileRTL_test.py b/tile/test/TileRTL_test.py index 8461d99..f165bc6 100644 --- a/tile/test/TileRTL_test.py +++ b/tile/test/TileRTL_test.py @@ -8,27 +8,26 @@ Author : Cheng Tan Date : Dec 11, 2019 - """ -from pymtl3 import * - -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) -from pymtl3.passes.backends.verilog import (VerilogTranslationPass, - VerilogVerilatorImportPass) -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.MemUnitRTL import MemUnitRTL +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) +from pymtl3.passes.backends.verilog import (VerilogTranslationPass, + VerilogVerilatorImportPass) +from ..TileRTL import TileRTL +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.MulRTL import MulRTL from ...fu.triple.ThreeMulAdderShifterRTL import ThreeMulAdderShifterRTL -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...mem.ctrl.CtrlMemRTL import CtrlMemRTL -from ..TileRTL import TileRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * +from ...mem.ctrl.CtrlMemRTL import CtrlMemRTL + #------------------------------------------------------------------------- # Test harness diff --git a/tile/test/TileSeparateCrossbarRTL_test.py b/tile/test/TileSeparateCrossbarRTL_test.py index 4a0bbbe..75dfeb2 100644 --- a/tile/test/TileSeparateCrossbarRTL_test.py +++ b/tile/test/TileSeparateCrossbarRTL_test.py @@ -8,25 +8,26 @@ Author : Cheng Tan Date : Nov 26, 2024 - """ + from pymtl3 import * from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) from pymtl3.passes.backends.verilog import (VerilogTranslationPass, VerilogVerilatorImportPass) -from ...lib.test_sinks import TestSinkRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * +from ..TileSeparateCrossbarRTL import TileSeparateCrossbarRTL from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MulRTL import MulRTL from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.MulRTL import MulRTL from ...fu.triple.ThreeMulAdderShifterRTL import ThreeMulAdderShifterRTL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * from ...mem.ctrl.CtrlMemRTL import CtrlMemRTL -from ..TileSeparateCrossbarRTL import TileSeparateCrossbarRTL + #------------------------------------------------------------------------- # Test harness diff --git a/tile/translate/TileRTL_test.py b/tile/translate/TileRTL_test.py index 43cf02f..a89fc19 100644 --- a/tile/translate/TileRTL_test.py +++ b/tile/translate/TileRTL_test.py @@ -6,29 +6,30 @@ Author: Yanghui Ou Date: July 11, 2023 ''' + + from pymtl3 import * from pymtl3.passes.backends.verilog import VerilogTranslationPass from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) - -from ...lib.opt_type import * -from ...lib.messages import * +from ..TileRTL import TileRTL +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.float.FpAddRTL import FpAddRTL +from ...fu.float.FpMulRTL import FpMulRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.SelRTL import SelRTL +from ...fu.single.ShifterRTL import ShifterRTL from ...fu.triple.ThreeMulAdderShifterRTL import ThreeMulAdderShifterRTL -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.SelRTL import SelRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.LogicRTL import LogicRTL -from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL -from ...fu.single.BranchRTL import BranchRTL -from ...fu.float.FpAddRTL import FpAddRTL -from ...fu.float.FpMulRTL import FpMulRTL -from ...fu.triple.ThreeMulAdderShifterRTL import ThreeMulAdderShifterRTL -from ...mem.ctrl.CtrlMemRTL import CtrlMemRTL -from ..TileRTL import TileRTL +from ...lib.messages import * +from ...lib.opt_type import * +from ...mem.ctrl.CtrlMemRTL import CtrlMemRTL + num_connect_inports = 4 num_connect_outports = 4 From cc7d0fd48f3b78906d3c69256ea7c814a44ffc3d Mon Sep 17 00:00:00 2001 From: tancheng Date: Sun, 1 Dec 2024 08:00:27 +0000 Subject: [PATCH 2/7] [fix] tests and include PyOCN as sub-module --- .gitmodules | 3 ++ .../CGRAMemBottomRTL_matmul_2x2_test.py | 23 +++++++------ ...GRAMemRightAndBottomRTL_matmul_2x2_test.py | 23 +++++++------ .../translate/CGRASeparateCrossbarRTL_test.py | 5 +-- cgra/translate/CGRATemplateRTL_test.py | 34 +++++++++---------- cgra/translate/VectorCGRAKingMeshRTL_test.py | 33 +++++++++--------- fu/float/test/FpMulRTL_test.py | 20 +++++------ mem/data/test/DataMemRTL_test.py | 14 ++++---- noc/PyOCN | 1 + 9 files changed, 82 insertions(+), 74 deletions(-) create mode 160000 noc/PyOCN diff --git a/.gitmodules b/.gitmodules index c19000d..5801b0b 100644 --- a/.gitmodules +++ b/.gitmodules @@ -4,3 +4,6 @@ [submodule "fu/dp_fpfma"] path = fu/dp_fpfma url = https://github.com/tancheng/dp_fpfma +[submodule "noc/PyOCN"] + path = noc/PyOCN + url = https://github.com/tancheng/PyOCN diff --git a/cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py b/cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py index a1bc3d1..f1d510e 100644 --- a/cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py +++ b/cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py @@ -8,27 +8,28 @@ Date : Oct 14, 2024 """ + from pymtl3 import * from pymtl3.passes.backends.verilog import VerilogTranslationPass from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.test_sinks import TestSinkRTL -from ...lib.opt_type import * -from ...lib.messages import * +from ..CGRAMemBottomRTL import CGRAMemBottomRTL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL from ...fu.single.MemUnitRTL import MemUnitRTL from ...fu.single.MulRTL import MulRTL -from ...fu.single.SelRTL import SelRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.LogicRTL import LogicRTL from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL +from ...fu.single.SelRTL import SelRTL from ...fu.double.SeqMulAdderRTL import SeqMulAdderRTL -from ...fu.single.BranchRTL import BranchRTL -from ..CGRAMemBottomRTL import CGRAMemBottomRTL +from ...fu.single.ShifterRTL import ShifterRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.messages import * +from ...lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py b/cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py index 2a96527..7ad2000 100644 --- a/cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py +++ b/cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py @@ -8,27 +8,28 @@ Date : Nov 19, 2024 """ + from pymtl3 import * from pymtl3.passes.backends.verilog import VerilogTranslationPass from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.test_sinks import TestSinkRTL -from ...lib.opt_type import * -from ...lib.messages import * +from ..CGRAMemRightAndBottomRTL import CGRAMemRightAndBottomRTL from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL from ...fu.single.MemUnitRTL import MemUnitRTL from ...fu.single.MulRTL import MulRTL -from ...fu.single.SelRTL import SelRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.LogicRTL import LogicRTL from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL +from ...fu.single.SelRTL import SelRTL from ...fu.double.SeqMulAdderRTL import SeqMulAdderRTL -from ...fu.single.BranchRTL import BranchRTL -from ..CGRAMemRightAndBottomRTL import CGRAMemRightAndBottomRTL +from ...fu.single.ShifterRTL import ShifterRTL +from ...lib.basic.en_rdy.test_sinks import TestSinkRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/cgra/translate/CGRASeparateCrossbarRTL_test.py b/cgra/translate/CGRASeparateCrossbarRTL_test.py index 2bfa35e..ad00c6c 100644 --- a/cgra/translate/CGRASeparateCrossbarRTL_test.py +++ b/cgra/translate/CGRASeparateCrossbarRTL_test.py @@ -6,9 +6,9 @@ Author : Cheng Tan Date : Nov 29, 2024 - """ + from pymtl3 import * from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) @@ -19,9 +19,10 @@ from ...fu.single.AdderRTL import AdderRTL from ...fu.single.MemUnitRTL import MemUnitRTL from ...fu.single.ShifterRTL import ShifterRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL from ...lib.messages import * from ...lib.opt_type import * -from ...lib.test_srcs import TestSrcRTL + #------------------------------------------------------------------------- # Test harness diff --git a/cgra/translate/CGRATemplateRTL_test.py b/cgra/translate/CGRATemplateRTL_test.py index f634f65..430d14f 100644 --- a/cgra/translate/CGRATemplateRTL_test.py +++ b/cgra/translate/CGRATemplateRTL_test.py @@ -14,24 +14,24 @@ VerilogVerilatorImportPass) from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) +from ..CGRATemplateRTL import CGRATemplateRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * +from ...lib.util.common import * +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.RetRTL import RetRTL +from ...fu.single.SelRTL import SelRTL +from ...fu.double.SeqMulAdderRTL import SeqMulAdderRTL +from ...fu.single.ShifterRTL import ShifterRTL -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ...lib.common import * -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.SelRTL import SelRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.LogicRTL import LogicRTL -from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL -from ...fu.single.BranchRTL import BranchRTL -from ...fu.single.RetRTL import RetRTL -from ...fu.double.SeqMulAdderRTL import SeqMulAdderRTL -from ..CGRATemplateRTL import CGRATemplateRTL fuType2RTL = {} fuType2RTL["Phi" ] = PhiRTL diff --git a/cgra/translate/VectorCGRAKingMeshRTL_test.py b/cgra/translate/VectorCGRAKingMeshRTL_test.py index c899276..f6826de 100644 --- a/cgra/translate/VectorCGRAKingMeshRTL_test.py +++ b/cgra/translate/VectorCGRAKingMeshRTL_test.py @@ -6,32 +6,31 @@ Author : Cheng Tan Date : April 1, 2023 - """ + from pymtl3 import * from pymtl3.passes.backends.verilog import (VerilogTranslationPass, VerilogVerilatorImportPass) from pymtl3.stdlib.test_utils import (run_sim, config_model_with_cmdline_opts) - -from ...lib.test_srcs import TestSrcRTL -from ...lib.opt_type import * -from ...lib.messages import * -from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL -from ...fu.single.AdderRTL import AdderRTL -from ...fu.single.MemUnitRTL import MemUnitRTL -from ...fu.single.MulRTL import MulRTL -from ...fu.single.SelRTL import SelRTL -from ...fu.single.ShifterRTL import ShifterRTL -from ...fu.single.LogicRTL import LogicRTL -from ...fu.single.PhiRTL import PhiRTL -from ...fu.single.CompRTL import CompRTL -from ...fu.single.BranchRTL import BranchRTL -from ...fu.vector.VectorMulComboRTL import VectorMulComboRTL +from ..CGRAKingMeshRTL import CGRAKingMeshRTL +from ...fu.flexible.FlexibleFuRTL import FlexibleFuRTL +from ...fu.single.AdderRTL import AdderRTL +from ...fu.single.BranchRTL import BranchRTL +from ...fu.single.CompRTL import CompRTL +from ...fu.single.LogicRTL import LogicRTL +from ...fu.single.MemUnitRTL import MemUnitRTL +from ...fu.single.MulRTL import MulRTL +from ...fu.single.PhiRTL import PhiRTL +from ...fu.single.SelRTL import SelRTL +from ...fu.single.ShifterRTL import ShifterRTL from ...fu.vector.VectorAdderComboRTL import VectorAdderComboRTL +from ...fu.vector.VectorMulComboRTL import VectorMulComboRTL +from ...lib.basic.en_rdy.test_srcs import TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * -from ..CGRAKingMeshRTL import CGRAKingMeshRTL #------------------------------------------------------------------------- # Test harness diff --git a/fu/float/test/FpMulRTL_test.py b/fu/float/test/FpMulRTL_test.py index 72c4122..ad65198 100644 --- a/fu/float/test/FpMulRTL_test.py +++ b/fu/float/test/FpMulRTL_test.py @@ -6,21 +6,21 @@ Author : Cheng Tan Date : August 10, 2023 - """ -from pymtl3 import * -from pymtl3.stdlib.test_utils import (run_sim, - config_model_with_cmdline_opts) -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * -from ....mem.const.ConstQueueRTL import ConstQueueRTL -from ..FpMulRTL import FpMulRTL +from pymtl3 import * +from pymtl3.stdlib.test_utils import (run_sim, + config_model_with_cmdline_opts) +from ..FpMulRTL import FpMulRTL from ...pymtl3_hardfloat.HardFloat.converter_funcs import (floatToFN, fNToFloat) +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * +from ....mem.const.ConstQueueRTL import ConstQueueRTL + round_near_even = 0b000 diff --git a/mem/data/test/DataMemRTL_test.py b/mem/data/test/DataMemRTL_test.py index 3ceb272..8e8ba63 100644 --- a/mem/data/test/DataMemRTL_test.py +++ b/mem/data/test/DataMemRTL_test.py @@ -3,17 +3,19 @@ DataMemRTL_test.py ========================================================================== Test cases for DataMemRTL. + Author : Cheng Tan Date : Nov 26, 2022 """ -from pymtl3 import * -from ....lib.test_sinks import TestSinkRTL -from ....lib.test_srcs import TestSrcRTL -from ....lib.opt_type import * -from ....lib.messages import * -from ..DataMemRTL import DataMemRTL +from pymtl3 import * +from ..DataMemRTL import DataMemRTL +from ....lib.basic.en_rdy.test_sinks import TestSinkRTL +from ....lib.basic.en_rdy.test_srcs import TestSrcRTL +from ....lib.messages import * +from ....lib.opt_type import * + #------------------------------------------------------------------------- # Test harness diff --git a/noc/PyOCN b/noc/PyOCN new file mode 160000 index 0000000..b55a160 --- /dev/null +++ b/noc/PyOCN @@ -0,0 +1 @@ +Subproject commit b55a16069e290132acf1e30ccf99bc94c2b567cb From 62c068663fe9e85c99a4d6455859238b873d292f Mon Sep 17 00:00:00 2001 From: tancheng Date: Sun, 1 Dec 2024 08:09:08 +0000 Subject: [PATCH 3/7] [refactor] Ignore tests in PyOCN for now until the porting is done --- pytest.ini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pytest.ini b/pytest.ini index 514d502..ec35475 100644 --- a/pytest.ini +++ b/pytest.ini @@ -26,4 +26,4 @@ python_functions = test test_* # error/warnings at the end; otherwise syntax errors won't really show # up. -addopts = --tb=no -r Ew +addopts = --tb=no -r Ew --ignore=noc/PyOCN From 6f970ba93217cfe9aa251dd4f883e22936118259 Mon Sep 17 00:00:00 2001 From: tancheng Date: Sun, 1 Dec 2024 08:12:50 +0000 Subject: [PATCH 4/7] [refactor] Try ignore again --- pytest.ini | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pytest.ini b/pytest.ini index ec35475..fc34c7a 100644 --- a/pytest.ini +++ b/pytest.ini @@ -26,4 +26,4 @@ python_functions = test test_* # error/warnings at the end; otherwise syntax errors won't really show # up. -addopts = --tb=no -r Ew --ignore=noc/PyOCN +addopts = --tb=no -r Ew --ignore=../noc/PyOCN From 038b12ab5af9da0f541a661e68d5cc2fcd81fca1 Mon Sep 17 00:00:00 2001 From: tancheng Date: Mon, 2 Dec 2024 05:09:51 +0000 Subject: [PATCH 5/7] [update] Checkout PyOCN to a specific branch to integrate with CGRA --- noc/PyOCN | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/noc/PyOCN b/noc/PyOCN index b55a160..132f63f 160000 --- a/noc/PyOCN +++ b/noc/PyOCN @@ -1 +1 @@ -Subproject commit b55a16069e290132acf1e30ccf99bc94c2b567cb +Subproject commit 132f63fa8403f709c7f11e6fbc109ff3593241d5 From ff94b252b9a2e73c2bdca70deac2df440162af85 Mon Sep 17 00:00:00 2001 From: tancheng Date: Mon, 2 Dec 2024 05:13:21 +0000 Subject: [PATCH 6/7] [test] Include PyOCN ring simulation and translation test --- .github/workflows/python-package.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/python-package.yml b/.github/workflows/python-package.yml index 7b806f5..c393708 100644 --- a/.github/workflows/python-package.yml +++ b/.github/workflows/python-package.yml @@ -65,4 +65,5 @@ jobs: pytest ../cgra/translate/CGRAMemBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short pytest ../cgra/translate/CGRAMemRightAndBottomRTL_matmul_2x2_test.py -xvs --tb=short --test-verilog --dump-vtb --dump-vcd + pytest ../noc/PyOCN/pymtl3_net/ringnet/test/RingNetworkRTL_test.py --tb=short -sv From 9406bf7388f4eba3e0f779dd0a5325731a459851 Mon Sep 17 00:00:00 2001 From: tancheng Date: Mon, 2 Dec 2024 07:31:05 +0000 Subject: [PATCH 7/7] [feature] Test ring with CGRA data type --- lib/messages.py | 122 +++++++++++++++++++------ multi_cgra/__init__.py | 0 multi_cgra/test/RingNetworkRTL_test.py | 104 +++++++++++++++++++++ 3 files changed, 196 insertions(+), 30 deletions(-) create mode 100644 multi_cgra/__init__.py create mode 100644 multi_cgra/test/RingNetworkRTL_test.py diff --git a/lib/messages.py b/lib/messages.py index 3ab11c1..fb51e4f 100644 --- a/lib/messages.py +++ b/lib/messages.py @@ -63,7 +63,8 @@ def str_func( s ): # Generic config message #========================================================================= -def mk_ctrl( num_fu_in=2, num_inports=5, num_outports=5, prefix="CGRAConfig" ): +def mk_ctrl(num_fu_in = 2, num_inports = 5, num_outports = 5, + prefix = "CGRAConfig"): ctrl_nbits = 6 CtrlType = mk_bits( ctrl_nbits ) @@ -72,7 +73,8 @@ def mk_ctrl( num_fu_in=2, num_inports=5, num_outports=5, prefix="CGRAConfig" ): FuInType = mk_bits( clog2( num_fu_in + 1 ) ) PredicateType = mk_bits( 1 ) - new_name = f"{prefix}_{ctrl_nbits}_{num_fu_in}_{num_inports}_{num_outports}" + new_name = f"{prefix}_{ctrl_nbits}_{num_fu_in}_{num_inports}_" \ + f"{num_outports}" def str_func( s ): out_str = '(in)' @@ -100,27 +102,31 @@ def str_func( s ): return f"(opt){s.ctrl}|{out_str}" field_dict = {} - field_dict[ 'ctrl' ] = CtrlType - # The 'predicate' indicates whether the current operation is based on the partial - # predication or not. Note that 'predicate' is different from the following - # 'predicate_in', which contributes to the 'predicate' at the next cycle. - field_dict[ 'predicate' ] = PredicateType - # The fu_in indicates the input register ID (i.e., operands) for the operation. - field_dict[ 'fu_in' ] = [ FuInType for _ in range( num_fu_in ) ] - - field_dict[ 'outport' ] = [ InportsType for _ in range( num_outports ) ] - # I assume one tile supports single predicate during the entire execution time, as - # it is hard to distinguish predication for different operations (we automatically - # update, i.e., 'or', the predicate stored in the predicate register). This should - # be guaranteed by the compiler. - field_dict[ 'predicate_in' ] = [ PredicateType for _ in range( num_inports ) ] + field_dict['ctrl'] = CtrlType + # The 'predicate' indicates whether the current operation is based on + # the partial predication or not. Note that 'predicate' is different + # from the following 'predicate_in', which contributes to the + # 'predicate' at the next cycle. + field_dict['predicate'] = PredicateType + # The fu_in indicates the input register ID (i.e., operands) for the + # operation. + field_dict['fu_in'] = [FuInType for _ in range(num_fu_in)] + + field_dict['outport'] = [InportsType for _ in range(num_outports)] + # I assume one tile supports single predicate during the entire + # execution time, as it is hard to distinguish predication for + # different operations (we automatically update, i.e., 'or', the + # predicate stored in the predicate register). This should be + # guaranteed by the compiler. + field_dict['predicate_in'] = [PredicateType for _ in range( + num_inports)] # TODO: to support multiple predicate # field_dict[ 'predicate_in0' ] = ... # field_dict[ 'predicate_in1' ] = ... - return mk_bitstruct( new_name, field_dict, - namespace = { '__str__': str_func } + return mk_bitstruct(new_name, field_dict, + namespace = {'__str__': str_func} ) @@ -139,7 +145,9 @@ def mk_separate_ctrl(num_fu_inports = 4, FuOutType = mk_bits(clog2(num_fu_outports + 1)) PredicateType = mk_bits(1) - new_name = f"{prefix}_{operation_nbits}_{num_fu_inports}_{num_fu_outports}_{num_tile_inports}_{num_tile_outports}" + new_name = f"{prefix}_{operation_nbits}_{num_fu_inports}_" \ + f"{num_fu_outports}_{num_tile_inports}_" \ + f"{num_tile_outports}" def str_func(s): out_str = '(fu_in)' @@ -180,20 +188,25 @@ def str_func(s): field_dict = {} field_dict['ctrl'] = OperationType # TODO: need fix to pair `predicate` with specific operation. - # The 'predicate' indicates whether the current operation is based on the partial - # predication or not. Note that 'predicate' is different from the following - # 'predicate_in', which contributes to the 'predicate' at the next cycle. + # The 'predicate' indicates whether the current operation is based on + # the partial predication or not. Note that 'predicate' is different + # from the following 'predicate_in', which contributes to the 'predicate' + # at the next cycle. field_dict['predicate'] = PredicateType - # The fu_in indicates the input register ID (i.e., operands) for the operation. + # The fu_in indicates the input register ID (i.e., operands) for the + # operation. field_dict['fu_in'] = [FuInType for _ in range(num_fu_inports)] - field_dict['routing_xbar_outport'] = [TileInportsType for _ in range(num_routing_outports)] - field_dict['fu_xbar_outport'] = [FuOutType for _ in range(num_routing_outports)] - # I assume one tile supports single predicate during the entire execution time, as - # it is hard to distinguish predication for different operations (we automatically - # update, i.e., 'or', the predicate stored in the predicate register). This should - # be guaranteed by the compiler. - field_dict['routing_predicate_in'] = [PredicateType for _ in range(num_tile_inports)] + field_dict['routing_xbar_outport'] = [TileInportsType for _ in range( + num_routing_outports)] + field_dict['fu_xbar_outport'] = [FuOutType for _ in range( + num_routing_outports)] + # I assume one tile supports single predicate during the entire execution + # time, as it is hard to distinguish predication for different operations + # (we automatically update, i.e., 'or', the predicate stored in the + # predicate register). This should be guaranteed by the compiler. + field_dict['routing_predicate_in'] = [PredicateType for _ in range( + num_tile_inports)] # TODO: to support multiple predicate # field_dict[ 'predicate_in0' ] = ... @@ -203,3 +216,52 @@ def str_func(s): namespace = { '__str__': str_func } ) + +#========================================================================= +# Ring multi-CGRA data/config/cmd packet +#========================================================================= + +def mk_ring_multi_cgra_pkt(nrouters = 4, opaque_nbits = 8, vc = 2, + payload_nbits = 16, predicate_nbits = 1, + prefix="RingMultiCGRAPacket" ): + + IdType = mk_bits(clog2(nrouters)) + OpqType = mk_bits(opaque_nbits) + PayloadType = mk_bits(payload_nbits) + PredicateType = mk_bits(predicate_nbits) + + new_name = f"{prefix}_{nrouters}_{vc}_{opaque_nbits}_{payload_nbits}_" \ + f"{predicate_nbits}" + + if vc > 1: + VcIdType = mk_bits( clog2( vc ) ) + + def str_func( s ): + return f"{s.src}>{s.dst}:{s.opaque}:{s.vc_id}:{s.payload}." \ + f"{s.predicate}" + + return mk_bitstruct( new_name, { + 'src': IdType, + 'dst': IdType, + 'opaque': OpqType, + 'vc_id': VcIdType, + 'payload': PayloadType, + 'predicate': PredicateType, + }, + namespace = { '__str__': str_func } + ) + + else: + def str_func( s ): + return f"{s.src}>{s.dst}:{s.opaque}:{s.payload}.{s.predicate}" + + return mk_bitstruct( new_name, { + 'src': IdType, + 'dst': IdType, + 'opaque': OpqType, + 'payload': PayloadType, + 'predicate': PredicateType, + }, + namespace = { '__str__': str_func } + ) + diff --git a/multi_cgra/__init__.py b/multi_cgra/__init__.py new file mode 100644 index 0000000..e69de29 diff --git a/multi_cgra/test/RingNetworkRTL_test.py b/multi_cgra/test/RingNetworkRTL_test.py new file mode 100644 index 0000000..25f8a85 --- /dev/null +++ b/multi_cgra/test/RingNetworkRTL_test.py @@ -0,0 +1,104 @@ +""" +========================================================================= +RingNetworkRTL_test.py +========================================================================= +Test for RingNetworkRTL with CGRA message. + +Author : Cheng Tan + Date : Dec 1, 2024 +""" + + +from pymtl3 import * +from ...lib.basic.val_rdy.SourceRTL import SourceRTL as TestSrcRTL +from ...lib.messages import * +from ...lib.opt_type import * +# from ...noc.PyOCN.pymtl3_net.ocnlib.ifcs.packets import mk_ring_pkt +from ...noc.PyOCN.pymtl3_net.ocnlib.ifcs.positions import mk_ring_pos +from ...noc.PyOCN.pymtl3_net.ocnlib.utils import run_sim +from ...noc.PyOCN.pymtl3_net.ocnlib.test.stream_sinks import NetSinkRTL as TestNetSinkRTL +from ...noc.PyOCN.pymtl3_net.ringnet.RingNetworkFL import ringnet_fl +from ...noc.PyOCN.pymtl3_net.ringnet.RingNetworkRTL import RingNetworkRTL + + +#------------------------------------------------------------------------- +# TestHarness +#------------------------------------------------------------------------- + +class TestHarness(Component): + + def construct(s, MsgType, num_routers, src_msgs, sink_msgs): + + s.num_routers = num_routers + RingPos = mk_ring_pos(num_routers) + cmp_fn = lambda a, b : a.payload == b.payload + + s.srcs = [TestSrcRTL(MsgType, src_msgs[i]) + for i in range(num_routers)] + s.dut = RingNetworkRTL(MsgType, RingPos, num_routers, 0) + s.sinks = [TestNetSinkRTL(MsgType, sink_msgs[i], cmp_fn = cmp_fn) + for i in range( num_routers)] + + # Connections + for i in range (s.dut.num_routers): + s.srcs[i].send //= s.dut.recv[i] + s.dut.send[i] //= s.sinks[i].recv + + def done(s): + srcs_done = True + sinks_done = True + for i in range(s.num_routers): + srcs_done = srcs_done and s.srcs[i].done() + sinks_done = sinks_done and s.sinks[i].done() + return srcs_done and sinks_done + + def line_trace(s): + return s.dut.line_trace() + +#------------------------------------------------------------------------- +# mk_src_pkts +#------------------------------------------------------------------------- + +def mk_src_pkts( nterminals, lst ): + src_pkts = [ [] for _ in range( nterminals ) ] + src = 0 + for pkt in lst: + if hasattr(pkt, 'fl_type'): + if pkt.fl_type == 0: + src = pkt.src + else: + src = pkt.src + src_pkts[ src ].append( pkt ) + return src_pkts + +#========================================================================= +# Test cases +#========================================================================= + +class RingNetwork_Tests: + + @classmethod + def setup_class(cls): + cls.DutType = RingNetworkRTL + + def _test_cgra_data(s, translation = ''): + DataType = mk_data(16, 1) + nterminals = 4 + Pkt = mk_ring_multi_cgra_pkt(nterminals, payload_nbits = 32, + predicate_nbits = 1) + src_pkts = mk_src_pkts(nterminals, [ + # src dst opq vc payload predicate + Pkt(0, 1, 0, 0, 0xfaceb00c, 1), + Pkt(1, 2, 1, 0, 0xdeadbeef, 0), + Pkt(2, 3, 2, 0, 0xbaadface, 1), + Pkt(3, 0, 0, 0, 0xfaceb00c, 0), + ]) + dst_pkts = ringnet_fl(src_pkts) + th = TestHarness(Pkt, nterminals, src_pkts, dst_pkts) + cmdline_opts={'dump_vcd': False, 'test_verilog': translation, + 'dump_vtb': False} + run_sim(th, cmdline_opts) + + def test_cgra_data(self): + self._test_cgra_data('zeros') +