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Decoder.cpp
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// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "DecodedInst.hpp"
#include "IntRegs.hpp"
#include "Decoder.hpp"
#include "instforms.hpp"
using namespace WdRiscv;
Decoder::Decoder() = default;
Decoder::~Decoder() = default;
void
Decoder::decode(uint64_t addr, uint64_t physAddr, uint32_t inst, DecodedInst& di) const
{
// For vector load/store ops, op3 captures the number of fields
// (non-zero for segmented, and whole-register ld/st).
uint32_t op0 = 0, op1 = 0, op2 = 0, op3 = 0;
const InstEntry& entry = decode(inst, op0, op1, op2, op3);
di.reset(addr, physAddr, inst, &entry, op0, op1, op2, op3);
// Set the mask bit for vector instructions. Set acquire/release bits
// for atomic instructions.
if (di.instEntry())
{
if (di.instEntry()->isVector())
{
bool masked = ((inst >> 25) & 1) == 0; // Bit 25 of instruction
di.setMasked(masked);
di.setVecFieldCount(op3);
}
}
}
const InstEntry&
Decoder::decodeFp(uint32_t inst, uint32_t& op0, uint32_t& op1, uint32_t& op2) const
{
RFormInst rform(inst);
op0 = rform.bits.rd, op1 = rform.bits.rs1, op2 = rform.bits.rs2;
unsigned f7 = rform.bits.funct7, f3 = rform.bits.funct3;
unsigned top5 = f7 >> 2;
if ((f7 & 3) == 1)
{
if (top5 == 0) return instTable_.getEntry(InstId::fadd_d);
if (top5 == 1) return instTable_.getEntry(InstId::fsub_d);
if (top5 == 2) return instTable_.getEntry(InstId::fmul_d);
if (top5 == 3) return instTable_.getEntry(InstId::fdiv_d);
if (top5 == 4)
{
if (f3 == 0) return instTable_.getEntry(InstId::fsgnj_d);
if (f3 == 1) return instTable_.getEntry(InstId::fsgnjn_d);
if (f3 == 2) return instTable_.getEntry(InstId::fsgnjx_d);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 5)
{
if (f3 == 0) return instTable_.getEntry(InstId::fmin_d);
if (f3 == 2) return instTable_.getEntry(InstId::fminm_d);
if (f3 == 1) return instTable_.getEntry(InstId::fmax_d);
if (f3 == 3) return instTable_.getEntry(InstId::fmaxm_d);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 8)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_d_s);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_d_h);
if (op2 == 4) return instTable_.getEntry(InstId::fround_d);
if (op2 == 5) return instTable_.getEntry(InstId::froundnx_d);
return instTable_.getEntry(InstId::illegal);
}
if (top5==0xb and op2==0) return instTable_.getEntry(InstId::fsqrt_d);
if (top5 == 0x14)
{
if (f3 == 0) return instTable_.getEntry(InstId::fle_d);
if (f3 == 4) return instTable_.getEntry(InstId::fleq_d);
if (f3 == 1) return instTable_.getEntry(InstId::flt_d);
if (f3 == 5) return instTable_.getEntry(InstId::fltq_d);
if (f3 == 2) return instTable_.getEntry(InstId::feq_d);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x18)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_w_d);
if (op2 ==8 && f3==1) return instTable_.getEntry(InstId::fcvtmod_w_d);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_wu_d);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_l_d);
if (op2 == 3) return instTable_.getEntry(InstId::fcvt_lu_d);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1a)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_d_w);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_d_wu);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_d_l);
if (op2 == 3) return instTable_.getEntry(InstId::fcvt_d_lu);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1c)
{
if (op2==0 and f3==0) return instTable_.getEntry(InstId::fmv_x_d);
if (op2==0 and f3==1) return instTable_.getEntry(InstId::fclass_d);
if (op2==1 and f3==0) return instTable_.getEntry(InstId::fmvh_x_d);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1e)
{
if (op2==0 and f3==0) return instTable_.getEntry(InstId::fmv_d_x);
if (op2==1 and f3==0) return instTable_.getEntry(InstId::fli_d);
}
if (top5 == 0x26)
if (f3==0) return instTable_.getEntry(InstId::fmvp_d_x);
return instTable_.getEntry(InstId::illegal);
}
if ((f7 & 3) == 0)
{
if (top5 == 0) return instTable_.getEntry(InstId::fadd_s);
if (top5 == 1) return instTable_.getEntry(InstId::fsub_s);
if (top5 == 2) return instTable_.getEntry(InstId::fmul_s);
if (top5 == 3) return instTable_.getEntry(InstId::fdiv_s);
if (top5 == 4)
{
if (f3 == 0) return instTable_.getEntry(InstId::fsgnj_s);
if (f3 == 1) return instTable_.getEntry(InstId::fsgnjn_s);
if (f3 == 2) return instTable_.getEntry(InstId::fsgnjx_s);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 5)
{
if (f3 == 0) return instTable_.getEntry(InstId::fmin_s);
if (f3 == 2) return instTable_.getEntry(InstId::fminm_s);
if (f3 == 1) return instTable_.getEntry(InstId::fmax_s);
if (f3 == 3) return instTable_.getEntry(InstId::fmaxm_s);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 8)
{
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_s_d);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_s_h);
if (op2 == 4) return instTable_.getEntry(InstId::fround_s);
if (op2 == 5) return instTable_.getEntry(InstId::froundnx_s);
if (op2 == 6) return instTable_.getEntry(InstId::fcvt_s_bf16);
return instTable_.getEntry(InstId::illegal);
}
if (top5==0xb and op2==0) return instTable_.getEntry(InstId::fsqrt_s);
if (top5 == 0x14)
{
if (f3 == 0) return instTable_.getEntry(InstId::fle_s);
if (f3 == 1) return instTable_.getEntry(InstId::flt_s);
if (f3 == 2) return instTable_.getEntry(InstId::feq_s);
if (f3 == 4) return instTable_.getEntry(InstId::fleq_s);
if (f3 == 5) return instTable_.getEntry(InstId::fltq_s);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x18)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_w_s);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_wu_s);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_l_s);
if (op2 == 3) return instTable_.getEntry(InstId::fcvt_lu_s);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1a)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_s_w);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_s_wu);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_s_l);
if (op2 == 3) return instTable_.getEntry(InstId::fcvt_s_lu);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1c)
{
if (op2==0 and f3==0) return instTable_.getEntry(InstId::fmv_x_w);
if (op2==0 and f3==1) return instTable_.getEntry(InstId::fclass_s);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1e)
{
if (op2==0 and f3==0) return instTable_.getEntry(InstId::fmv_w_x);
if (op2==1 and f3==0) return instTable_.getEntry(InstId::fli_s);
}
return instTable_.getEntry(InstId::illegal);
}
if ((f7 & 3) == 2)
{
if (top5 == 0) return instTable_.getEntry(InstId::fadd_h);
if (top5 == 1) return instTable_.getEntry(InstId::fsub_h);
if (top5 == 2) return instTable_.getEntry(InstId::fmul_h);
if (top5 == 3) return instTable_.getEntry(InstId::fdiv_h);
if (top5 == 4)
{
if (f3 == 0) return instTable_.getEntry(InstId::fsgnj_h);
if (f3 == 1) return instTable_.getEntry(InstId::fsgnjn_h);
if (f3 == 2) return instTable_.getEntry(InstId::fsgnjx_h);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 5)
{
if (f3 == 0) return instTable_.getEntry(InstId::fmin_h);
if (f3 == 2) return instTable_.getEntry(InstId::fminm_h);
if (f3 == 1) return instTable_.getEntry(InstId::fmax_h);
if (f3 == 3) return instTable_.getEntry(InstId::fmaxm_h);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 8)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_h_s);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_h_d);
if (op2 == 4) return instTable_.getEntry(InstId::fround_h);
if (op2 == 5) return instTable_.getEntry(InstId::froundnx_h);
if (op2 == 8) return instTable_.getEntry(InstId::fcvt_bf16_s);
return instTable_.getEntry(InstId::illegal);
}
if (top5==0xb and op2==0) return instTable_.getEntry(InstId::fsqrt_h);
if (top5 == 0x14)
{
if (f3 == 0) return instTable_.getEntry(InstId::fle_h);
if (f3 == 4) return instTable_.getEntry(InstId::fleq_h);
if (f3 == 1) return instTable_.getEntry(InstId::flt_h);
if (f3 == 5) return instTable_.getEntry(InstId::fltq_h);
if (f3 == 2) return instTable_.getEntry(InstId::feq_h);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x18)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_w_h);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_wu_h);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_l_h);
if (op2 == 3) return instTable_.getEntry(InstId::fcvt_lu_h);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1a)
{
if (op2 == 0) return instTable_.getEntry(InstId::fcvt_h_w);
if (op2 == 1) return instTable_.getEntry(InstId::fcvt_h_wu);
if (op2 == 2) return instTable_.getEntry(InstId::fcvt_h_l);
if (op2 == 3) return instTable_.getEntry(InstId::fcvt_h_lu);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1c)
{
if (op2==0 and f3==0) return instTable_.getEntry(InstId::fmv_x_h);
if (op2==0 and f3==1) return instTable_.getEntry(InstId::fclass_h);
return instTable_.getEntry(InstId::illegal);
}
if (top5 == 0x1e)
{
if (op2==0 and f3==0) return instTable_.getEntry(InstId::fmv_h_x);
if (op2==1 and f3==0) return instTable_.getEntry(InstId::fli_h);
}
return instTable_.getEntry(InstId::illegal);
}
return instTable_.getEntry(InstId::illegal);
}
inline bool
isMaskedVec(uint32_t inst)
{
return ((inst >> 25) & 1) == 0;
}
// Least sig 7 bits already determined to be: 1010111
const InstEntry&
Decoder::decodeVec(uint32_t inst, uint32_t& op0, uint32_t& op1, uint32_t& op2,
uint32_t& op3) const
{
RFormInst rform(inst);
unsigned f3 = rform.bits.funct3, f6 = rform.top6();
unsigned vm = (inst >> 25) & 1;
bool masked = vm == 0;
const InstEntry& illegal = instTable_.getEntry(InstId::illegal);
op3 = 0;
if (f3 == 0)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2; // operand order reversed
op2 = rform.bits.rs1;
switch (f6)
{
case 0: return instTable_.getEntry(InstId::vadd_vv);
case 1: return instTable_.getEntry(InstId::vandn_vv);
case 2: return instTable_.getEntry(InstId::vsub_vv);
case 4: return instTable_.getEntry(InstId::vminu_vv);
case 5: return instTable_.getEntry(InstId::vmin_vv);
case 6: return instTable_.getEntry(InstId::vmaxu_vv);
case 7: return instTable_.getEntry(InstId::vmax_vv);
case 9: return instTable_.getEntry(InstId::vand_vv);
case 0xa: return instTable_.getEntry(InstId::vor_vv);
case 0xb: return instTable_.getEntry(InstId::vxor_vv);
case 0xc: return instTable_.getEntry(InstId::vrgather_vv);
case 0xe: return instTable_.getEntry(InstId::vrgatherei16_vv);
case 0x10: return instTable_.getEntry(InstId::vadc_vvm);
case 0x11: return instTable_.getEntry(InstId::vmadc_vvm);
case 0x12: return instTable_.getEntry(InstId::vsbc_vvm);
case 0x13: return instTable_.getEntry(InstId::vmsbc_vvm);
case 0x14: return instTable_.getEntry(InstId::vror_vv);
case 0x15: return instTable_.getEntry(InstId::vrol_vv);
case 0x17:
if (vm == 0) return instTable_.getEntry(InstId::vmerge_vvm);
if (vm == 1)
{
std::swap(op1, op2); // Per spec !
if (op2 == 0) return instTable_.getEntry(InstId::vmv_v_v);
}
break;
case 0x18: return instTable_.getEntry(InstId::vmseq_vv);
case 0x19: return instTable_.getEntry(InstId::vmsne_vv);
case 0x1a: return instTable_.getEntry(InstId::vmsltu_vv);
case 0x1b: return instTable_.getEntry(InstId::vmslt_vv);
case 0x1c: return instTable_.getEntry(InstId::vmsleu_vv);
case 0x1d: return instTable_.getEntry(InstId::vmsle_vv);
case 0x20: return instTable_.getEntry(InstId::vsaddu_vv);
case 0x21: return instTable_.getEntry(InstId::vsadd_vv);
case 0x22: return instTable_.getEntry(InstId::vssubu_vv);
case 0x23: return instTable_.getEntry(InstId::vssub_vv);
case 0x25: return instTable_.getEntry(InstId::vsll_vv);
case 0x27: return instTable_.getEntry(InstId::vsmul_vv);
case 0x28: return instTable_.getEntry(InstId::vsrl_vv);
case 0x29: return instTable_.getEntry(InstId::vsra_vv);
case 0x2a: return instTable_.getEntry(InstId::vssrl_vv);
case 0x2b: return instTable_.getEntry(InstId::vssra_vv);
case 0x2c: return instTable_.getEntry(InstId::vnsrl_wv);
case 0x2d: return instTable_.getEntry(InstId::vnsra_wv);
case 0x2e: return instTable_.getEntry(InstId::vnclipu_wv);
case 0x2f: return instTable_.getEntry(InstId::vnclip_wv);
case 0x30: return instTable_.getEntry(InstId::vwredsumu_vs);
case 0x31: return instTable_.getEntry(InstId::vwredsum_vs);
case 0x35: return instTable_.getEntry(InstId::vwsll_vv);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 1)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2;
op2 = rform.bits.rs1;
switch (f6)
{
case 0: return instTable_.getEntry(InstId::vfadd_vv);
case 1: return instTable_.getEntry(InstId::vfredusum_vs);
case 2: return instTable_.getEntry(InstId::vfsub_vv);
case 3: return instTable_.getEntry(InstId::vfredosum_vs);
case 4: return instTable_.getEntry(InstId::vfmin_vv);
case 5: return instTable_.getEntry(InstId::vfredmin_vs);
case 6: return instTable_.getEntry(InstId::vfmax_vv);
case 7: return instTable_.getEntry(InstId::vfredmax_vs);
case 8: return instTable_.getEntry(InstId::vfsgnj_vv);
case 9: return instTable_.getEntry(InstId::vfsgnjn_vv);
case 0xa: return instTable_.getEntry(InstId::vfsgnjx_vv);
case 0x10:
if (op2 == 0) return instTable_.getEntry(InstId::vfmv_f_s);
return instTable_.getEntry(InstId::illegal);
case 0x12:
switch (op2)
{
case 0: return instTable_.getEntry(InstId::vfcvt_xu_f_v);
case 1: return instTable_.getEntry(InstId::vfcvt_x_f_v);
case 2: return instTable_.getEntry(InstId::vfcvt_f_xu_v);
case 3: return instTable_.getEntry(InstId::vfcvt_f_x_v);
case 6: return instTable_.getEntry(InstId::vfcvt_rtz_xu_f_v);
case 7: return instTable_.getEntry(InstId::vfcvt_rtz_x_f_v);
case 8: return instTable_.getEntry(InstId::vfwcvt_xu_f_v);
case 9: return instTable_.getEntry(InstId::vfwcvt_x_f_v);
case 0xa: return instTable_.getEntry(InstId::vfwcvt_f_xu_v);
case 0xb: return instTable_.getEntry(InstId::vfwcvt_f_x_v);
case 0xc: return instTable_.getEntry(InstId::vfwcvt_f_f_v);
case 0xd: return instTable_.getEntry(InstId::vfwcvtbf16_f_f_v);
case 0xe: return instTable_.getEntry(InstId::vfwcvt_rtz_xu_f_v);
case 0xf: return instTable_.getEntry(InstId::vfwcvt_rtz_x_f_v);
case 0x10: return instTable_.getEntry(InstId::vfncvt_xu_f_w);
case 0x11: return instTable_.getEntry(InstId::vfncvt_x_f_w);
case 0x12: return instTable_.getEntry(InstId::vfncvt_f_xu_w);
case 0x13: return instTable_.getEntry(InstId::vfncvt_f_x_w);
case 0x14: return instTable_.getEntry(InstId::vfncvt_f_f_w);
case 0x15: return instTable_.getEntry(InstId::vfncvt_rod_f_f_w);
case 0x16: return instTable_.getEntry(InstId::vfncvt_rtz_xu_f_w);
case 0x17: return instTable_.getEntry(InstId::vfncvt_rtz_x_f_w);
case 0x1d: return instTable_.getEntry(InstId::vfncvtbf16_f_f_w);
}
break;
case 0x13:
if (op2 == 0) return instTable_.getEntry(InstId::vfsqrt_v);
if (op2 == 4) return instTable_.getEntry(InstId::vfrsqrt7_v);
if (op2 == 5) return instTable_.getEntry(InstId::vfrec7_v);
if (op2 == 0x10) return instTable_.getEntry(InstId::vfclass_v);
break;
case 0x18: return instTable_.getEntry(InstId::vmfeq_vv);
case 0x19: return instTable_.getEntry(InstId::vmfle_vv);
case 0x1b: return instTable_.getEntry(InstId::vmflt_vv);
case 0x1c: return instTable_.getEntry(InstId::vmfne_vv);
case 0x20: return instTable_.getEntry(InstId::vfdiv_vv);
case 0x24: return instTable_.getEntry(InstId::vfmul_vv);
case 0x28:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmadd_vv);
case 0x29:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmadd_vv);
case 0x2a:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmsub_vv);
case 0x2b:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmsub_vv);
case 0x2c:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmacc_vv);
case 0x2d:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmacc_vv);
case 0x2e:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmsac_vv);
case 0x2f:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmsac_vv);
case 0x30: return instTable_.getEntry(InstId::vfwadd_vv);
case 0x31: return instTable_.getEntry(InstId::vfwredusum_vs);
case 0x32: return instTable_.getEntry(InstId::vfwsub_vv);
case 0x33: return instTable_.getEntry(InstId::vfwredosum_vs);
case 0x34: return instTable_.getEntry(InstId::vfwadd_wv);
case 0x36: return instTable_.getEntry(InstId::vfwsub_wv);
case 0x38: return instTable_.getEntry(InstId::vfwmul_vv);
case 0x3b:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwmaccbf16_vv);
case 0x3c:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwmacc_vv);
case 0x3d:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwnmacc_vv);
case 0x3e:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwmsac_vv);
case 0x3f:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwnmsac_vv);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 2)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2; // operand order reversed
op2 = rform.bits.rs1;
switch(f6)
{
case 0: return instTable_.getEntry(InstId::vredsum_vs);
case 1: return instTable_.getEntry(InstId::vredand_vs);
case 2: return instTable_.getEntry(InstId::vredor_vs);
case 3: return instTable_.getEntry(InstId::vredxor_vs);
case 4: return instTable_.getEntry(InstId::vredminu_vs);
case 5: return instTable_.getEntry(InstId::vredmin_vs);
case 6: return instTable_.getEntry(InstId::vredmaxu_vs);
case 7: return instTable_.getEntry(InstId::vredmax_vs);
case 8: return instTable_.getEntry(InstId::vaaddu_vv);
case 9: return instTable_.getEntry(InstId::vaadd_vv);
case 0xa: return instTable_.getEntry(InstId::vasubu_vv);
case 0xb: return instTable_.getEntry(InstId::vasub_vv);
case 0xc: return instTable_.getEntry(InstId::vclmul_vv);
case 0xd: return instTable_.getEntry(InstId::vclmulh_vv);
case 0x10:
if (op2 == 0) return instTable_.getEntry(InstId::vmv_x_s);
if (op2 == 0x10) return instTable_.getEntry(InstId::vcpop_m);
if (op2 == 0x11) return instTable_.getEntry(InstId::vfirst_m);
return instTable_.getEntry(InstId::illegal);
case 0x12:
if (op2 == 2) return instTable_.getEntry(InstId::vzext_vf8);
if (op2 == 4) return instTable_.getEntry(InstId::vzext_vf4);
if (op2 == 6) return instTable_.getEntry(InstId::vzext_vf2);
if (op2 == 3) return instTable_.getEntry(InstId::vsext_vf8);
if (op2 == 5) return instTable_.getEntry(InstId::vsext_vf4);
if (op2 == 7) return instTable_.getEntry(InstId::vsext_vf2);
if (op2 == 8) return instTable_.getEntry(InstId::vbrev8_v);
if (op2 == 9) return instTable_.getEntry(InstId::vrev8_v);
if (op2 == 10) return instTable_.getEntry(InstId::vbrev_v);
if (op2 == 12) return instTable_.getEntry(InstId::vclz_v);
if (op2 == 13) return instTable_.getEntry(InstId::vctz_v);
if (op2 == 14) return instTable_.getEntry(InstId::vcpop_v);
return instTable_.getEntry(InstId::illegal);
case 0x14:
if (op2 == 1) return instTable_.getEntry(InstId::vmsbf_m);
if (op2 == 2) return instTable_.getEntry(InstId::vmsof_m);
if (op2 == 3) return instTable_.getEntry(InstId::vmsif_m);
if (op2 == 0x10) return instTable_.getEntry(InstId::viota_m);
if (op2 == 0x11) return instTable_.getEntry(InstId::vid_v);
return instTable_.getEntry(InstId::illegal);
case 0x17: return instTable_.getEntry(InstId::vcompress_vm);
case 0x19: return masked? illegal : instTable_.getEntry(InstId::vmand_mm);
case 0x1d: return masked? illegal : instTable_.getEntry(InstId::vmnand_mm);
case 0x18: return masked? illegal : instTable_.getEntry(InstId::vmandn_mm);
case 0x1b: return masked? illegal : instTable_.getEntry(InstId::vmxor_mm);
case 0x1a: return masked? illegal : instTable_.getEntry(InstId::vmor_mm);
case 0x1e: return masked? illegal : instTable_.getEntry(InstId::vmnor_mm);
case 0x1c: return masked? illegal : instTable_.getEntry(InstId::vmorn_mm);
case 0x1f: return masked? illegal : instTable_.getEntry(InstId::vmxnor_mm);
case 0x20: return instTable_.getEntry(InstId::vdivu_vv);
case 0x21: return instTable_.getEntry(InstId::vdiv_vv);
case 0x22: return instTable_.getEntry(InstId::vremu_vv);
case 0x23: return instTable_.getEntry(InstId::vrem_vv);
case 0x24: return instTable_.getEntry(InstId::vmulhu_vv);
case 0x25: return instTable_.getEntry(InstId::vmul_vv);
case 0x26: return instTable_.getEntry(InstId::vmulhsu_vv);
case 0x27: return instTable_.getEntry(InstId::vmulh_vv);
case 0x29:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vmadd_vv);
case 0x2b:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vnmsub_vv);
case 0x2d:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vmacc_vv);
case 0x2f:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vnmsac_vv);
case 0x30: return instTable_.getEntry(InstId::vwaddu_vv);
case 0x31: return instTable_.getEntry(InstId::vwadd_vv);
case 0x32: return instTable_.getEntry(InstId::vwsubu_vv);
case 0x33: return instTable_.getEntry(InstId::vwsub_vv);
case 0x34: return instTable_.getEntry(InstId::vwaddu_wv);
case 0x35: return instTable_.getEntry(InstId::vwadd_wv);
case 0x36: return instTable_.getEntry(InstId::vwsubu_wv);
case 0x37: return instTable_.getEntry(InstId::vwsub_wv);
case 0x38: return instTable_.getEntry(InstId::vwmulu_vv);
case 0x3a: return instTable_.getEntry(InstId::vwmulsu_vv);
case 0x3b: return instTable_.getEntry(InstId::vwmul_vv);
case 0x3c:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmaccu_vv);
case 0x3d:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmacc_vv);
case 0x3f:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmaccsu_vv);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 3)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2; // operand order reversed
uint32_t uimm = rform.bits.rs1; // Unsigned immediate.
int32_t imm = (int32_t(uimm) << 27) >> 27; // Sign extended immediate.
op2 = imm;
switch (f6)
{
case 0: return instTable_.getEntry(InstId::vadd_vi);
case 3: return instTable_.getEntry(InstId::vrsub_vi);
case 9: return instTable_.getEntry(InstId::vand_vi);
case 0xa: return instTable_.getEntry(InstId::vor_vi);
case 0xb: return instTable_.getEntry(InstId::vxor_vi);
case 0xc: op2 = uimm; return instTable_.getEntry(InstId::vrgather_vi);
case 0xe: op2 = uimm; return instTable_.getEntry(InstId::vslideup_vi);
case 0xf: op2 = uimm; return instTable_.getEntry(InstId::vslidedown_vi);
case 0x10: return instTable_.getEntry(InstId::vadc_vim);
case 0x11: return instTable_.getEntry(InstId::vmadc_vim);
case 0x14: op2 = uimm; return instTable_.getEntry(InstId::vror_vi); // Bit 26 is zero.
case 0x15: op2 = uimm | 0x20; return instTable_.getEntry(InstId::vror_vi); // Bit 26 is 1.
case 0x17:
if (vm == 0) return instTable_.getEntry(InstId::vmerge_vim);
if (vm == 1)
{
op1 = (int32_t(rform.bits.rs1) << 27) >> 27;
op2 = rform.bits.rs2;
if (op2 == 0) return instTable_.getEntry(InstId::vmv_v_i);
}
break;
case 0x18: return instTable_.getEntry(InstId::vmseq_vi);
case 0x19: return instTable_.getEntry(InstId::vmsne_vi);
case 0x1c: return instTable_.getEntry(InstId::vmsleu_vi);
case 0x1d: return instTable_.getEntry(InstId::vmsle_vi);
case 0x1e: return instTable_.getEntry(InstId::vmsgtu_vi);
case 0x1f: return instTable_.getEntry(InstId::vmsgt_vi);
case 0x20: return instTable_.getEntry(InstId::vsaddu_vi);
case 0x21: return instTable_.getEntry(InstId::vsadd_vi);
case 0x25: op2 = uimm; return instTable_.getEntry(InstId::vsll_vi);
case 0x27:
if (imm == 0) return masked? illegal : instTable_.getEntry(InstId::vmv1r_v);
if (imm == 1) return masked? illegal : instTable_.getEntry(InstId::vmv2r_v);
if (imm == 3) return masked? illegal : instTable_.getEntry(InstId::vmv4r_v);
if (imm == 7) return masked? illegal : instTable_.getEntry(InstId::vmv8r_v);
break;
case 0x28: op2 = uimm; return instTable_.getEntry(InstId::vsrl_vi);
case 0x29: op2 = uimm; return instTable_.getEntry(InstId::vsra_vi);
case 0x2a: op2 = uimm; return instTable_.getEntry(InstId::vssrl_vi);
case 0x2b: op2 = uimm; return instTable_.getEntry(InstId::vssra_vi);
case 0x2c: op2 = uimm; return instTable_.getEntry(InstId::vnsrl_wi);
case 0x2d: op2 = uimm; return instTable_.getEntry(InstId::vnsra_wi);
case 0x2e: op2 = uimm; return instTable_.getEntry(InstId::vnclipu_wi);
case 0x2f: op2 = uimm; return instTable_.getEntry(InstId::vnclip_wi);
case 0x35: op2 = uimm; return instTable_.getEntry(InstId::vwsll_vi);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 4)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2; // operand order reversed
op2 = rform.bits.rs1;
switch (f6)
{
case 0: return instTable_.getEntry(InstId::vadd_vx);
case 1: return instTable_.getEntry(InstId::vandn_vx);
case 2: return instTable_.getEntry(InstId::vsub_vx);
case 3: return instTable_.getEntry(InstId::vrsub_vx);
case 4: return instTable_.getEntry(InstId::vminu_vx);
case 5: return instTable_.getEntry(InstId::vmin_vx);
case 6: return instTable_.getEntry(InstId::vmaxu_vx);
case 7: return instTable_.getEntry(InstId::vmax_vx);
case 9: return instTable_.getEntry(InstId::vand_vx);
case 0xa: return instTable_.getEntry(InstId::vor_vx);
case 0xb: return instTable_.getEntry(InstId::vxor_vx);
case 0xc: return instTable_.getEntry(InstId::vrgather_vx);
case 0xe: return instTable_.getEntry(InstId::vslideup_vx);
case 0xf: return instTable_.getEntry(InstId::vslidedown_vx);
case 0x10: return instTable_.getEntry(InstId::vadc_vxm);
case 0x11: return instTable_.getEntry(InstId::vmadc_vxm);
case 0x12: return instTable_.getEntry(InstId::vsbc_vxm);
case 0x13: return instTable_.getEntry(InstId::vmsbc_vxm);
case 0x14: return instTable_.getEntry(InstId::vror_vx);
case 0x15: return instTable_.getEntry(InstId::vrol_vx);
case 0x17:
if (vm == 0) return instTable_.getEntry(InstId::vmerge_vxm);
if (vm == 1)
{
std::swap(op1, op2); // Per spec!
if (op2 == 0) return instTable_.getEntry(InstId::vmv_v_x);
}
break;
case 0x18: return instTable_.getEntry(InstId::vmseq_vx);
case 0x19: return instTable_.getEntry(InstId::vmsne_vx);
case 0x1a: return instTable_.getEntry(InstId::vmsltu_vx);
case 0x1b: return instTable_.getEntry(InstId::vmslt_vx);
case 0x1c: return instTable_.getEntry(InstId::vmsleu_vx);
case 0x1d: return instTable_.getEntry(InstId::vmsle_vx);
case 0x1e: return instTable_.getEntry(InstId::vmsgtu_vx);
case 0x1f: return instTable_.getEntry(InstId::vmsgt_vx);
case 0x20: return instTable_.getEntry(InstId::vsaddu_vx);
case 0x21: return instTable_.getEntry(InstId::vsadd_vx);
case 0x22: return instTable_.getEntry(InstId::vssubu_vx);
case 0x23: return instTable_.getEntry(InstId::vssub_vx);
case 0x25: return instTable_.getEntry(InstId::vsll_vx);
case 0x27: return instTable_.getEntry(InstId::vsmul_vx);
case 0x28: return instTable_.getEntry(InstId::vsrl_vx);
case 0x29: return instTable_.getEntry(InstId::vsra_vx);
case 0x2a: return instTable_.getEntry(InstId::vssrl_vx);
case 0x2b: return instTable_.getEntry(InstId::vssra_vx);
case 0x2c: return instTable_.getEntry(InstId::vnsrl_wx);
case 0x2d: return instTable_.getEntry(InstId::vnsra_wx);
case 0x2e: return instTable_.getEntry(InstId::vnclipu_wx);
case 0x2f: return instTable_.getEntry(InstId::vnclip_wx);
case 0x35: return instTable_.getEntry(InstId::vwsll_vx);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 6)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2; // operand order reversed
op2 = rform.bits.rs1;
switch (f6)
{
case 8: return instTable_.getEntry(InstId::vaaddu_vx);
case 9: return instTable_.getEntry(InstId::vaadd_vx);
case 0xa: return instTable_.getEntry(InstId::vasubu_vx);
case 0xb: return instTable_.getEntry(InstId::vasub_vx);
case 0xc: return instTable_.getEntry(InstId::vclmul_vx);
case 0xd: return instTable_.getEntry(InstId::vclmulh_vx);
case 0xe: return instTable_.getEntry(InstId::vslide1up_vx);
case 0xf: return instTable_.getEntry(InstId::vslide1down_vx);
case 0x10:
std::swap(op1, op2); // per spec !
if (op2 == 0) return instTable_.getEntry(InstId::vmv_s_x);
return instTable_.getEntry(InstId::illegal);
case 0x20: return instTable_.getEntry(InstId::vdivu_vx);
case 0x21: return instTable_.getEntry(InstId::vdiv_vx);
case 0x22: return instTable_.getEntry(InstId::vremu_vx);
case 0x23: return instTable_.getEntry(InstId::vrem_vx);
case 0x24: return instTable_.getEntry(InstId::vmulhu_vx);
case 0x25: return instTable_.getEntry(InstId::vmul_vx);
case 0x26: return instTable_.getEntry(InstId::vmulhsu_vx);
case 0x27: return instTable_.getEntry(InstId::vmulh_vx);
case 0x29:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vmadd_vx);
case 0x2b:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vnmsub_vx);
case 0x2d:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vmacc_vx);
case 0x2f:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vnmsac_vx);
case 0x30: return instTable_.getEntry(InstId::vwaddu_vx);
case 0x31: return instTable_.getEntry(InstId::vwadd_vx);
case 0x32: return instTable_.getEntry(InstId::vwsubu_vx);
case 0x33: return instTable_.getEntry(InstId::vwsub_vx);
case 0x34: return instTable_.getEntry(InstId::vwaddu_wx);
case 0x35: return instTable_.getEntry(InstId::vwadd_wx);
case 0x36: return instTable_.getEntry(InstId::vwsubu_wx);
case 0x37: return instTable_.getEntry(InstId::vwsub_wx);
case 0x38: return instTable_.getEntry(InstId::vwmulu_vx);
case 0x3a: return instTable_.getEntry(InstId::vwmulsu_vx);
case 0x3b: return instTable_.getEntry(InstId::vwmul_vx);
case 0x3c:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmaccu_vx);
case 0x3d:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmacc_vx);
case 0x3e:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmaccus_vx);
case 0x3f:
std::swap(op1, op2); // Spec is baffling.
return instTable_.getEntry(InstId::vwmaccsu_vx);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 5)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs2;
op2 = rform.bits.rs1;
switch (f6)
{
case 0: return instTable_.getEntry(InstId::vfadd_vf);
case 2: return instTable_.getEntry(InstId::vfsub_vf);
case 4: return instTable_.getEntry(InstId::vfmin_vf);
case 6: return instTable_.getEntry(InstId::vfmax_vf);
case 8: return instTable_.getEntry(InstId::vfsgnj_vf);
case 9: return instTable_.getEntry(InstId::vfsgnjn_vf);
case 0xa: return instTable_.getEntry(InstId::vfsgnjx_vf);
case 0xe: return instTable_.getEntry(InstId::vfslide1up_vf);
case 0xf: return instTable_.getEntry(InstId::vfslide1down_vf);
case 0x10:
std::swap(op1, op2);
if (op2 == 0) return instTable_.getEntry(InstId::vfmv_s_f);
return instTable_.getEntry(InstId::illegal);
case 0x17:
if (vm == 0) return instTable_.getEntry(InstId::vfmerge_vfm);
if (vm == 1)
{
op1 = (uint32_t(rform.bits.rs1) << 27) >> 27;
op2 = rform.bits.rs2;
if (op2 == 0) return instTable_.getEntry(InstId::vfmv_v_f);
}
break;
case 0x18: return instTable_.getEntry(InstId::vmfeq_vf);
case 0x19: return instTable_.getEntry(InstId::vmfle_vf);
case 0x1b: return instTable_.getEntry(InstId::vmflt_vf);
case 0x1c: return instTable_.getEntry(InstId::vmfne_vf);
case 0x1d: return instTable_.getEntry(InstId::vmfgt_vf);
case 0x1f: return instTable_.getEntry(InstId::vmfge_vf);
case 0x20: return instTable_.getEntry(InstId::vfdiv_vf);
case 0x21: return instTable_.getEntry(InstId::vfrdiv_vf);
case 0x24: return instTable_.getEntry(InstId::vfmul_vf);
case 0x27: return instTable_.getEntry(InstId::vfrsub_vf);
case 0x28:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmadd_vf);
case 0x29:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmadd_vf);
case 0x2a:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmsub_vf);
case 0x2b:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmsub_vf);
case 0x2c:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmacc_vf);
case 0x2d:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmacc_vf);
case 0x2e:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfmsac_vf);
case 0x2f:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfnmsac_vf);
case 0x30: return instTable_.getEntry(InstId::vfwadd_vf);
case 0x32: return instTable_.getEntry(InstId::vfwsub_vf);
case 0x34: return instTable_.getEntry(InstId::vfwadd_wf);
case 0x36: return instTable_.getEntry(InstId::vfwsub_wf);
case 0x38: return instTable_.getEntry(InstId::vfwmul_vf);
case 0x3b:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwmaccbf16_vf);
case 0x3c:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwmacc_vf);
case 0x3d:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwnmacc_vf);
case 0x3e:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwmsac_vf);
case 0x3f:
std::swap(op1, op2); // per spec
return instTable_.getEntry(InstId::vfwnmsac_vf);
}
return instTable_.getEntry(InstId::illegal);
}
if (f3 == 7)
{
op0 = rform.bits.rd;
op1 = rform.bits.rs1;
op2 = rform.bits.rs2;
if ((f6 >> 5) == 0)
{
op2 = ((rform.bits.funct7 & 0x3f) << 5 | op2);
return instTable_.getEntry(InstId::vsetvli);
}
if ((f6 >> 4) == 3)
{
op2 = ((rform.bits.funct7 & 0x1f) << 5 | op2);
return instTable_.getEntry(InstId::vsetivli);
}
if (rform.bits.funct7 == 0x40) return instTable_.getEntry(InstId::vsetvl);
}
return instTable_.getEntry(InstId::illegal);
}
const InstEntry&
Decoder::decodeVecLoad(uint32_t f3, uint32_t imm12, uint32_t& fieldCount) const
{
unsigned lumop = imm12 & 0x1f; // Bits 0 to 4 of imm12
unsigned mop = (imm12 >> 6) & 3; // Bits 6 & 7 of imm12
unsigned mew = (imm12 >> 8) & 1; // Bit 8 of imm12
unsigned nf = (imm12 >> 9) & 7; // Bit 9, 10, and 11 of imm12
if (mop == 0)
{ // Unit stride
if (lumop == 0)
{
if (nf == 0)
{
if (mew == 0)
{
if (f3 == 0) return instTable_.getEntry(InstId::vle8_v);
if (f3 == 5) return instTable_.getEntry(InstId::vle16_v);
if (f3 == 6) return instTable_.getEntry(InstId::vle32_v);
if (f3 == 7) return instTable_.getEntry(InstId::vle64_v);
}
else
{
if (f3 == 0) return instTable_.getEntry(InstId::vle128_v);
if (f3 == 5) return instTable_.getEntry(InstId::vle256_v);
if (f3 == 6) return instTable_.getEntry(InstId::vle512_v);
if (f3 == 7) return instTable_.getEntry(InstId::vle1024_v);
}
}
else
{
fieldCount = 1 + nf; // number of fields in segment.
if (mew == 0)
{
if (f3 == 0) return instTable_.getEntry(InstId::vlsege8_v);
if (f3 == 5) return instTable_.getEntry(InstId::vlsege16_v);
if (f3 == 6) return instTable_.getEntry(InstId::vlsege32_v);
if (f3 == 7) return instTable_.getEntry(InstId::vlsege64_v);
}
else
{
if (f3 == 0) return instTable_.getEntry(InstId::vlsege128_v);
if (f3 == 5) return instTable_.getEntry(InstId::vlsege256_v);
if (f3 == 6) return instTable_.getEntry(InstId::vlsege512_v);
if (f3 == 7) return instTable_.getEntry(InstId::vlsege1024_v);
}
}
}
else if (lumop == 0x8)
{ // load whole registers
if (nf != 0 and nf != 1 and nf != 3 and nf != 7)
return instTable_.getEntry(InstId::illegal);
fieldCount = nf + 1;
if (mew == 0)
{
if (f3 == 0) return instTable_.getEntry(InstId::vlre8_v);
if (f3 == 5) return instTable_.getEntry(InstId::vlre16_v);
if (f3 == 6) return instTable_.getEntry(InstId::vlre32_v);
if (f3 == 7) return instTable_.getEntry(InstId::vlre64_v);
}
else
{
if (f3 == 0) return instTable_.getEntry(InstId::vlre128_v);
if (f3 == 5) return instTable_.getEntry(InstId::vlre256_v);
if (f3 == 6) return instTable_.getEntry(InstId::vlre512_v);
if (f3 == 7) return instTable_.getEntry(InstId::vlre1024_v);
}
}
else if (lumop == 0xb)
{
if (nf == 0 and mew == 0 and f3 == 0)
return instTable_.getEntry(InstId::vlm_v);
}
else if (lumop == 0x10)
{
if (nf == 0)
{
// fault only on first
if (mew == 0)
{
if (f3 == 0) return instTable_.getEntry(InstId::vle8ff_v);
if (f3 == 5) return instTable_.getEntry(InstId::vle16ff_v);
if (f3 == 6) return instTable_.getEntry(InstId::vle32ff_v);
if (f3 == 7) return instTable_.getEntry(InstId::vle64ff_v);
}
else
{
if (f3 == 0) return instTable_.getEntry(InstId::vle128ff_v);
if (f3 == 5) return instTable_.getEntry(InstId::vle256ff_v);
if (f3 == 6) return instTable_.getEntry(InstId::vle512ff_v);
if (f3 == 7) return instTable_.getEntry(InstId::vle1024ff_v);
}
}
else
{
fieldCount = nf + 1;
if (mew == 0)
{
if (f3 == 0) return instTable_.getEntry(InstId::vlsege8ff_v);
if (f3 == 5) return instTable_.getEntry(InstId::vlsege16ff_v);
if (f3 == 6) return instTable_.getEntry(InstId::vlsege32ff_v);
if (f3 == 7) return instTable_.getEntry(InstId::vlsege64ff_v);
}
else
{
if (f3 == 0) return instTable_.getEntry(InstId::vlsege128ff_v);
if (f3 == 5) return instTable_.getEntry(InstId::vlsege256ff_v);
if (f3 == 6) return instTable_.getEntry(InstId::vlsege512ff_v);
if (f3 == 7) return instTable_.getEntry(InstId::vlsege1024ff_v);
}
}
}
}
if (mop == 1)
{ // indexed unordered
if (nf == 0)
{
if (mew == 0)
{