From c0f2b11d605099d9a74f17ff795dbb30cb7ea2f1 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Tue, 28 Nov 2023 19:09:45 +0200 Subject: [PATCH] mpfs/mpfs_corespi.c: Round up divider to prevent overlock of SPI The divider should be rounded to the next full integer to ensure that the resulting SPI frequency is <= target frequency, i.e. the SPI is not overclocked. --- arch/risc-v/src/mpfs/mpfs_corespi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/risc-v/src/mpfs/mpfs_corespi.c b/arch/risc-v/src/mpfs/mpfs_corespi.c index 0c8d1624f1f22..8393666b176be 100644 --- a/arch/risc-v/src/mpfs/mpfs_corespi.c +++ b/arch/risc-v/src/mpfs/mpfs_corespi.c @@ -535,9 +535,9 @@ static uint32_t mpfs_spi_setfrequency(struct spi_dev_s *dev, priv->frequency = frequency; - /* Formula is SPICLK = PCLK/(2*(CFG_CLK + 1)) */ + /* Formula is SPICLK = PCLK/(2*(CFG_CLK + 1)) (result is rounded up) */ - divider = ((MPFS_FPGA_PERIPHERAL_CLK / frequency) >> 1) - 1; + divider = (MPFS_FPGA_PERIPHERAL_CLK / frequency) >> 1; priv->actual = MPFS_FPGA_PERIPHERAL_CLK / ((divider + 1) << 1); DEBUGASSERT(divider < 256u);