From dc8234245f21f89dc06ec99311baf71a8c3c1fd9 Mon Sep 17 00:00:00 2001 From: Ville Juven Date: Thu, 22 Feb 2024 16:59:38 +0200 Subject: [PATCH] arm64/imx9: Add GPIO, IOMUX and external interrupt support This adds memory mapped registers and drivers for digital I/O. --- arch/arm64/include/imx9/chip.h | 2 + arch/arm64/src/imx9/Kconfig | 4 + arch/arm64/src/imx9/Make.defs | 6 +- arch/arm64/src/imx9/chip.h | 2 + .../src/imx9/hardware/imx93/imx93_gpio.h | 59 ++ .../src/imx9/hardware/imx93/imx93_iomux.h | 604 +++++++++++++++++ .../src/imx9/hardware/imx93/imx93_pinmux.h | 634 ++++++++++++++++++ arch/arm64/src/imx9/hardware/imx9_gpio.h | 106 +++ arch/arm64/src/imx9/hardware/imx9_iomuxc.h | 104 +++ arch/arm64/src/imx9/hardware/imx9_pinmux.h | 36 + arch/arm64/src/imx9/imx9_gpio.c | 278 ++++++++ arch/arm64/src/imx9/imx9_gpio.h | 323 +++++++++ arch/arm64/src/imx9/imx9_gpiobase.c | 49 ++ arch/arm64/src/imx9/imx9_gpioirq.c | 356 ++++++++++ arch/arm64/src/imx9/imx9_iomuxc.c | 116 ++++ arch/arm64/src/imx9/imx9_iomuxc.h | 117 ++++ .../imx9/imx93-evk/configs/nsh/defconfig | 1 + 17 files changed, 2796 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h create mode 100644 arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h create mode 100644 arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h create mode 100644 arch/arm64/src/imx9/hardware/imx9_gpio.h create mode 100644 arch/arm64/src/imx9/hardware/imx9_iomuxc.h create mode 100644 arch/arm64/src/imx9/hardware/imx9_pinmux.h create mode 100644 arch/arm64/src/imx9/imx9_gpio.c create mode 100644 arch/arm64/src/imx9/imx9_gpio.h create mode 100644 arch/arm64/src/imx9/imx9_gpiobase.c create mode 100644 arch/arm64/src/imx9/imx9_gpioirq.c create mode 100644 arch/arm64/src/imx9/imx9_iomuxc.c create mode 100644 arch/arm64/src/imx9/imx9_iomuxc.h diff --git a/arch/arm64/include/imx9/chip.h b/arch/arm64/include/imx9/chip.h index b5b46f8ce1032..28553a96e2837 100644 --- a/arch/arm64/include/imx9/chip.h +++ b/arch/arm64/include/imx9/chip.h @@ -59,6 +59,8 @@ #define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xff) +#define IMX9_GPIO_NPORTS 4 + #endif /**************************************************************************** diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig index 3c921bbebe7c5..64a266865aa84 100644 --- a/arch/arm64/src/imx9/Kconfig +++ b/arch/arm64/src/imx9/Kconfig @@ -28,6 +28,10 @@ config IMX9_UART1 select UART1_SERIALDRIVER endmenu # iMX Peripheral Selection +config IMX9_GPIO_IRQ + bool "GPIO Interrupt Support" + default n + config IMX9_PLL bool "PLL setup support (WIP)" default n diff --git a/arch/arm64/src/imx9/Make.defs b/arch/arm64/src/imx9/Make.defs index 8e8a8d98623be..15128654abaed 100644 --- a/arch/arm64/src/imx9/Make.defs +++ b/arch/arm64/src/imx9/Make.defs @@ -22,7 +22,7 @@ include common/Make.defs # i.MX9-specific C source files -CHIP_CSRCS = imx9_boot.c imx9_ccm.c imx9_clockconfig.c +CHIP_CSRCS = imx9_boot.c imx9_ccm.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c ifeq ($(CONFIG_ARCH_CHIP_IMX93),y) CHIP_CSRCS += imx9_lpuart.c @@ -30,3 +30,7 @@ ifeq ($(CONFIG_ARCH_CHIP_IMX93),y) CHIP_ASRCS = imx93_lowputc.S endif endif + +ifeq ($(CONFIG_IMX9_GPIO_IRQ),y) + CHIP_CSRCS += imx9_gpioirq.c +endif diff --git a/arch/arm64/src/imx9/chip.h b/arch/arm64/src/imx9/chip.h index 691f795ed8f28..f9792f5518e30 100644 --- a/arch/arm64/src/imx9/chip.h +++ b/arch/arm64/src/imx9/chip.h @@ -29,6 +29,8 @@ #ifndef __ASSEMBLY__ # include +# include +# include #endif /**************************************************************************** diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h b/arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h new file mode 100644 index 0000000000000..e00856d6780ac --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h @@ -0,0 +1,59 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include "imx93_memorymap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */ +#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */ +#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */ +#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */ +#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */ +#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */ +#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */ +#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */ +#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */ +#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */ +#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */ +#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */ +#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */ +#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */ +#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */ +#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */ +#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */ +#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */ +#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_GPIO_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h b/arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h new file mode 100644 index 0000000000000..afa9b388f7832 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h @@ -0,0 +1,604 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_iomux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets */ + +#define IOMUXC_MUX_CTL_DAP_TDI_OFFSET (0x0000) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET (0x0004) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET (0x0008) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET (0x000C) +#define IOMUXC_MUX_CTL_GPIO_IO00_OFFSET (0x0010) +#define IOMUXC_MUX_CTL_GPIO_IO01_OFFSET (0x0014) +#define IOMUXC_MUX_CTL_GPIO_IO02_OFFSET (0x0018) +#define IOMUXC_MUX_CTL_GPIO_IO03_OFFSET (0x001C) +#define IOMUXC_MUX_CTL_GPIO_IO04_OFFSET (0x0020) +#define IOMUXC_MUX_CTL_GPIO_IO05_OFFSET (0x0024) +#define IOMUXC_MUX_CTL_GPIO_IO06_OFFSET (0x0028) +#define IOMUXC_MUX_CTL_GPIO_IO07_OFFSET (0x002C) +#define IOMUXC_MUX_CTL_GPIO_IO08_OFFSET (0x0030) +#define IOMUXC_MUX_CTL_GPIO_IO09_OFFSET (0x0034) +#define IOMUXC_MUX_CTL_GPIO_IO10_OFFSET (0x0038) +#define IOMUXC_MUX_CTL_GPIO_IO11_OFFSET (0x003C) +#define IOMUXC_MUX_CTL_GPIO_IO12_OFFSET (0x0040) +#define IOMUXC_MUX_CTL_GPIO_IO13_OFFSET (0x0044) +#define IOMUXC_MUX_CTL_GPIO_IO14_OFFSET (0x0048) +#define IOMUXC_MUX_CTL_GPIO_IO15_OFFSET (0x004C) +#define IOMUXC_MUX_CTL_GPIO_IO16_OFFSET (0x0050) +#define IOMUXC_MUX_CTL_GPIO_IO17_OFFSET (0x0054) +#define IOMUXC_MUX_CTL_GPIO_IO18_OFFSET (0x0058) +#define IOMUXC_MUX_CTL_GPIO_IO19_OFFSET (0x005C) +#define IOMUXC_MUX_CTL_GPIO_IO20_OFFSET (0x0060) +#define IOMUXC_MUX_CTL_GPIO_IO21_OFFSET (0x0064) +#define IOMUXC_MUX_CTL_GPIO_IO22_OFFSET (0x0068) +#define IOMUXC_MUX_CTL_GPIO_IO23_OFFSET (0x006C) +#define IOMUXC_MUX_CTL_GPIO_IO24_OFFSET (0x0070) +#define IOMUXC_MUX_CTL_GPIO_IO25_OFFSET (0x0074) +#define IOMUXC_MUX_CTL_GPIO_IO26_OFFSET (0x0078) +#define IOMUXC_MUX_CTL_GPIO_IO27_OFFSET (0x007C) +#define IOMUXC_MUX_CTL_GPIO_IO28_OFFSET (0x0080) +#define IOMUXC_MUX_CTL_GPIO_IO29_OFFSET (0x0084) +#define IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET (0x0088) +#define IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET (0x008C) +#define IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET (0x0090) +#define IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET (0x0094) +#define IOMUXC_MUX_CTL_ENET1_MDC_OFFSET (0x0098) +#define IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET (0x009C) +#define IOMUXC_MUX_CTL_ENET1_TD3_OFFSET (0x00A0) +#define IOMUXC_MUX_CTL_ENET1_TD2_OFFSET (0x00A4) +#define IOMUXC_MUX_CTL_ENET1_TD1_OFFSET (0x00A8) +#define IOMUXC_MUX_CTL_ENET1_TD0_OFFSET (0x00AC) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET (0x00B0) +#define IOMUXC_MUX_CTL_ENET1_TXC_OFFSET (0x00B4) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET (0x00B8) +#define IOMUXC_MUX_CTL_ENET1_RXC_OFFSET (0x00BC) +#define IOMUXC_MUX_CTL_ENET1_RD0_OFFSET (0x00C0) +#define IOMUXC_MUX_CTL_ENET1_RD1_OFFSET (0x00C4) +#define IOMUXC_MUX_CTL_ENET1_RD2_OFFSET (0x00C8) +#define IOMUXC_MUX_CTL_ENET1_RD3_OFFSET (0x00CC) +#define IOMUXC_MUX_CTL_ENET2_MDC_OFFSET (0x00D0) +#define IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET (0x00D4) +#define IOMUXC_MUX_CTL_ENET2_TD3_OFFSET (0x00D8) +#define IOMUXC_MUX_CTL_ENET2_TD2_OFFSET (0x00DC) +#define IOMUXC_MUX_CTL_ENET2_TD1_OFFSET (0x00E0) +#define IOMUXC_MUX_CTL_ENET2_TD0_OFFSET (0x00E4) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET (0x00E8) +#define IOMUXC_MUX_CTL_ENET2_TXC_OFFSET (0x00EC) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET (0x00F0) +#define IOMUXC_MUX_CTL_ENET2_RXC_OFFSET (0x00F4) +#define IOMUXC_MUX_CTL_ENET2_RD0_OFFSET (0x00F8) +#define IOMUXC_MUX_CTL_ENET2_RD1_OFFSET (0x00FC) +#define IOMUXC_MUX_CTL_ENET2_RD2_OFFSET (0x0100) +#define IOMUXC_MUX_CTL_ENET2_RD3_OFFSET (0x0104) +#define IOMUXC_MUX_CTL_SD1_CLK_OFFSET (0x0108) +#define IOMUXC_MUX_CTL_SD1_CMD_OFFSET (0x010C) +#define IOMUXC_MUX_CTL_SD1_DATA0_OFFSET (0x0110) +#define IOMUXC_MUX_CTL_SD1_DATA1_OFFSET (0x0114) +#define IOMUXC_MUX_CTL_SD1_DATA2_OFFSET (0x0118) +#define IOMUXC_MUX_CTL_SD1_DATA3_OFFSET (0x011C) +#define IOMUXC_MUX_CTL_SD1_DATA4_OFFSET (0x0120) +#define IOMUXC_MUX_CTL_SD1_DATA5_OFFSET (0x0124) +#define IOMUXC_MUX_CTL_SD1_DATA6_OFFSET (0x0128) +#define IOMUXC_MUX_CTL_SD1_DATA7_OFFSET (0x012C) +#define IOMUXC_MUX_CTL_SD1_STROBE_OFFSET (0x0130) +#define IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET (0x0134) +#define IOMUXC_MUX_CTL_SD3_CLK_OFFSET (0x0138) +#define IOMUXC_MUX_CTL_SD3_CMD_OFFSET (0x013C) +#define IOMUXC_MUX_CTL_SD3_DATA0_OFFSET (0x0140) +#define IOMUXC_MUX_CTL_SD3_DATA1_OFFSET (0x0144) +#define IOMUXC_MUX_CTL_SD3_DATA2_OFFSET (0x0148) +#define IOMUXC_MUX_CTL_SD3_DATA3_OFFSET (0x014C) +#define IOMUXC_MUX_CTL_SD2_CD_B_OFFSET (0x0150) +#define IOMUXC_MUX_CTL_SD2_CLK_OFFSET (0x0154) +#define IOMUXC_MUX_CTL_SD2_CMD_OFFSET (0x0158) +#define IOMUXC_MUX_CTL_SD2_DATA0_OFFSET (0x015C) +#define IOMUXC_MUX_CTL_SD2_DATA1_OFFSET (0x0160) +#define IOMUXC_MUX_CTL_SD2_DATA2_OFFSET (0x0164) +#define IOMUXC_MUX_CTL_SD2_DATA3_OFFSET (0x0168) +#define IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET (0x016C) +#define IOMUXC_MUX_CTL_I2C1_SCL_OFFSET (0x0170) +#define IOMUXC_MUX_CTL_I2C1_SDA_OFFSET (0x0174) +#define IOMUXC_MUX_CTL_I2C2_SCL_OFFSET (0x0178) +#define IOMUXC_MUX_CTL_I2C2_SDA_OFFSET (0x017C) +#define IOMUXC_MUX_CTL_UART1_RXD_OFFSET (0x0180) +#define IOMUXC_MUX_CTL_UART1_TXD_OFFSET (0x0184) +#define IOMUXC_MUX_CTL_UART2_RXD_OFFSET (0x0188) +#define IOMUXC_MUX_CTL_UART2_TXD_OFFSET (0x018C) +#define IOMUXC_MUX_CTL_PDM_CLK_OFFSET (0x0190) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET (0x0194) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET (0x0198) +#define IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET (0x019C) +#define IOMUXC_MUX_CTL_SAI1_TXC_OFFSET (0x01A0) +#define IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET (0x01A4) +#define IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET (0x01A8) +#define IOMUXC_MUX_CTL_WDOG_ANY_OFFSET (0x01AC) + +#define IOMUXC_PAD_CTL_DAP_TDI_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET (0x01B4) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET (0x01B8) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET (0x01BC) +#define IOMUXC_PAD_CTL_GPIO_IO00_OFFSET (0x01C0) +#define IOMUXC_PAD_CTL_GPIO_IO01_OFFSET (0x01C4) +#define IOMUXC_PAD_CTL_GPIO_IO02_OFFSET (0x01C8) +#define IOMUXC_PAD_CTL_GPIO_IO03_OFFSET (0x01CC) +#define IOMUXC_PAD_CTL_GPIO_IO04_OFFSET (0x01D0) +#define IOMUXC_PAD_CTL_GPIO_IO05_OFFSET (0x01D4) +#define IOMUXC_PAD_CTL_GPIO_IO06_OFFSET (0x01D8) +#define IOMUXC_PAD_CTL_GPIO_IO07_OFFSET (0x01DC) +#define IOMUXC_PAD_CTL_GPIO_IO08_OFFSET (0x01E0) +#define IOMUXC_PAD_CTL_GPIO_IO09_OFFSET (0x01E4) +#define IOMUXC_PAD_CTL_GPIO_IO10_OFFSET (0x01E8) +#define IOMUXC_PAD_CTL_GPIO_IO11_OFFSET (0x01EC) +#define IOMUXC_PAD_CTL_GPIO_IO12_OFFSET (0x01F0) +#define IOMUXC_PAD_CTL_GPIO_IO13_OFFSET (0x01F4) +#define IOMUXC_PAD_CTL_GPIO_IO14_OFFSET (0x01F8) +#define IOMUXC_PAD_CTL_GPIO_IO15_OFFSET (0x01FC) +#define IOMUXC_PAD_CTL_GPIO_IO16_OFFSET (0x0200) +#define IOMUXC_PAD_CTL_GPIO_IO17_OFFSET (0x0204) +#define IOMUXC_PAD_CTL_GPIO_IO18_OFFSET (0x0208) +#define IOMUXC_PAD_CTL_GPIO_IO19_OFFSET (0x020C) +#define IOMUXC_PAD_CTL_GPIO_IO20_OFFSET (0x0210) +#define IOMUXC_PAD_CTL_GPIO_IO21_OFFSET (0x0214) +#define IOMUXC_PAD_CTL_GPIO_IO22_OFFSET (0x0218) +#define IOMUXC_PAD_CTL_GPIO_IO23_OFFSET (0x021C) +#define IOMUXC_PAD_CTL_GPIO_IO24_OFFSET (0x0220) +#define IOMUXC_PAD_CTL_GPIO_IO25_OFFSET (0x0224) +#define IOMUXC_PAD_CTL_GPIO_IO26_OFFSET (0x0228) +#define IOMUXC_PAD_CTL_GPIO_IO27_OFFSET (0x022C) +#define IOMUXC_PAD_CTL_GPIO_IO28_OFFSET (0x0230) +#define IOMUXC_PAD_CTL_GPIO_IO29_OFFSET (0x0234) +#define IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET (0x0238) +#define IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET (0x023C) +#define IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET (0x0240) +#define IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET (0x0244) +#define IOMUXC_PAD_CTL_ENET1_MDC_OFFSET (0x0248) +#define IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET (0x024C) +#define IOMUXC_PAD_CTL_ENET1_TD3_OFFSET (0x0250) +#define IOMUXC_PAD_CTL_ENET1_TD2_OFFSET (0x0254) +#define IOMUXC_PAD_CTL_ENET1_TD1_OFFSET (0x0258) +#define IOMUXC_PAD_CTL_ENET1_TD0_OFFSET (0x025C) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET (0x0260) +#define IOMUXC_PAD_CTL_ENET1_TXC_OFFSET (0x0264) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET (0x0268) +#define IOMUXC_PAD_CTL_ENET1_RXC_OFFSET (0x026C) +#define IOMUXC_PAD_CTL_ENET1_RD0_OFFSET (0x0270) +#define IOMUXC_PAD_CTL_ENET1_RD1_OFFSET (0x0274) +#define IOMUXC_PAD_CTL_ENET1_RD2_OFFSET (0x0278) +#define IOMUXC_PAD_CTL_ENET1_RD3_OFFSET (0x027C) +#define IOMUXC_PAD_CTL_ENET2_MDC_OFFSET (0x0280) +#define IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET (0x0284) +#define IOMUXC_PAD_CTL_ENET2_TD3_OFFSET (0x0288) +#define IOMUXC_PAD_CTL_ENET2_TD2_OFFSET (0x028C) +#define IOMUXC_PAD_CTL_ENET2_TD1_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TD0_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET (0x01B0) +#define IOMUXC_PAD_CTL_ENET2_TXC_OFFSET (0x029C) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET (0x02A0) +#define IOMUXC_PAD_CTL_ENET2_RXC_OFFSET (0x02A4) +#define IOMUXC_PAD_CTL_ENET2_RD0_OFFSET (0x02A8) +#define IOMUXC_PAD_CTL_ENET2_RD1_OFFSET (0x02AC) +#define IOMUXC_PAD_CTL_ENET2_RD2_OFFSET (0x02B0) +#define IOMUXC_PAD_CTL_ENET2_RD3_OFFSET (0x02B4) +#define IOMUXC_PAD_CTL_SD1_CLK_OFFSET (0x02B8) +#define IOMUXC_PAD_CTL_SD1_CMD_OFFSET (0x02BC) +#define IOMUXC_PAD_CTL_SD1_DATA0_OFFSET (0x02C0) +#define IOMUXC_PAD_CTL_SD1_DATA1_OFFSET (0x02C4) +#define IOMUXC_PAD_CTL_SD1_DATA2_OFFSET (0x02C8) +#define IOMUXC_PAD_CTL_SD1_DATA3_OFFSET (0x02CC) +#define IOMUXC_PAD_CTL_SD1_DATA4_OFFSET (0x02D0) +#define IOMUXC_PAD_CTL_SD1_DATA5_OFFSET (0x02D4) +#define IOMUXC_PAD_CTL_SD1_DATA6_OFFSET (0x02D8) +#define IOMUXC_PAD_CTL_SD1_DATA7_OFFSET (0x02DC) +#define IOMUXC_PAD_CTL_SD1_STROBE_OFFSET (0x02E0) +#define IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET (0x02E4) +#define IOMUXC_PAD_CTL_SD3_CLK_OFFSET (0x02E8) +#define IOMUXC_PAD_CTL_SD3_CMD_OFFSET (0x02EC) +#define IOMUXC_PAD_CTL_SD3_DATA0_OFFSET (0x02F0) +#define IOMUXC_PAD_CTL_SD3_DATA1_OFFSET (0x02F4) +#define IOMUXC_PAD_CTL_SD3_DATA2_OFFSET (0x02F8) +#define IOMUXC_PAD_CTL_SD3_DATA3_OFFSET (0x02FC) +#define IOMUXC_PAD_CTL_SD2_CD_B_OFFSET (0x0300) +#define IOMUXC_PAD_CTL_SD2_CLK_OFFSET (0x0304) +#define IOMUXC_PAD_CTL_SD2_CMD_OFFSET (0x0308) +#define IOMUXC_PAD_CTL_SD2_DATA0_OFFSET (0x030C) +#define IOMUXC_PAD_CTL_SD2_DATA1_OFFSET (0x0310) +#define IOMUXC_PAD_CTL_SD2_DATA2_OFFSET (0x0314) +#define IOMUXC_PAD_CTL_SD2_DATA3_OFFSET (0x0318) +#define IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET (0x031C) +#define IOMUXC_PAD_CTL_I2C1_SCL_OFFSET (0x0320) +#define IOMUXC_PAD_CTL_I2C1_SDA_OFFSET (0x0324) +#define IOMUXC_PAD_CTL_I2C2_SCL_OFFSET (0x0328) +#define IOMUXC_PAD_CTL_I2C2_SDA_OFFSET (0x032C) +#define IOMUXC_PAD_CTL_UART1_RXD_OFFSET (0x0330) +#define IOMUXC_PAD_CTL_UART1_TXD_OFFSET (0x0334) +#define IOMUXC_PAD_CTL_UART2_RXD_OFFSET (0x0338) +#define IOMUXC_PAD_CTL_UART2_TXD_OFFSET (0x033C) +#define IOMUXC_PAD_CTL_PDM_CLK_OFFSET (0x0340) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET (0x0344) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET (0x0348) +#define IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET (0x034C) +#define IOMUXC_PAD_CTL_SAI1_TXC_OFFSET (0x0350) +#define IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET (0x0354) +#define IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET (0x0358) +#define IOMUXC_PAD_CTL_WDOG_ANY_OFFSET (0x035C) + +#define CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0360) +#define CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET (0x0364) +#define CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT_OFFSET (0x0368) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET (0x036C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET (0x0370) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET (0x0374) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET (0x0378) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET (0x037C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET (0x0380) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET (0x0384) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET (0x0388) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET (0x038C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET (0x0390) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET (0x0394) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET (0x0398) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET (0x039C) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET (0x03A0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET (0x03A4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET (0x03A8) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET (0x03AC) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET (0x03B0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET (0x03B4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET (0x03B8) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET (0x03BC) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET (0x03C0) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET (0x03C4) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET (0x03C8) +#define I3C2_PIN_SCL_IN_SELECT_INPUT_OFFSET (0x03CC) +#define I3C2_PIN_SDA_IN_SELECT_INPUT_OFFSET (0x03D0) +#define JTAG_MUX_TCK_SELECT_INPUT_OFFSET (0x03D4) +#define JTAG_MUX_TDI_SELECT_INPUT_OFFSET (0x03D8) +#define JTAG_MUX_TMS_SELECT_INPUT_OFFSET (0x03DC) +#define LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03E0) +#define LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03E4) +#define LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03E8) +#define LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03EC) +#define LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03F0) +#define LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03F4) +#define LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x03F8) +#define LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x03FC) +#define LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET (0x0400) +#define LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET (0x0404) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O_OFFSET (0x0408) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET (0x040C) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET (0x0410) +#define LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x0414) +#define LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0418) +#define LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x041C) +#define LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x0420) +#define LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0424) +#define LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0428) +#define LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET (0x042C) +#define LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET (0x0430) +#define LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET (0x0434) +#define SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET (0x0448) +#define SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET (0x044c) +#define SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET (0x0450) +#define SPDIF_SPDIF_I_SELECT_INPUT_OFFSET (0x0454) +#define USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET (0x0458) +#define USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET (0x045C) +#define USDHC3_IPP_DATO_IN_SELECT_INPUT_OFFSET (0x0460) +#define USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET (0x0464) +#define USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET (0x0468) +#define USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET (0x046C) + +/* Register addresses */ + +#define IOMUXC_MUX_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDI_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_MUX_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_MUX_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_MUX_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_MUX_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_MUX_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_MUX_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_MUX_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CLK_OFFSET) +#define IOMUXC_MUX_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_CMD_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_MUX_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_MUX_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_MUX_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_MUX_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART1_TXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_RXD_OFFSET) +#define IOMUXC_MUX_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_UART2_TXD_OFFSET) +#define IOMUXC_MUX_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_CLK_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_MUX_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_MUX_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_MUX_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_MUX_CTL_WDOG_ANY_OFFSET) + +#define IOMUXC_PAD_CTL_DAP_TDI (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDI_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TMS_SWDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TMS_SWDIO_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TCLK_SWCLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TCLK_SWCLK_OFFSET) +#define IOMUXC_PAD_CTL_DAP_TDO_TRACESWO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_DAP_TDO_TRACESWO_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO00 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO00_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO01 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO01_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO02 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO02_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO03 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO03_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO04 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO04_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO05 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO05_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO06 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO06_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO07 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO07_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO08 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO08_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO09 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO09_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO10 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO10_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO11 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO11_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO12 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO12_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO13 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO13_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO14 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO14_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO15 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO15_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO16 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO16_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO17 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO17_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO18 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO18_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO19 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO19_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO20 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO20_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO21 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO21_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO22 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO22_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO23 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO23_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO24 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO24_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO25 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO25_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO26 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO26_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO27 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO27_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO28 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO28_OFFSET) +#define IOMUXC_PAD_CTL_GPIO_IO29 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_GPIO_IO29_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO1_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO2_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO3_OFFSET) +#define IOMUXC_PAD_CTL_CCM_CLKO4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_CCM_CLKO4_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET1_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET1_RD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_MDIO (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_MDIO_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD3_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_TXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RX_CTL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RX_CTL_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RXC_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD0_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD1_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD2_OFFSET) +#define IOMUXC_PAD_CTL_ENET2_RD3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_ENET2_RD3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD1_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA4 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA4_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA5 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA5_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA6 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA6_OFFSET) +#define IOMUXC_PAD_CTL_SD1_DATA7 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_DATA7_OFFSET) +#define IOMUXC_PAD_CTL_SD1_STROBE (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD1_STROBE_OFFSET) +#define IOMUXC_PAD_CTL_SD2_VSELECT (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_VSELECT_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD3_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD3_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD3_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CD_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CD_B_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CLK_OFFSET) +#define IOMUXC_PAD_CTL_SD2_CMD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_CMD_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA0_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA1_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA2 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA2_OFFSET) +#define IOMUXC_PAD_CTL_SD2_DATA3 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_DATA3_OFFSET) +#define IOMUXC_PAD_CTL_SD2_RESET_B (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SD2_RESET_B_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C1_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C1_SDA_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SCL (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SCL_OFFSET) +#define IOMUXC_PAD_CTL_I2C2_SDA (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_I2C2_SDA_OFFSET) +#define IOMUXC_PAD_CTL_UART1_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART1_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART1_TXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_RXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_RXD_OFFSET) +#define IOMUXC_PAD_CTL_UART2_TXD (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_UART2_TXD_OFFSET) +#define IOMUXC_PAD_CTL_PDM_CLK (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_CLK_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM0_OFFSET) +#define IOMUXC_PAD_CTL_PDM_BIT_STREAM1 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_PDM_BIT_STREAM1_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXFS (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXFS_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXC (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXC_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_TXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_TXD0_OFFSET) +#define IOMUXC_PAD_CTL_SAI1_RXD0 (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_SAI1_RXD0_OFFSET) +#define IOMUXC_PAD_CTL_WDOG_ANY (IMX9_IOMUXC1_BASE + IOMUXC_PAD_CTL_WDOG_ANY_OFFSET) + +#define CAN1_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + CAN1_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define CAN2_IPP_IND_CANRX_SELECT_INPUT (IMX9_IOMUXC1_BASE + CAN2_IPP_IND_CANRX_SELECT_INPUT_OFFSET) +#define CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + CCMSRCGPCMIX_EXT1_CLK_SELECT_INPUT_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_0_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_1_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_2_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_3_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_4_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_5_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_6_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_7_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_8_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_9_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_10_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_11_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_13_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_14_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_15_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_16_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_17_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_18_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_20_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_22_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_23_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_24_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_25_OFFSET) +#define FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27 (IMX9_IOMUXC1_BASE + FLEXIO1_IPP_IND_FLEXIO_SELECT_INPUT_27_OFFSET) +#define I3C2_PIN_SCL_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + 13C2_PIN_SCL_IN_SELECT_INPUT_OFFSET) +#define I3C2_PIN_SDA_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + 13C2_PIN_SDA_IN_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TCK_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TCK_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TDI_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TDI_SELECT_INPUT_OFFSET) +#define JTAG_MUX_TMS_SELECT_INPUT (IMX9_IOMUXC1_BASE + JTAG_MUX_TMS_SELECT_INPUT_OFFSET) +#define LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C3_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI12C3_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C5_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LP12C5_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C7_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C7_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C8_IPP_IND_LPI2C_SCL_SELECT_INPUT_OFFSET) +#define LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPI2C8_IPP_IND_LPI2C_SDA_SELECT_INPUT_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_O_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1 (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_1_OFFSET) +#define LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2 (IMX9_IOMUXC1_BASE + LPTMR2_IPP_IND_LPTIMER_SELECT_INPUT_2_OFFSET) +#define LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_CTS_N_SELECT_INP_OFFSET) +#define LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_RXD_SELECT_INPUT_OFFSET) +#define LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT (IMX9_IOMUXC1_BASE + LPUARTS_IPP_IND_LPUART_TXD_SELECT_INPUT_OFFSET) +#define SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI1_IPP_IND_SAI_MCLK_SELECT_INPUT_OFFSET) +#define SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT_OFFSET) +#define SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT (IMX9_IOMUXC1_BASE + SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT_OFFSET) +#define SPDIF_SPDIF_I_SELECT_INPUT (IMX9_IOMUXC1_BASE + SPDIF_SPDIF_I_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_CARD_CLK_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_CMD_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_CMD_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DATO_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DATO_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT1_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT1_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT2_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT2_IN_SELECT_INPUT_OFFSET) +#define USDHC3_IPP_DAT3_IN_SELECT_INPUT (IMX9_IOMUXC1_BASE + USDHC3_IPP_DAT3_IN_SELECT_INPUT_OFFSET) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_IOMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h b/arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h new file mode 100644 index 0000000000000..2a3487d98530a --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h @@ -0,0 +1,634 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx93/imx93_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H + +#define IOMUXC_PAD_DAP_TDI_JTAG_MUX_TDI IOMUX_PADCFG(0x443c0000, 0x0, 0x443c03d8, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_MQS2_LEFT IOMUX_PADCFG(0x443c0000, 0x1, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_CAN2_TX IOMUX_PADCFG(0x443c0000, 0x3, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_FLEXIO2_FLEXIO30 IOMUX_PADCFG(0x443c0000, 0x4, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_GPIO3_IO28 IOMUX_PADCFG(0x443c0000, 0x5, 0x00000000, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TDI_LPUART5_RX IOMUX_PADCFG(0x443c0000, 0x6, 0x443c0430, 0x00000000, 0x443c01b0) +#define IOMUXC_PAD_DAP_TMS_SWDIO_JTAG_MUX_TMS IOMUX_PADCFG(0x443c0004, 0x0, 0x443c03dc, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_FLEXIO2_FLEXIO31 IOMUX_PADCFG(0x443c0004, 0x4, 0x00000000, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_GPIO3_IO29 IOMUX_PADCFG(0x443c0004, 0x5, 0x00000000, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TMS_SWDIO_LPUART5_RTS_B IOMUX_PADCFG(0x443c0004, 0x6, 0x00000000, 0x00000000, 0x443c01b4) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_JTAG_MUX_TCK IOMUX_PADCFG(0x443c0008, 0x0, 0x443c03d4, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_FLEXIO1_FLEXIO30 IOMUX_PADCFG(0x443c0008, 0x4, 0x00000000, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_GPIO3_IO30 IOMUX_PADCFG(0x443c0008, 0x5, 0x00000000, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TCLK_SWCLK_LPUART5_CTS_B IOMUX_PADCFG(0x443c0008, 0x6, 0x443c042c, 0x00000000, 0x443c01b8) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_JTAG_MUX_TDO IOMUX_PADCFG(0x443c000c, 0x0, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_MQS2_RIGHT IOMUX_PADCFG(0x443c000c, 0x1, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_CAN2_RX IOMUX_PADCFG(0x443c000c, 0x3, 0x443c0364, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_FLEXIO1_FLEXIO31 IOMUX_PADCFG(0x443c000c, 0x4, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_GPIO3_IO31 IOMUX_PADCFG(0x443c000c, 0x5, 0x00000000, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_DAP_TDO_TRACESWO_LPUART5_TX IOMUX_PADCFG(0x443c000c, 0x6, 0x443c0434, 0x00000000, 0x443c01bc) +#define IOMUXC_PAD_GPIO_IO00_GPIO2_IO00 IOMUX_PADCFG(0x443c0010, 0x0, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPI2C3_SDA IOMUX_PADCFG(0x443c0010, 0x1, 0x443c03e4, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_MEDIAMIX_CAM_CLK IOMUX_PADCFG(0x443c0010, 0x2, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_MEDIAMIX_DISP_CLK IOMUX_PADCFG(0x443c0010, 0x3, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPSPI6_PCS0 IOMUX_PADCFG(0x443c0010, 0x4, 0x00000000, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPUART5_TX IOMUX_PADCFG(0x443c0010, 0x5, 0x443c0434, 0x00000001, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_LPI2C5_SDA IOMUX_PADCFG(0x443c0010, 0x6, 0x443c03ec, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO00_FLEXIO1_FLEXIO00 IOMUX_PADCFG(0x443c0010, 0x7, 0x443c036c, 0x00000000, 0x443c01c0) +#define IOMUXC_PAD_GPIO_IO01_GPIO2_IO01 IOMUX_PADCFG(0x443c0014, 0x0, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPI2C3_SCL IOMUX_PADCFG(0x443c0014, 0x1, 0x443c03e0, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_MEDIAMIX_CAM_DATA00 IOMUX_PADCFG(0x443c0014, 0x2, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_MEDIAMIX_DISP_DE IOMUX_PADCFG(0x443c0014, 0x3, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPSPI6_SIN IOMUX_PADCFG(0x443c0014, 0x4, 0x00000000, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPUART5_RX IOMUX_PADCFG(0x443c0014, 0x5, 0x443c0430, 0x00000001, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_LPI2C5_SCL IOMUX_PADCFG(0x443c0014, 0x6, 0x443c03e8, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO01_FLEXIO1_FLEXIO01 IOMUX_PADCFG(0x443c0014, 0x7, 0x443c0370, 0x00000000, 0x443c01c4) +#define IOMUXC_PAD_GPIO_IO02_GPIO2_IO02 IOMUX_PADCFG(0x443c0018, 0x0, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPI2C4_SDA IOMUX_PADCFG(0x443c0018, 0x1, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_MEDIAMIX_CAM_VSYNC IOMUX_PADCFG(0x443c0018, 0x2, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_MEDIAMIX_DISP_VSYNC IOMUX_PADCFG(0x443c0018, 0x3, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPSPI6_SOUT IOMUX_PADCFG(0x443c0018, 0x4, 0x00000000, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPUART5_CTS_B IOMUX_PADCFG(0x443c0018, 0x5, 0x443c042c, 0x00000001, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_LPI2C6_SDA IOMUX_PADCFG(0x443c0018, 0x6, 0x443c03f4, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO02_FLEXIO1_FLEXIO02 IOMUX_PADCFG(0x443c0018, 0x7, 0x443c0374, 0x00000000, 0x443c01c8) +#define IOMUXC_PAD_GPIO_IO03_GPIO2_IO03 IOMUX_PADCFG(0x443c001c, 0x0, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPI2C4_SCL IOMUX_PADCFG(0x443c001c, 0x1, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_MEDIAMIX_CAM_HSYNC IOMUX_PADCFG(0x443c001c, 0x2, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_MEDIAMIX_DISP_HSYNC IOMUX_PADCFG(0x443c001c, 0x3, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPSPI6_SCK IOMUX_PADCFG(0x443c001c, 0x4, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPUART5_RTS_B IOMUX_PADCFG(0x443c001c, 0x5, 0x00000000, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_LPI2C6_SCL IOMUX_PADCFG(0x443c001c, 0x6, 0x443c03f0, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO03_FLEXIO1_FLEXIO03 IOMUX_PADCFG(0x443c001c, 0x7, 0x443c0378, 0x00000000, 0x443c01cc) +#define IOMUXC_PAD_GPIO_IO04_GPIO2_IO04 IOMUX_PADCFG(0x443c0020, 0x0, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_TPM3_CH0 IOMUX_PADCFG(0x443c0020, 0x1, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_PDM_CLK IOMUX_PADCFG(0x443c0020, 0x2, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_MEDIAMIX_DISP_DATA00 IOMUX_PADCFG(0x443c0020, 0x3, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_LPSPI7_PCS0 IOMUX_PADCFG(0x443c0020, 0x4, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_LPUART6_TX IOMUX_PADCFG(0x443c0020, 0x5, 0x00000000, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_LPI2C6_SDA IOMUX_PADCFG(0x443c0020, 0x6, 0x443c03f4, 0x00000001, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO04_FLEXIO1_FLEXIO04 IOMUX_PADCFG(0x443c0020, 0x7, 0x443c037c, 0x00000000, 0x443c01d0) +#define IOMUXC_PAD_GPIO_IO05_GPIO2_IO05 IOMUX_PADCFG(0x443c0024, 0x0, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_TPM4_CH0 IOMUX_PADCFG(0x443c0024, 0x1, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_PDM_BIT_STREAM00 IOMUX_PADCFG(0x443c0024, 0x2, 0x443c0438, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_MEDIAMIX_DISP_DATA01 IOMUX_PADCFG(0x443c0024, 0x3, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_LPSPI7_SIN IOMUX_PADCFG(0x443c0024, 0x4, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_LPUART6_RX IOMUX_PADCFG(0x443c0024, 0x5, 0x00000000, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_LPI2C6_SCL IOMUX_PADCFG(0x443c0024, 0x6, 0x443c03f0, 0x00000001, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO05_FLEXIO1_FLEXIO05 IOMUX_PADCFG(0x443c0024, 0x7, 0x443c0380, 0x00000000, 0x443c01d4) +#define IOMUXC_PAD_GPIO_IO06_GPIO2_IO06 IOMUX_PADCFG(0x443c0028, 0x0, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_TPM5_CH0 IOMUX_PADCFG(0x443c0028, 0x1, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_PDM_BIT_STREAM01 IOMUX_PADCFG(0x443c0028, 0x2, 0x443c043c, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_MEDIAMIX_DISP_DATA02 IOMUX_PADCFG(0x443c0028, 0x3, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_LPSPI7_SOUT IOMUX_PADCFG(0x443c0028, 0x4, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_LPUART6_CTS_B IOMUX_PADCFG(0x443c0028, 0x5, 0x00000000, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_LPI2C7_SDA IOMUX_PADCFG(0x443c0028, 0x6, 0x443c03fc, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO06_FLEXIO1_FLEXIO06 IOMUX_PADCFG(0x443c0028, 0x7, 0x443c0384, 0x00000000, 0x443c01d8) +#define IOMUXC_PAD_GPIO_IO07_GPIO2_IO07 IOMUX_PADCFG(0x443c002c, 0x0, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPSPI3_PCS1 IOMUX_PADCFG(0x443c002c, 0x1, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_MEDIAMIX_CAM_DATA01 IOMUX_PADCFG(0x443c002c, 0x2, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_MEDIAMIX_DISP_DATA03 IOMUX_PADCFG(0x443c002c, 0x3, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPSPI7_SCK IOMUX_PADCFG(0x443c002c, 0x4, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPUART6_RTS_B IOMUX_PADCFG(0x443c002c, 0x5, 0x00000000, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_LPI2C7_SCL IOMUX_PADCFG(0x443c002c, 0x6, 0x443c03f8, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO07_FLEXIO1_FLEXIO07 IOMUX_PADCFG(0x443c002c, 0x7, 0x443c0388, 0x00000000, 0x443c01dc) +#define IOMUXC_PAD_GPIO_IO08_GPIO2_IO08 IOMUX_PADCFG(0x443c0030, 0x0, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_LPSPI3_PCS0 IOMUX_PADCFG(0x443c0030, 0x1, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_MEDIAMIX_CAM_DATA02 IOMUX_PADCFG(0x443c0030, 0x2, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_MEDIAMIX_DISP_DATA04 IOMUX_PADCFG(0x443c0030, 0x3, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_TPM6_CH0 IOMUX_PADCFG(0x443c0030, 0x4, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_LPUART7_TX IOMUX_PADCFG(0x443c0030, 0x5, 0x00000000, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_LPI2C7_SDA IOMUX_PADCFG(0x443c0030, 0x6, 0x443c03fc, 0x00000001, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO08_FLEXIO1_FLEXIO08 IOMUX_PADCFG(0x443c0030, 0x7, 0x443c038c, 0x00000000, 0x443c01e0) +#define IOMUXC_PAD_GPIO_IO09_GPIO2_IO09 IOMUX_PADCFG(0x443c0034, 0x0, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_LPSPI3_SIN IOMUX_PADCFG(0x443c0034, 0x1, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_MEDIAMIX_CAM_DATA03 IOMUX_PADCFG(0x443c0034, 0x2, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_MEDIAMIX_DISP_DATA05 IOMUX_PADCFG(0x443c0034, 0x3, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_TPM3_EXTCLK IOMUX_PADCFG(0x443c0034, 0x4, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_LPUART7_RX IOMUX_PADCFG(0x443c0034, 0x5, 0x00000000, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_LPI2C7_SCL IOMUX_PADCFG(0x443c0034, 0x6, 0x443c03f8, 0x00000001, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO09_FLEXIO1_FLEXIO09 IOMUX_PADCFG(0x443c0034, 0x7, 0x443c0390, 0x00000000, 0x443c01e4) +#define IOMUXC_PAD_GPIO_IO10_GPIO2_IO10 IOMUX_PADCFG(0x443c0038, 0x0, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_LPSPI3_SOUT IOMUX_PADCFG(0x443c0038, 0x1, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_MEDIAMIX_CAM_DATA04 IOMUX_PADCFG(0x443c0038, 0x2, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_MEDIAMIX_DISP_DATA06 IOMUX_PADCFG(0x443c0038, 0x3, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_TPM4_EXTCLK IOMUX_PADCFG(0x443c0038, 0x4, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_LPUART7_CTS_B IOMUX_PADCFG(0x443c0038, 0x5, 0x00000000, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_LPI2C8_SDA IOMUX_PADCFG(0x443c0038, 0x6, 0x443c0404, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO10_FLEXIO1_FLEXIO10 IOMUX_PADCFG(0x443c0038, 0x7, 0x443c0394, 0x00000000, 0x443c01e8) +#define IOMUXC_PAD_GPIO_IO11_GPIO2_IO11 IOMUX_PADCFG(0x443c003c, 0x0, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_LPSPI3_SCK IOMUX_PADCFG(0x443c003c, 0x1, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_MEDIAMIX_CAM_DATA05 IOMUX_PADCFG(0x443c003c, 0x2, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_MEDIAMIX_DISP_DATA07 IOMUX_PADCFG(0x443c003c, 0x3, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_TPM5_EXTCLK IOMUX_PADCFG(0x443c003c, 0x4, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_LPUART7_RTS_B IOMUX_PADCFG(0x443c003c, 0x5, 0x00000000, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_LPI2C8_SCL IOMUX_PADCFG(0x443c003c, 0x6, 0x443c0400, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO11_FLEXIO1_FLEXIO11 IOMUX_PADCFG(0x443c003c, 0x7, 0x443c0398, 0x00000000, 0x443c01ec) +#define IOMUXC_PAD_GPIO_IO12_GPIO2_IO12 IOMUX_PADCFG(0x443c0040, 0x0, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_TPM3_CH2 IOMUX_PADCFG(0x443c0040, 0x1, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_PDM_BIT_STREAM02 IOMUX_PADCFG(0x443c0040, 0x2, 0x443c0440, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_MEDIAMIX_DISP_DATA08 IOMUX_PADCFG(0x443c0040, 0x3, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_LPSPI8_PCS0 IOMUX_PADCFG(0x443c0040, 0x4, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_LPUART8_TX IOMUX_PADCFG(0x443c0040, 0x5, 0x00000000, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_LPI2C8_SDA IOMUX_PADCFG(0x443c0040, 0x6, 0x443c0404, 0x00000001, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO12_SAI3_RX_SYNC IOMUX_PADCFG(0x443c0040, 0x7, 0x443c0450, 0x00000000, 0x443c01f0) +#define IOMUXC_PAD_GPIO_IO13_GPIO2_IO13 IOMUX_PADCFG(0x443c0044, 0x0, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_TPM4_CH2 IOMUX_PADCFG(0x443c0044, 0x1, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_PDM_BIT_STREAM03 IOMUX_PADCFG(0x443c0044, 0x2, 0x443c0444, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_MEDIAMIX_DISP_DATA09 IOMUX_PADCFG(0x443c0044, 0x3, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_LPSPI8_SIN IOMUX_PADCFG(0x443c0044, 0x4, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_LPUART8_RX IOMUX_PADCFG(0x443c0044, 0x5, 0x00000000, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_LPI2C8_SCL IOMUX_PADCFG(0x443c0044, 0x6, 0x443c0400, 0x00000001, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO13_FLEXIO1_FLEXIO13 IOMUX_PADCFG(0x443c0044, 0x7, 0x443c039c, 0x00000000, 0x443c01f4) +#define IOMUXC_PAD_GPIO_IO14_GPIO2_IO14 IOMUX_PADCFG(0x443c0048, 0x0, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART3_TX IOMUX_PADCFG(0x443c0048, 0x1, 0x443c041c, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_MEDIAMIX_CAM_DATA06 IOMUX_PADCFG(0x443c0048, 0x2, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_MEDIAMIX_DISP_DATA10 IOMUX_PADCFG(0x443c0048, 0x3, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPSPI8_SOUT IOMUX_PADCFG(0x443c0048, 0x4, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART8_CTS_B IOMUX_PADCFG(0x443c0048, 0x5, 0x00000000, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_LPUART4_TX IOMUX_PADCFG(0x443c0048, 0x6, 0x443c0428, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO14_FLEXIO1_FLEXIO14 IOMUX_PADCFG(0x443c0048, 0x7, 0x443c03a0, 0x00000000, 0x443c01f8) +#define IOMUXC_PAD_GPIO_IO15_GPIO2_IO15 IOMUX_PADCFG(0x443c004c, 0x0, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART3_RX IOMUX_PADCFG(0x443c004c, 0x1, 0x443c0418, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_MEDIAMIX_CAM_DATA07 IOMUX_PADCFG(0x443c004c, 0x2, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_MEDIAMIX_DISP_DATA11 IOMUX_PADCFG(0x443c004c, 0x3, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPSPI8_SCK IOMUX_PADCFG(0x443c004c, 0x4, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART8_RTS_B IOMUX_PADCFG(0x443c004c, 0x5, 0x00000000, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_LPUART4_RX IOMUX_PADCFG(0x443c004c, 0x6, 0x443c0424, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO15_FLEXIO1_FLEXIO15 IOMUX_PADCFG(0x443c004c, 0x7, 0x443c03a4, 0x00000000, 0x443c01fc) +#define IOMUXC_PAD_GPIO_IO16_GPIO2_IO16 IOMUX_PADCFG(0x443c0050, 0x0, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_SAI3_TX_BCLK IOMUX_PADCFG(0x443c0050, 0x1, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_PDM_BIT_STREAM02 IOMUX_PADCFG(0x443c0050, 0x2, 0x443c0440, 0x00000001, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_MEDIAMIX_DISP_DATA12 IOMUX_PADCFG(0x443c0050, 0x3, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_LPUART3_CTS_B IOMUX_PADCFG(0x443c0050, 0x4, 0x443c0414, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_LPSPI4_PCS2 IOMUX_PADCFG(0x443c0050, 0x5, 0x00000000, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_LPUART4_CTS_B IOMUX_PADCFG(0x443c0050, 0x6, 0x443c0420, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO16_FLEXIO1_FLEXIO16 IOMUX_PADCFG(0x443c0050, 0x7, 0x443c03a8, 0x00000000, 0x443c0200) +#define IOMUXC_PAD_GPIO_IO17_GPIO2_IO17 IOMUX_PADCFG(0x443c0054, 0x0, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_SAI3_MCLK IOMUX_PADCFG(0x443c0054, 0x1, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_MEDIAMIX_CAM_DATA08 IOMUX_PADCFG(0x443c0054, 0x2, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_MEDIAMIX_DISP_DATA13 IOMUX_PADCFG(0x443c0054, 0x3, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_LPUART3_RTS_B IOMUX_PADCFG(0x443c0054, 0x4, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_LPSPI4_PCS1 IOMUX_PADCFG(0x443c0054, 0x5, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_LPUART4_RTS_B IOMUX_PADCFG(0x443c0054, 0x6, 0x00000000, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO17_FLEXIO1_FLEXIO17 IOMUX_PADCFG(0x443c0054, 0x7, 0x443c03ac, 0x00000000, 0x443c0204) +#define IOMUXC_PAD_GPIO_IO18_GPIO2_IO18 IOMUX_PADCFG(0x443c0058, 0x0, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_SAI3_RX_BCLK IOMUX_PADCFG(0x443c0058, 0x1, 0x443c044c, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_MEDIAMIX_CAM_DATA09 IOMUX_PADCFG(0x443c0058, 0x2, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_MEDIAMIX_DISP_DATA14 IOMUX_PADCFG(0x443c0058, 0x3, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_LPSPI5_PCS0 IOMUX_PADCFG(0x443c0058, 0x4, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_LPSPI4_PCS0 IOMUX_PADCFG(0x443c0058, 0x5, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_TPM5_CH2 IOMUX_PADCFG(0x443c0058, 0x6, 0x00000000, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO18_FLEXIO1_FLEXIO18 IOMUX_PADCFG(0x443c0058, 0x7, 0x443c03b0, 0x00000000, 0x443c0208) +#define IOMUXC_PAD_GPIO_IO19_GPIO2_IO19 IOMUX_PADCFG(0x443c005c, 0x0, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_SAI3_RX_SYNC IOMUX_PADCFG(0x443c005c, 0x1, 0x443c0450, 0x00000001, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_PDM_BIT_STREAM03 IOMUX_PADCFG(0x443c005c, 0x2, 0x443c0444, 0x00000001, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_MEDIAMIX_DISP_DATA15 IOMUX_PADCFG(0x443c005c, 0x3, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_LPSPI5_SIN IOMUX_PADCFG(0x443c005c, 0x4, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_LPSPI4_SIN IOMUX_PADCFG(0x443c005c, 0x5, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_TPM6_CH2 IOMUX_PADCFG(0x443c005c, 0x6, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO19_SAI3_TX_DATA00 IOMUX_PADCFG(0x443c005c, 0x7, 0x00000000, 0x00000000, 0x443c020c) +#define IOMUXC_PAD_GPIO_IO20_GPIO2_IO20 IOMUX_PADCFG(0x443c0060, 0x0, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_SAI3_RX_DATA00 IOMUX_PADCFG(0x443c0060, 0x1, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_PDM_BIT_STREAM00 IOMUX_PADCFG(0x443c0060, 0x2, 0x443c0438, 0x00000001, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_MEDIAMIX_DISP_DATA16 IOMUX_PADCFG(0x443c0060, 0x3, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_LPSPI5_SOUT IOMUX_PADCFG(0x443c0060, 0x4, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_LPSPI4_SOUT IOMUX_PADCFG(0x443c0060, 0x5, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_TPM3_CH1 IOMUX_PADCFG(0x443c0060, 0x6, 0x00000000, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO20_FLEXIO1_FLEXIO20 IOMUX_PADCFG(0x443c0060, 0x7, 0x443c03b4, 0x00000000, 0x443c0210) +#define IOMUXC_PAD_GPIO_IO21_GPIO2_IO21 IOMUX_PADCFG(0x443c0064, 0x0, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_SAI3_TX_DATA00 IOMUX_PADCFG(0x443c0064, 0x1, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_PDM_CLK IOMUX_PADCFG(0x443c0064, 0x2, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_MEDIAMIX_DISP_DATA17 IOMUX_PADCFG(0x443c0064, 0x3, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_LPSPI5_SCK IOMUX_PADCFG(0x443c0064, 0x4, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_LPSPI4_SCK IOMUX_PADCFG(0x443c0064, 0x5, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_TPM4_CH1 IOMUX_PADCFG(0x443c0064, 0x6, 0x00000000, 0x00000000, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO21_SAI3_RX_BCLK IOMUX_PADCFG(0x443c0064, 0x7, 0x443c044c, 0x00000001, 0x443c0214) +#define IOMUXC_PAD_GPIO_IO22_GPIO2_IO22 IOMUX_PADCFG(0x443c0068, 0x0, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_USDHC3_CLK IOMUX_PADCFG(0x443c0068, 0x1, 0x443c0458, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_SPDIF_IN IOMUX_PADCFG(0x443c0068, 0x2, 0x443c0454, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_MEDIAMIX_DISP_DATA18 IOMUX_PADCFG(0x443c0068, 0x3, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_TPM5_CH1 IOMUX_PADCFG(0x443c0068, 0x4, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_TPM6_EXTCLK IOMUX_PADCFG(0x443c0068, 0x5, 0x00000000, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_LPI2C5_SDA IOMUX_PADCFG(0x443c0068, 0x6, 0x443c03ec, 0x00000001, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO22_FLEXIO1_FLEXIO22 IOMUX_PADCFG(0x443c0068, 0x7, 0x443c03b8, 0x00000000, 0x443c0218) +#define IOMUXC_PAD_GPIO_IO23_GPIO2_IO23 IOMUX_PADCFG(0x443c006c, 0x0, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_USDHC3_CMD IOMUX_PADCFG(0x443c006c, 0x1, 0x443c045c, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_SPDIF_OUT IOMUX_PADCFG(0x443c006c, 0x2, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_MEDIAMIX_DISP_DATA19 IOMUX_PADCFG(0x443c006c, 0x3, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_TPM6_CH1 IOMUX_PADCFG(0x443c006c, 0x4, 0x00000000, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_LPI2C5_SCL IOMUX_PADCFG(0x443c006c, 0x6, 0x443c03e8, 0x00000001, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO23_FLEXIO1_FLEXIO23 IOMUX_PADCFG(0x443c006c, 0x7, 0x443c03bc, 0x00000000, 0x443c021c) +#define IOMUXC_PAD_GPIO_IO24_GPIO2_IO24 IOMUX_PADCFG(0x443c0070, 0x0, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_USDHC3_DATA0 IOMUX_PADCFG(0x443c0070, 0x1, 0x443c0460, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_MEDIAMIX_DISP_DATA20 IOMUX_PADCFG(0x443c0070, 0x3, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_TPM3_CH3 IOMUX_PADCFG(0x443c0070, 0x4, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_JTAG_MUX_TDO IOMUX_PADCFG(0x443c0070, 0x5, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_LPSPI6_PCS1 IOMUX_PADCFG(0x443c0070, 0x6, 0x00000000, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO24_FLEXIO1_FLEXIO24 IOMUX_PADCFG(0x443c0070, 0x7, 0x443c03c0, 0x00000000, 0x443c0220) +#define IOMUXC_PAD_GPIO_IO25_GPIO2_IO25 IOMUX_PADCFG(0x443c0074, 0x0, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_USDHC3_DATA1 IOMUX_PADCFG(0x443c0074, 0x1, 0x443c0464, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_CAN2_TX IOMUX_PADCFG(0x443c0074, 0x2, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_MEDIAMIX_DISP_DATA21 IOMUX_PADCFG(0x443c0074, 0x3, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_TPM4_CH3 IOMUX_PADCFG(0x443c0074, 0x4, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_JTAG_MUX_TCK IOMUX_PADCFG(0x443c0074, 0x5, 0x443c03d4, 0x00000001, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_LPSPI7_PCS1 IOMUX_PADCFG(0x443c0074, 0x6, 0x00000000, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO25_FLEXIO1_FLEXIO25 IOMUX_PADCFG(0x443c0074, 0x7, 0x443c03c4, 0x00000000, 0x443c0224) +#define IOMUXC_PAD_GPIO_IO26_GPIO2_IO26 IOMUX_PADCFG(0x443c0078, 0x0, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_USDHC3_DATA2 IOMUX_PADCFG(0x443c0078, 0x1, 0x443c0468, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_PDM_BIT_STREAM01 IOMUX_PADCFG(0x443c0078, 0x2, 0x443c043c, 0x00000001, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_MEDIAMIX_DISP_DATA22 IOMUX_PADCFG(0x443c0078, 0x3, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_TPM5_CH3 IOMUX_PADCFG(0x443c0078, 0x4, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_JTAG_MUX_TDI IOMUX_PADCFG(0x443c0078, 0x5, 0x443c03d8, 0x00000001, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_LPSPI8_PCS1 IOMUX_PADCFG(0x443c0078, 0x6, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO26_SAI3_TX_SYNC IOMUX_PADCFG(0x443c0078, 0x7, 0x00000000, 0x00000000, 0x443c0228) +#define IOMUXC_PAD_GPIO_IO27_GPIO2_IO27 IOMUX_PADCFG(0x443c007c, 0x0, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_USDHC3_DATA3 IOMUX_PADCFG(0x443c007c, 0x1, 0x443c046c, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_CAN2_RX IOMUX_PADCFG(0x443c007c, 0x2, 0x443c0364, 0x00000001, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_MEDIAMIX_DISP_DATA23 IOMUX_PADCFG(0x443c007c, 0x3, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_TPM6_CH3 IOMUX_PADCFG(0x443c007c, 0x4, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_JTAG_MUX_TMS IOMUX_PADCFG(0x443c007c, 0x5, 0x443c03dc, 0x00000001, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_LPSPI5_PCS1 IOMUX_PADCFG(0x443c007c, 0x6, 0x00000000, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO27_FLEXIO1_FLEXIO27 IOMUX_PADCFG(0x443c007c, 0x7, 0x443c03c8, 0x00000000, 0x443c022c) +#define IOMUXC_PAD_GPIO_IO28_GPIO2_IO28 IOMUX_PADCFG(0x443c0080, 0x0, 0x00000000, 0x00000000, 0x443c0230) +#define IOMUXC_PAD_GPIO_IO28_LPI2C3_SDA IOMUX_PADCFG(0x443c0080, 0x1, 0x443c03e4, 0x00000001, 0x443c0230) +#define IOMUXC_PAD_GPIO_IO28_FLEXIO1_FLEXIO28 IOMUX_PADCFG(0x443c0080, 0x7, 0x00000000, 0x00000000, 0x443c0230) +#define IOMUXC_PAD_GPIO_IO29_GPIO2_IO29 IOMUX_PADCFG(0x443c0084, 0x0, 0x00000000, 0x00000000, 0x443c0234) +#define IOMUXC_PAD_GPIO_IO29_LPI2C3_SCL IOMUX_PADCFG(0x443c0084, 0x1, 0x443c03e0, 0x00000001, 0x443c0234) +#define IOMUXC_PAD_GPIO_IO29_FLEXIO1_FLEXIO29 IOMUX_PADCFG(0x443c0084, 0x7, 0x00000000, 0x00000000, 0x443c0234) +#define IOMUXC_PAD_CCM_CLKO1_CCMSRCGPCMIX_CLKO1 IOMUX_PADCFG(0x443c0088, 0x0, 0x00000000, 0x00000000, 0x443c0238) +#define IOMUXC_PAD_CCM_CLKO1_FLEXIO1_FLEXIO26 IOMUX_PADCFG(0x443c0088, 0x4, 0x00000000, 0x00000000, 0x443c0238) +#define IOMUXC_PAD_CCM_CLKO1_GPIO3_IO26 IOMUX_PADCFG(0x443c0088, 0x5, 0x00000000, 0x00000000, 0x443c0238) +#define IOMUXC_PAD_CCM_CLKO2_GPIO3_IO27 IOMUX_PADCFG(0x443c008c, 0x5, 0x00000000, 0x00000000, 0x443c023c) +#define IOMUXC_PAD_CCM_CLKO2_CCMSRCGPCMIX_CLKO2 IOMUX_PADCFG(0x443c008c, 0x0, 0x00000000, 0x00000000, 0x443c023c) +#define IOMUXC_PAD_CCM_CLKO2_FLEXIO1_FLEXIO27 IOMUX_PADCFG(0x443c008c, 0x4, 0x443c03c8, 0x00000001, 0x443c023c) +#define IOMUXC_PAD_CCM_CLKO3_CCMSRCGPCMIX_CLKO3 IOMUX_PADCFG(0x443c0090, 0x0, 0x00000000, 0x00000000, 0x443c0240) +#define IOMUXC_PAD_CCM_CLKO3_FLEXIO2_FLEXIO28 IOMUX_PADCFG(0x443c0090, 0x4, 0x00000000, 0x00000000, 0x443c0240) +#define IOMUXC_PAD_CCM_CLKO3_GPIO4_IO28 IOMUX_PADCFG(0x443c0090, 0x5, 0x00000000, 0x00000000, 0x443c0240) +#define IOMUXC_PAD_CCM_CLKO4_CCMSRCGPCMIX_CLKO4 IOMUX_PADCFG(0x443c0094, 0x0, 0x00000000, 0x00000000, 0x443c0244) +#define IOMUXC_PAD_CCM_CLKO4_FLEXIO2_FLEXIO29 IOMUX_PADCFG(0x443c0094, 0x4, 0x00000000, 0x00000000, 0x443c0244) +#define IOMUXC_PAD_CCM_CLKO4_GPIO4_IO29 IOMUX_PADCFG(0x443c0094, 0x5, 0x00000000, 0x00000000, 0x443c0244) +#define IOMUXC_PAD_ENET1_MDC_ENET_QOS_MDC IOMUX_PADCFG(0x443c0098, 0x0, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_LPUART3_DCB_B IOMUX_PADCFG(0x443c0098, 0x1, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_I3C2_SCL IOMUX_PADCFG(0x443c0098, 0x2, 0x443c03cc, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_HSIOMIX_OTG_ID1 IOMUX_PADCFG(0x443c0098, 0x3, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_FLEXIO2_FLEXIO00 IOMUX_PADCFG(0x443c0098, 0x4, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDC_GPIO4_IO00 IOMUX_PADCFG(0x443c0098, 0x5, 0x00000000, 0x00000000, 0x443c0248) +#define IOMUXC_PAD_ENET1_MDIO_ENET_QOS_MDIO IOMUX_PADCFG(0x443c009c, 0x0, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_LPUART3_RIN_B IOMUX_PADCFG(0x443c009c, 0x1, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_I3C2_SDA IOMUX_PADCFG(0x443c009c, 0x2, 0x443c03d0, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_HSIOMIX_OTG_PWR1 IOMUX_PADCFG(0x443c009c, 0x3, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_FLEXIO2_FLEXIO01 IOMUX_PADCFG(0x443c009c, 0x4, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_MDIO_GPIO4_IO01 IOMUX_PADCFG(0x443c009c, 0x5, 0x00000000, 0x00000000, 0x443c024c) +#define IOMUXC_PAD_ENET1_TD3_ENET_QOS_RGMII_TD3 IOMUX_PADCFG(0x443c00a0, 0x0, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_CAN2_TX IOMUX_PADCFG(0x443c00a0, 0x2, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_HSIOMIX_OTG_ID2 IOMUX_PADCFG(0x443c00a0, 0x3, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_FLEXIO2_FLEXIO02 IOMUX_PADCFG(0x443c00a0, 0x4, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD3_GPIO4_IO02 IOMUX_PADCFG(0x443c00a0, 0x5, 0x00000000, 0x00000000, 0x443c0250) +#define IOMUXC_PAD_ENET1_TD2_ENET_QOS_RGMII_TD2 IOMUX_PADCFG(0x443c00a4, 0x0, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK IOMUX_PADCFG(0x443c00a4, 0x1, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_CAN2_RX IOMUX_PADCFG(0x443c00a4, 0x2, 0x443c0364, 0x00000002, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_HSIOMIX_OTG_OC2 IOMUX_PADCFG(0x443c00a4, 0x3, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_FLEXIO2_FLEXIO03 IOMUX_PADCFG(0x443c00a4, 0x4, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD2_GPIO4_IO03 IOMUX_PADCFG(0x443c00a4, 0x5, 0x00000000, 0x00000000, 0x443c0254) +#define IOMUXC_PAD_ENET1_TD1_ENET_QOS_RGMII_TD1 IOMUX_PADCFG(0x443c00a8, 0x0, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_LPUART3_RTS_B IOMUX_PADCFG(0x443c00a8, 0x1, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR IOMUX_PADCFG(0x443c00a8, 0x2, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_HSIOMIX_OTG_OC1 IOMUX_PADCFG(0x443c00a8, 0x3, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_FLEXIO2_FLEXIO04 IOMUX_PADCFG(0x443c00a8, 0x4, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_GPIO4_IO04 IOMUX_PADCFG(0x443c00a8, 0x5, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD1_I3C2_PUR_B IOMUX_PADCFG(0x443c00a8, 0x6, 0x00000000, 0x00000000, 0x443c0258) +#define IOMUXC_PAD_ENET1_TD0_ENET_QOS_RGMII_TD0 IOMUX_PADCFG(0x443c00ac, 0x0, 0x00000000, 0x00000000, 0x443c025c) +#define IOMUXC_PAD_ENET1_TD0_LPUART3_TX IOMUX_PADCFG(0x443c00ac, 0x1, 0x443c041c, 0x00000001, 0x443c025c) +#define IOMUXC_PAD_ENET1_TD0_FLEXIO2_FLEXIO05 IOMUX_PADCFG(0x443c00ac, 0x4, 0x00000000, 0x00000000, 0x443c025c) +#define IOMUXC_PAD_ENET1_TD0_GPIO4_IO05 IOMUX_PADCFG(0x443c00ac, 0x5, 0x00000000, 0x00000000, 0x443c025c) +#define IOMUXC_PAD_ENET1_TX_CTL_ENET_QOS_RGMII_TX_CTL IOMUX_PADCFG(0x443c00b0, 0x0, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TX_CTL_LPUART3_DTR_B IOMUX_PADCFG(0x443c00b0, 0x1, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TX_CTL_FLEXIO2_FLEXIO06 IOMUX_PADCFG(0x443c00b0, 0x4, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TX_CTL_GPIO4_IO06 IOMUX_PADCFG(0x443c00b0, 0x5, 0x00000000, 0x00000000, 0x443c0260) +#define IOMUXC_PAD_ENET1_TXC_CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK IOMUX_PADCFG(0x443c00b4, 0x0, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_TXC_ENET_QOS_TX_ER IOMUX_PADCFG(0x443c00b4, 0x1, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_TXC_FLEXIO2_FLEXIO07 IOMUX_PADCFG(0x443c00b4, 0x4, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_TXC_GPIO4_IO07 IOMUX_PADCFG(0x443c00b4, 0x5, 0x00000000, 0x00000000, 0x443c0264) +#define IOMUXC_PAD_ENET1_RX_CTL_ENET_QOS_RGMII_RX_CTL IOMUX_PADCFG(0x443c00b8, 0x0, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_LPUART3_DSR_B IOMUX_PADCFG(0x443c00b8, 0x1, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_HSIOMIX_OTG_PWR2 IOMUX_PADCFG(0x443c00b8, 0x3, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_FLEXIO2_FLEXIO08 IOMUX_PADCFG(0x443c00b8, 0x4, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RX_CTL_GPIO4_IO08 IOMUX_PADCFG(0x443c00b8, 0x5, 0x00000000, 0x00000000, 0x443c0268) +#define IOMUXC_PAD_ENET1_RXC_CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK IOMUX_PADCFG(0x443c00bc, 0x0, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RXC_ENET_QOS_RX_ER IOMUX_PADCFG(0x443c00bc, 0x1, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RXC_FLEXIO2_FLEXIO09 IOMUX_PADCFG(0x443c00bc, 0x4, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RXC_GPIO4_IO09 IOMUX_PADCFG(0x443c00bc, 0x5, 0x00000000, 0x00000000, 0x443c026c) +#define IOMUXC_PAD_ENET1_RD0_ENET_QOS_RGMII_RD0 IOMUX_PADCFG(0x443c00c0, 0x0, 0x00000000, 0x00000000, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD0_LPUART3_RX IOMUX_PADCFG(0x443c00c0, 0x1, 0x443c0418, 0x00000001, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD0_FLEXIO2_FLEXIO10 IOMUX_PADCFG(0x443c00c0, 0x4, 0x00000000, 0x00000000, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD0_GPIO4_IO10 IOMUX_PADCFG(0x443c00c0, 0x5, 0x00000000, 0x00000000, 0x443c0270) +#define IOMUXC_PAD_ENET1_RD1_ENET_QOS_RGMII_RD1 IOMUX_PADCFG(0x443c00c4, 0x0, 0x00000000, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_LPUART3_CTS_B IOMUX_PADCFG(0x443c00c4, 0x1, 0x443c0414, 0x00000001, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_LPTMR2_ALT1 IOMUX_PADCFG(0x443c00c4, 0x3, 0x443c0408, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_FLEXIO2_FLEXIO11 IOMUX_PADCFG(0x443c00c4, 0x4, 0x00000000, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD1_GPIO4_IO11 IOMUX_PADCFG(0x443c00c4, 0x5, 0x00000000, 0x00000000, 0x443c0274) +#define IOMUXC_PAD_ENET1_RD2_ENET_QOS_RGMII_RD2 IOMUX_PADCFG(0x443c00c8, 0x0, 0x00000000, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD2_LPTMR2_ALT2 IOMUX_PADCFG(0x443c00c8, 0x3, 0x443c040c, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD2_FLEXIO2_FLEXIO12 IOMUX_PADCFG(0x443c00c8, 0x4, 0x00000000, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD2_GPIO4_IO12 IOMUX_PADCFG(0x443c00c8, 0x5, 0x00000000, 0x00000000, 0x443c0278) +#define IOMUXC_PAD_ENET1_RD3_ENET_QOS_RGMII_RD3 IOMUX_PADCFG(0x443c00cc, 0x0, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_FLEXSPI1_TESTER_TRIGGER IOMUX_PADCFG(0x443c00cc, 0x2, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_LPTMR2_ALT3 IOMUX_PADCFG(0x443c00cc, 0x3, 0x443c0410, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_FLEXIO2_FLEXIO13 IOMUX_PADCFG(0x443c00cc, 0x4, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET1_RD3_GPIO4_IO13 IOMUX_PADCFG(0x443c00cc, 0x5, 0x00000000, 0x00000000, 0x443c027c) +#define IOMUXC_PAD_ENET2_MDC_ENET1_MDC IOMUX_PADCFG(0x443c00d0, 0x0, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_LPUART4_DCB_B IOMUX_PADCFG(0x443c00d0, 0x1, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_SAI2_RX_SYNC IOMUX_PADCFG(0x443c00d0, 0x2, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_FLEXIO2_FLEXIO14 IOMUX_PADCFG(0x443c00d0, 0x4, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDC_GPIO4_IO14 IOMUX_PADCFG(0x443c00d0, 0x5, 0x00000000, 0x00000000, 0x443c0280) +#define IOMUXC_PAD_ENET2_MDIO_ENET1_MDIO IOMUX_PADCFG(0x443c00d4, 0x0, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_LPUART4_RIN_B IOMUX_PADCFG(0x443c00d4, 0x1, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_SAI2_RX_BCLK IOMUX_PADCFG(0x443c00d4, 0x2, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_FLEXIO2_FLEXIO15 IOMUX_PADCFG(0x443c00d4, 0x4, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_MDIO_GPIO4_IO15 IOMUX_PADCFG(0x443c00d4, 0x5, 0x00000000, 0x00000000, 0x443c0284) +#define IOMUXC_PAD_ENET2_TD3_SAI2_RX_DATA00 IOMUX_PADCFG(0x443c00d8, 0x2, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD3_FLEXIO2_FLEXIO16 IOMUX_PADCFG(0x443c00d8, 0x4, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD3_GPIO4_IO16 IOMUX_PADCFG(0x443c00d8, 0x5, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD3_ENET1_RGMII_TD3 IOMUX_PADCFG(0x443c00d8, 0x0, 0x00000000, 0x00000000, 0x443c0288) +#define IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2 IOMUX_PADCFG(0x443c00dc, 0x0, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_ENET1_TX_CLK IOMUX_PADCFG(0x443c00dc, 0x1, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_SAI2_RX_DATA01 IOMUX_PADCFG(0x443c00dc, 0x2, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_FLEXIO2_FLEXIO17 IOMUX_PADCFG(0x443c00dc, 0x4, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD2_GPIO4_IO17 IOMUX_PADCFG(0x443c00dc, 0x5, 0x00000000, 0x00000000, 0x443c028c) +#define IOMUXC_PAD_ENET2_TD1_ENET1_RGMII_TD1 IOMUX_PADCFG(0x443c00e0, 0x0, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_LPUART4_RTS_B IOMUX_PADCFG(0x443c00e0, 0x1, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_SAI2_RX_DATA02 IOMUX_PADCFG(0x443c00e0, 0x2, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_FLEXIO2_FLEXIO18 IOMUX_PADCFG(0x443c00e0, 0x4, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD1_GPIO4_IO18 IOMUX_PADCFG(0x443c00e0, 0x5, 0x00000000, 0x00000000, 0x443c0290) +#define IOMUXC_PAD_ENET2_TD0_ENET1_RGMII_TD0 IOMUX_PADCFG(0x443c00e4, 0x0, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_LPUART4_TX IOMUX_PADCFG(0x443c00e4, 0x1, 0x443c0428, 0x00000001, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_SAI2_RX_DATA03 IOMUX_PADCFG(0x443c00e4, 0x2, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_FLEXIO2_FLEXIO19 IOMUX_PADCFG(0x443c00e4, 0x4, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TD0_GPIO4_IO19 IOMUX_PADCFG(0x443c00e4, 0x5, 0x00000000, 0x00000000, 0x443c0294) +#define IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL IOMUX_PADCFG(0x443c00e8, 0x0, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_LPUART4_DTR_B IOMUX_PADCFG(0x443c00e8, 0x1, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_SAI2_TX_SYNC IOMUX_PADCFG(0x443c00e8, 0x2, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_FLEXIO2_FLEXIO20 IOMUX_PADCFG(0x443c00e8, 0x4, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TX_CTL_GPIO4_IO20 IOMUX_PADCFG(0x443c00e8, 0x5, 0x00000000, 0x00000000, 0x443c0298) +#define IOMUXC_PAD_ENET2_TXC_ENET1_RGMII_TXC IOMUX_PADCFG(0x443c00ec, 0x0, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_ENET1_TX_ER IOMUX_PADCFG(0x443c00ec, 0x1, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_SAI2_TX_BCLK IOMUX_PADCFG(0x443c00ec, 0x2, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_FLEXIO2_FLEXIO21 IOMUX_PADCFG(0x443c00ec, 0x4, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_TXC_GPIO4_IO21 IOMUX_PADCFG(0x443c00ec, 0x5, 0x00000000, 0x00000000, 0x443c029c) +#define IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL IOMUX_PADCFG(0x443c00f0, 0x0, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_LPUART4_DSR_B IOMUX_PADCFG(0x443c00f0, 0x1, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_SAI2_TX_DATA00 IOMUX_PADCFG(0x443c00f0, 0x2, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_FLEXIO2_FLEXIO22 IOMUX_PADCFG(0x443c00f0, 0x4, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RX_CTL_GPIO4_IO22 IOMUX_PADCFG(0x443c00f0, 0x5, 0x00000000, 0x00000000, 0x443c02a0) +#define IOMUXC_PAD_ENET2_RXC_ENET1_RGMII_RXC IOMUX_PADCFG(0x443c00f4, 0x0, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_ENET1_RX_ER IOMUX_PADCFG(0x443c00f4, 0x1, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_SAI2_TX_DATA01 IOMUX_PADCFG(0x443c00f4, 0x2, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_FLEXIO2_FLEXIO23 IOMUX_PADCFG(0x443c00f4, 0x4, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RXC_GPIO4_IO23 IOMUX_PADCFG(0x443c00f4, 0x5, 0x00000000, 0x00000000, 0x443c02a4) +#define IOMUXC_PAD_ENET2_RD0_ENET1_RGMII_RD0 IOMUX_PADCFG(0x443c00f8, 0x0, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_LPUART4_RX IOMUX_PADCFG(0x443c00f8, 0x1, 0x443c0424, 0x00000001, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_SAI2_TX_DATA02 IOMUX_PADCFG(0x443c00f8, 0x2, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_FLEXIO2_FLEXIO24 IOMUX_PADCFG(0x443c00f8, 0x4, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD0_GPIO4_IO24 IOMUX_PADCFG(0x443c00f8, 0x5, 0x00000000, 0x00000000, 0x443c02a8) +#define IOMUXC_PAD_ENET2_RD1_ENET1_RGMII_RD1 IOMUX_PADCFG(0x443c00fc, 0x0, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_SPDIF_IN IOMUX_PADCFG(0x443c00fc, 0x1, 0x443c0454, 0x00000001, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_SAI2_TX_DATA03 IOMUX_PADCFG(0x443c00fc, 0x2, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_FLEXIO2_FLEXIO25 IOMUX_PADCFG(0x443c00fc, 0x4, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD1_GPIO4_IO25 IOMUX_PADCFG(0x443c00fc, 0x5, 0x00000000, 0x00000000, 0x443c02ac) +#define IOMUXC_PAD_ENET2_RD2_ENET1_RGMII_RD2 IOMUX_PADCFG(0x443c0100, 0x0, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_LPUART4_CTS_B IOMUX_PADCFG(0x443c0100, 0x1, 0x443c0420, 0x00000001, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_SAI2_MCLK IOMUX_PADCFG(0x443c0100, 0x2, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_MQS2_RIGHT IOMUX_PADCFG(0x443c0100, 0x3, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_FLEXIO2_FLEXIO26 IOMUX_PADCFG(0x443c0100, 0x4, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD2_GPIO4_IO26 IOMUX_PADCFG(0x443c0100, 0x5, 0x00000000, 0x00000000, 0x443c02b0) +#define IOMUXC_PAD_ENET2_RD3_ENET1_RGMII_RD3 IOMUX_PADCFG(0x443c0104, 0x0, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_OUT IOMUX_PADCFG(0x443c0104, 0x1, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_SPDIF_IN IOMUX_PADCFG(0x443c0104, 0x2, 0x443c0454, 0x00000002, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_MQS2_LEFT IOMUX_PADCFG(0x443c0104, 0x3, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_FLEXIO2_FLEXIO27 IOMUX_PADCFG(0x443c0104, 0x4, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_ENET2_RD3_GPIO4_IO27 IOMUX_PADCFG(0x443c0104, 0x5, 0x00000000, 0x00000000, 0x443c02b4) +#define IOMUXC_PAD_SD1_CLK_FLEXIO1_FLEXIO08 IOMUX_PADCFG(0x443c0108, 0x4, 0x443c038c, 0x00000001, 0x443c02b8) +#define IOMUXC_PAD_SD1_CLK_GPIO3_IO08 IOMUX_PADCFG(0x443c0108, 0x5, 0x00000000, 0x00000000, 0x443c02b8) +#define IOMUXC_PAD_SD1_CLK_USDHC1_CLK IOMUX_PADCFG(0x443c0108, 0x0, 0x00000000, 0x00000000, 0x443c02b8) +#define IOMUXC_PAD_SD1_CMD_USDHC1_CMD IOMUX_PADCFG(0x443c010c, 0x0, 0x00000000, 0x00000000, 0x443c02bc) +#define IOMUXC_PAD_SD1_CMD_FLEXIO1_FLEXIO09 IOMUX_PADCFG(0x443c010c, 0x4, 0x443c0390, 0x00000001, 0x443c02bc) +#define IOMUXC_PAD_SD1_CMD_GPIO3_IO09 IOMUX_PADCFG(0x443c010c, 0x5, 0x00000000, 0x00000000, 0x443c02bc) +#define IOMUXC_PAD_SD1_DATA0_USDHC1_DATA0 IOMUX_PADCFG(0x443c0110, 0x0, 0x00000000, 0x00000000, 0x443c02c0) +#define IOMUXC_PAD_SD1_DATA0_FLEXIO1_FLEXIO10 IOMUX_PADCFG(0x443c0110, 0x4, 0x443c0394, 0x00000001, 0x443c02c0) +#define IOMUXC_PAD_SD1_DATA0_GPIO3_IO10 IOMUX_PADCFG(0x443c0110, 0x5, 0x00000000, 0x00000000, 0x443c02c0) +#define IOMUXC_PAD_SD1_DATA1_USDHC1_DATA1 IOMUX_PADCFG(0x443c0114, 0x0, 0x00000000, 0x00000000, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA1_FLEXIO1_FLEXIO11 IOMUX_PADCFG(0x443c0114, 0x4, 0x443c0398, 0x00000001, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA1_GPIO3_IO11 IOMUX_PADCFG(0x443c0114, 0x5, 0x00000000, 0x00000000, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA1_CCMSRCGPCMIX_INT_BOOT IOMUX_PADCFG(0x443c0114, 0x6, 0x00000000, 0x00000000, 0x443c02c4) +#define IOMUXC_PAD_SD1_DATA2_USDHC1_DATA2 IOMUX_PADCFG(0x443c0118, 0x0, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA2_FLEXIO1_FLEXIO12 IOMUX_PADCFG(0x443c0118, 0x4, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA2_GPIO3_IO12 IOMUX_PADCFG(0x443c0118, 0x5, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA2_CCMSRCGPCMIX_PMIC_READY IOMUX_PADCFG(0x443c0118, 0x6, 0x00000000, 0x00000000, 0x443c02c8) +#define IOMUXC_PAD_SD1_DATA3_USDHC1_DATA3 IOMUX_PADCFG(0x443c011c, 0x0, 0x00000000, 0x00000000, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA3_FLEXSPI1_A_SS1_B IOMUX_PADCFG(0x443c011c, 0x1, 0x00000000, 0x00000000, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA3_FLEXIO1_FLEXIO13 IOMUX_PADCFG(0x443c011c, 0x4, 0x443c039c, 0x00000001, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA3_GPIO3_IO13 IOMUX_PADCFG(0x443c011c, 0x5, 0x00000000, 0x00000000, 0x443c02cc) +#define IOMUXC_PAD_SD1_DATA4_USDHC1_DATA4 IOMUX_PADCFG(0x443c0120, 0x0, 0x00000000, 0x00000000, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA4_FLEXSPI1_A_DATA04 IOMUX_PADCFG(0x443c0120, 0x1, 0x00000000, 0x00000000, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA4_FLEXIO1_FLEXIO14 IOMUX_PADCFG(0x443c0120, 0x4, 0x443c03a0, 0x00000001, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA4_GPIO3_IO14 IOMUX_PADCFG(0x443c0120, 0x5, 0x00000000, 0x00000000, 0x443c02d0) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_DATA5 IOMUX_PADCFG(0x443c0124, 0x0, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_FLEXSPI1_A_DATA05 IOMUX_PADCFG(0x443c0124, 0x1, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_USDHC1_RESET_B IOMUX_PADCFG(0x443c0124, 0x2, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_FLEXIO1_FLEXIO15 IOMUX_PADCFG(0x443c0124, 0x4, 0x443c03a4, 0x00000001, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA5_GPIO3_IO15 IOMUX_PADCFG(0x443c0124, 0x5, 0x00000000, 0x00000000, 0x443c02d4) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_DATA6 IOMUX_PADCFG(0x443c0128, 0x0, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_FLEXSPI1_A_DATA06 IOMUX_PADCFG(0x443c0128, 0x1, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_USDHC1_CD_B IOMUX_PADCFG(0x443c0128, 0x2, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_FLEXIO1_FLEXIO16 IOMUX_PADCFG(0x443c0128, 0x4, 0x443c03a8, 0x00000001, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA6_GPIO3_IO16 IOMUX_PADCFG(0x443c0128, 0x5, 0x00000000, 0x00000000, 0x443c02d8) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_DATA7 IOMUX_PADCFG(0x443c012c, 0x0, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_FLEXSPI1_A_DATA07 IOMUX_PADCFG(0x443c012c, 0x1, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_USDHC1_WP IOMUX_PADCFG(0x443c012c, 0x2, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_FLEXIO1_FLEXIO17 IOMUX_PADCFG(0x443c012c, 0x4, 0x443c03ac, 0x00000001, 0x443c02dc) +#define IOMUXC_PAD_SD1_DATA7_GPIO3_IO17 IOMUX_PADCFG(0x443c012c, 0x5, 0x00000000, 0x00000000, 0x443c02dc) +#define IOMUXC_PAD_SD1_STROBE_USDHC1_STROBE IOMUX_PADCFG(0x443c0130, 0x0, 0x00000000, 0x00000000, 0x443c02e0) +#define IOMUXC_PAD_SD1_STROBE_FLEXSPI1_A_DQS IOMUX_PADCFG(0x443c0130, 0x1, 0x00000000, 0x00000000, 0x443c02e0) +#define IOMUXC_PAD_SD1_STROBE_FLEXIO1_FLEXIO18 IOMUX_PADCFG(0x443c0130, 0x4, 0x443c03b0, 0x00000001, 0x443c02e0) +#define IOMUXC_PAD_SD1_STROBE_GPIO3_IO18 IOMUX_PADCFG(0x443c0130, 0x5, 0x00000000, 0x00000000, 0x443c02e0) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_VSELECT IOMUX_PADCFG(0x443c0134, 0x0, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_USDHC2_WP IOMUX_PADCFG(0x443c0134, 0x1, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_LPTMR2_ALT3 IOMUX_PADCFG(0x443c0134, 0x2, 0x443c0410, 0x00000001, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_FLEXIO1_FLEXIO19 IOMUX_PADCFG(0x443c0134, 0x4, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_GPIO3_IO19 IOMUX_PADCFG(0x443c0134, 0x5, 0x00000000, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD2_VSELECT_CCMSRCGPCMIX_EXT_CLK1 IOMUX_PADCFG(0x443c0134, 0x6, 0x443c0368, 0x00000000, 0x443c02e4) +#define IOMUXC_PAD_SD3_CLK_USDHC3_CLK IOMUX_PADCFG(0x443c0138, 0x0, 0x443c0458, 0x00000001, 0x443c02e8) +#define IOMUXC_PAD_SD3_CLK_FLEXSPI1_A_SCLK IOMUX_PADCFG(0x443c0138, 0x1, 0x00000000, 0x00000000, 0x443c02e8) +#define IOMUXC_PAD_SD3_CLK_FLEXIO1_FLEXIO20 IOMUX_PADCFG(0x443c0138, 0x4, 0x443c03b4, 0x00000001, 0x443c02e8) +#define IOMUXC_PAD_SD3_CLK_GPIO3_IO20 IOMUX_PADCFG(0x443c0138, 0x5, 0x00000000, 0x00000000, 0x443c02e8) +#define IOMUXC_PAD_SD3_CMD_USDHC3_CMD IOMUX_PADCFG(0x443c013c, 0x0, 0x443c045c, 0x00000001, 0x443c02ec) +#define IOMUXC_PAD_SD3_CMD_FLEXSPI1_A_SS0_B IOMUX_PADCFG(0x443c013c, 0x1, 0x00000000, 0x00000000, 0x443c02ec) +#define IOMUXC_PAD_SD3_CMD_FLEXIO1_FLEXIO21 IOMUX_PADCFG(0x443c013c, 0x4, 0x00000000, 0x00000000, 0x443c02ec) +#define IOMUXC_PAD_SD3_CMD_GPIO3_IO21 IOMUX_PADCFG(0x443c013c, 0x5, 0x00000000, 0x00000000, 0x443c02ec) +#define IOMUXC_PAD_SD3_DATA0_USDHC3_DATA0 IOMUX_PADCFG(0x443c0140, 0x0, 0x443c0460, 0x00000001, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA0_FLEXSPI1_A_DATA00 IOMUX_PADCFG(0x443c0140, 0x1, 0x00000000, 0x00000000, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA0_FLEXIO1_FLEXIO22 IOMUX_PADCFG(0x443c0140, 0x4, 0x443c03b8, 0x00000001, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA0_GPIO3_IO22 IOMUX_PADCFG(0x443c0140, 0x5, 0x00000000, 0x00000000, 0x443c02f0) +#define IOMUXC_PAD_SD3_DATA1_USDHC3_DATA1 IOMUX_PADCFG(0x443c0144, 0x0, 0x443c0464, 0x00000001, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA1_FLEXSPI1_A_DATA01 IOMUX_PADCFG(0x443c0144, 0x1, 0x00000000, 0x00000000, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA1_FLEXIO1_FLEXIO23 IOMUX_PADCFG(0x443c0144, 0x4, 0x443c03bc, 0x00000001, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA1_GPIO3_IO23 IOMUX_PADCFG(0x443c0144, 0x5, 0x00000000, 0x00000000, 0x443c02f4) +#define IOMUXC_PAD_SD3_DATA2_USDHC3_DATA2 IOMUX_PADCFG(0x443c0148, 0x0, 0x443c0468, 0x00000001, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA2_FLEXSPI1_A_DATA02 IOMUX_PADCFG(0x443c0148, 0x1, 0x00000000, 0x00000000, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA2_FLEXIO1_FLEXIO24 IOMUX_PADCFG(0x443c0148, 0x4, 0x443c03c0, 0x00000001, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA2_GPIO3_IO24 IOMUX_PADCFG(0x443c0148, 0x5, 0x00000000, 0x00000000, 0x443c02f8) +#define IOMUXC_PAD_SD3_DATA3_USDHC3_DATA3 IOMUX_PADCFG(0x443c014c, 0x0, 0x443c046c, 0x00000001, 0x443c02fc) +#define IOMUXC_PAD_SD3_DATA3_FLEXSPI1_A_DATA03 IOMUX_PADCFG(0x443c014c, 0x1, 0x00000000, 0x00000000, 0x443c02fc) +#define IOMUXC_PAD_SD3_DATA3_FLEXIO1_FLEXIO25 IOMUX_PADCFG(0x443c014c, 0x4, 0x443c03c4, 0x00000001, 0x443c02fc) +#define IOMUXC_PAD_SD3_DATA3_GPIO3_IO25 IOMUX_PADCFG(0x443c014c, 0x5, 0x00000000, 0x00000000, 0x443c02fc) +#define IOMUXC_PAD_SD2_CD_B_USDHC2_CD_B IOMUX_PADCFG(0x443c0150, 0x0, 0x00000000, 0x00000000, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_ENET_QOS_1588_EVENT0_IN IOMUX_PADCFG(0x443c0150, 0x1, 0x00000000, 0x00000000, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_I3C2_SCL IOMUX_PADCFG(0x443c0150, 0x2, 0x443c03cc, 0x00000001, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_FLEXIO1_FLEXIO00 IOMUX_PADCFG(0x443c0150, 0x4, 0x443c036c, 0x00000001, 0x443c0300) +#define IOMUXC_PAD_SD2_CD_B_GPIO3_IO00 IOMUX_PADCFG(0x443c0150, 0x5, 0x00000000, 0x00000000, 0x443c0300) +#define IOMUXC_PAD_SD2_CLK_USDHC2_CLK IOMUX_PADCFG(0x443c0154, 0x0, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_ENET_QOS_1588_EVENT0_OUT IOMUX_PADCFG(0x443c0154, 0x1, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_I3C2_SDA IOMUX_PADCFG(0x443c0154, 0x2, 0x443c03d0, 0x00000001, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_FLEXIO1_FLEXIO01 IOMUX_PADCFG(0x443c0154, 0x4, 0x443c0370, 0x00000001, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_GPIO3_IO01 IOMUX_PADCFG(0x443c0154, 0x5, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CLK_CCMSRCGPCMIX_OBSERVE0 IOMUX_PADCFG(0x443c0154, 0x6, 0x00000000, 0x00000000, 0x443c0304) +#define IOMUXC_PAD_SD2_CMD_USDHC2_CMD IOMUX_PADCFG(0x443c0158, 0x0, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_ENET1_1588_EVENT0_IN IOMUX_PADCFG(0x443c0158, 0x1, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR IOMUX_PADCFG(0x443c0158, 0x2, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_I3C2_PUR_B IOMUX_PADCFG(0x443c0158, 0x3, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_FLEXIO1_FLEXIO02 IOMUX_PADCFG(0x443c0158, 0x4, 0x443c0374, 0x00000001, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_GPIO3_IO02 IOMUX_PADCFG(0x443c0158, 0x5, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_CMD_CCMSRCGPCMIX_OBSERVE1 IOMUX_PADCFG(0x443c0158, 0x6, 0x00000000, 0x00000000, 0x443c0308) +#define IOMUXC_PAD_SD2_DATA0_USDHC2_DATA0 IOMUX_PADCFG(0x443c015c, 0x0, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_ENET1_1588_EVENT0_OUT IOMUX_PADCFG(0x443c015c, 0x1, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_CAN2_TX IOMUX_PADCFG(0x443c015c, 0x2, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_FLEXIO1_FLEXIO03 IOMUX_PADCFG(0x443c015c, 0x4, 0x443c0378, 0x00000001, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_GPIO3_IO03 IOMUX_PADCFG(0x443c015c, 0x5, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2 IOMUX_PADCFG(0x443c015c, 0x6, 0x00000000, 0x00000000, 0x443c030c) +#define IOMUXC_PAD_SD2_DATA1_USDHC2_DATA1 IOMUX_PADCFG(0x443c0160, 0x0, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_ENET1_1588_EVENT1_IN IOMUX_PADCFG(0x443c0160, 0x1, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_CAN2_RX IOMUX_PADCFG(0x443c0160, 0x2, 0x443c0364, 0x00000003, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_FLEXIO1_FLEXIO04 IOMUX_PADCFG(0x443c0160, 0x4, 0x443c037c, 0x00000001, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_GPIO3_IO04 IOMUX_PADCFG(0x443c0160, 0x5, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA1_CCMSRCGPCMIX_WAIT IOMUX_PADCFG(0x443c0160, 0x6, 0x00000000, 0x00000000, 0x443c0310) +#define IOMUXC_PAD_SD2_DATA2_USDHC2_DATA2 IOMUX_PADCFG(0x443c0164, 0x0, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_ENET1_1588_EVENT1_OUT IOMUX_PADCFG(0x443c0164, 0x1, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_MQS2_RIGHT IOMUX_PADCFG(0x443c0164, 0x2, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_FLEXIO1_FLEXIO05 IOMUX_PADCFG(0x443c0164, 0x4, 0x443c0380, 0x00000001, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_GPIO3_IO05 IOMUX_PADCFG(0x443c0164, 0x5, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA2_CCMSRCGPCMIX_STOP IOMUX_PADCFG(0x443c0164, 0x6, 0x00000000, 0x00000000, 0x443c0314) +#define IOMUXC_PAD_SD2_DATA3_USDHC2_DATA3 IOMUX_PADCFG(0x443c0168, 0x0, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_LPTMR2_ALT1 IOMUX_PADCFG(0x443c0168, 0x1, 0x443c0408, 0x00000001, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_MQS2_LEFT IOMUX_PADCFG(0x443c0168, 0x2, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_FLEXIO1_FLEXIO06 IOMUX_PADCFG(0x443c0168, 0x4, 0x443c0384, 0x00000001, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_GPIO3_IO06 IOMUX_PADCFG(0x443c0168, 0x5, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET IOMUX_PADCFG(0x443c0168, 0x6, 0x00000000, 0x00000000, 0x443c0318) +#define IOMUXC_PAD_SD2_RESET_B_USDHC2_RESET_B IOMUX_PADCFG(0x443c016c, 0x0, 0x00000000, 0x00000000, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_LPTMR2_ALT2 IOMUX_PADCFG(0x443c016c, 0x1, 0x443c040c, 0x00000001, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_FLEXIO1_FLEXIO07 IOMUX_PADCFG(0x443c016c, 0x4, 0x443c0388, 0x00000001, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_GPIO3_IO07 IOMUX_PADCFG(0x443c016c, 0x5, 0x00000000, 0x00000000, 0x443c031c) +#define IOMUXC_PAD_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET IOMUX_PADCFG(0x443c016c, 0x6, 0x00000000, 0x00000000, 0x443c031c) +#define IOMUXC_PAD_I2C1_SCL_LPI2C1_SCL IOMUX_PADCFG(0x443c0170, 0x0, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_I3C1_SCL IOMUX_PADCFG(0x443c0170, 0x1, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_LPUART1_DCB_B IOMUX_PADCFG(0x443c0170, 0x2, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_TPM2_CH0 IOMUX_PADCFG(0x443c0170, 0x3, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SCL_GPIO1_IO00 IOMUX_PADCFG(0x443c0170, 0x5, 0x00000000, 0x00000000, 0x443c0320) +#define IOMUXC_PAD_I2C1_SDA_LPI2C1_SDA IOMUX_PADCFG(0x443c0174, 0x0, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_I3C1_SDA IOMUX_PADCFG(0x443c0174, 0x1, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_LPUART1_RIN_B IOMUX_PADCFG(0x443c0174, 0x2, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_TPM2_CH1 IOMUX_PADCFG(0x443c0174, 0x3, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C1_SDA_GPIO1_IO01 IOMUX_PADCFG(0x443c0174, 0x5, 0x00000000, 0x00000000, 0x443c0324) +#define IOMUXC_PAD_I2C2_SCL_LPI2C2_SCL IOMUX_PADCFG(0x443c0178, 0x0, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR IOMUX_PADCFG(0x443c0178, 0x1, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_LPUART2_DCB_B IOMUX_PADCFG(0x443c0178, 0x2, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_TPM2_CH2 IOMUX_PADCFG(0x443c0178, 0x3, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_SAI1_RX_SYNC IOMUX_PADCFG(0x443c0178, 0x4, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_GPIO1_IO02 IOMUX_PADCFG(0x443c0178, 0x5, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SCL_I3C1_PUR_B IOMUX_PADCFG(0x443c0178, 0x6, 0x00000000, 0x00000000, 0x443c0328) +#define IOMUXC_PAD_I2C2_SDA_LPI2C2_SDA IOMUX_PADCFG(0x443c017c, 0x0, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_LPUART2_RIN_B IOMUX_PADCFG(0x443c017c, 0x2, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_TPM2_CH3 IOMUX_PADCFG(0x443c017c, 0x3, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_SAI1_RX_BCLK IOMUX_PADCFG(0x443c017c, 0x4, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_I2C2_SDA_GPIO1_IO03 IOMUX_PADCFG(0x443c017c, 0x5, 0x00000000, 0x00000000, 0x443c032c) +#define IOMUXC_PAD_UART1_RXD_LPUART1_RX IOMUX_PADCFG(0x443c0180, 0x0, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_S400_UART_RX IOMUX_PADCFG(0x443c0180, 0x1, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_LPSPI2_SIN IOMUX_PADCFG(0x443c0180, 0x2, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_TPM1_CH0 IOMUX_PADCFG(0x443c0180, 0x3, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_RXD_GPIO1_IO04 IOMUX_PADCFG(0x443c0180, 0x5, 0x00000000, 0x00000000, 0x443c0330) +#define IOMUXC_PAD_UART1_TXD_LPUART1_TX IOMUX_PADCFG(0x443c0184, 0x0, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_S400_UART_TX IOMUX_PADCFG(0x443c0184, 0x1, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_LPSPI2_PCS0 IOMUX_PADCFG(0x443c0184, 0x2, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_TPM1_CH1 IOMUX_PADCFG(0x443c0184, 0x3, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART1_TXD_GPIO1_IO05 IOMUX_PADCFG(0x443c0184, 0x5, 0x00000000, 0x00000000, 0x443c0334) +#define IOMUXC_PAD_UART2_RXD_LPUART2_RX IOMUX_PADCFG(0x443c0188, 0x0, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_LPUART1_CTS_B IOMUX_PADCFG(0x443c0188, 0x1, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_LPSPI2_SOUT IOMUX_PADCFG(0x443c0188, 0x2, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_TPM1_CH2 IOMUX_PADCFG(0x443c0188, 0x3, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_SAI1_MCLK IOMUX_PADCFG(0x443c0188, 0x4, 0x443c0448, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_RXD_GPIO1_IO06 IOMUX_PADCFG(0x443c0188, 0x5, 0x00000000, 0x00000000, 0x443c0338) +#define IOMUXC_PAD_UART2_TXD_LPUART2_TX IOMUX_PADCFG(0x443c018c, 0x0, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_LPUART1_RTS_B IOMUX_PADCFG(0x443c018c, 0x1, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_LPSPI2_SCK IOMUX_PADCFG(0x443c018c, 0x2, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_TPM1_CH3 IOMUX_PADCFG(0x443c018c, 0x3, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_UART2_TXD_GPIO1_IO07 IOMUX_PADCFG(0x443c018c, 0x5, 0x00000000, 0x00000000, 0x443c033c) +#define IOMUXC_PAD_PDM_CLK_PDM_CLK IOMUX_PADCFG(0x443c0190, 0x0, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_MQS1_LEFT IOMUX_PADCFG(0x443c0190, 0x1, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_LPTMR1_ALT1 IOMUX_PADCFG(0x443c0190, 0x4, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_GPIO1_IO08 IOMUX_PADCFG(0x443c0190, 0x5, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_CLK_CAN1_TX IOMUX_PADCFG(0x443c0190, 0x6, 0x00000000, 0x00000000, 0x443c0340) +#define IOMUXC_PAD_PDM_BIT_STREAM0_PDM_BIT_STREAM00 IOMUX_PADCFG(0x443c0194, 0x0, 0x443c0438, 0x00000002, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_MQS1_RIGHT IOMUX_PADCFG(0x443c0194, 0x1, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPSPI1_PCS1 IOMUX_PADCFG(0x443c0194, 0x2, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_TPM1_EXTCLK IOMUX_PADCFG(0x443c0194, 0x3, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_LPTMR1_ALT2 IOMUX_PADCFG(0x443c0194, 0x4, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_GPIO1_IO09 IOMUX_PADCFG(0x443c0194, 0x5, 0x00000000, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM0_CAN1_RX IOMUX_PADCFG(0x443c0194, 0x6, 0x443c0360, 0x00000000, 0x443c0344) +#define IOMUXC_PAD_PDM_BIT_STREAM1_PDM_BIT_STREAM01 IOMUX_PADCFG(0x443c0198, 0x0, 0x443c043c, 0x00000002, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_NMI_GLUE_NMI IOMUX_PADCFG(0x443c0198, 0x1, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPSPI2_PCS1 IOMUX_PADCFG(0x443c0198, 0x2, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_TPM2_EXTCLK IOMUX_PADCFG(0x443c0198, 0x3, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_LPTMR1_ALT3 IOMUX_PADCFG(0x443c0198, 0x4, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_GPIO1_IO10 IOMUX_PADCFG(0x443c0198, 0x5, 0x00000000, 0x00000000, 0x443c0348) +#define IOMUXC_PAD_PDM_BIT_STREAM1_CCMSRCGPCMIX_EXT_CLK1 IOMUX_PADCFG(0x443c0198, 0x6, 0x443c0368, 0x00000001, 0x443c0348) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_SYNC IOMUX_PADCFG(0x443c019c, 0x0, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_SAI1_TX_DATA01 IOMUX_PADCFG(0x443c019c, 0x1, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_LPSPI1_PCS0 IOMUX_PADCFG(0x443c019c, 0x2, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_LPUART2_DTR_B IOMUX_PADCFG(0x443c019c, 0x3, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_MQS1_LEFT IOMUX_PADCFG(0x443c019c, 0x4, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXFS_GPIO1_IO11 IOMUX_PADCFG(0x443c019c, 0x5, 0x00000000, 0x00000000, 0x443c034c) +#define IOMUXC_PAD_SAI1_TXC_SAI1_TX_BCLK IOMUX_PADCFG(0x443c01a0, 0x0, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_LPUART2_CTS_B IOMUX_PADCFG(0x443c01a0, 0x1, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_LPSPI1_SIN IOMUX_PADCFG(0x443c01a0, 0x2, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_LPUART1_DSR_B IOMUX_PADCFG(0x443c01a0, 0x3, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_CAN1_RX IOMUX_PADCFG(0x443c01a0, 0x4, 0x443c0360, 0x00000001, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXC_GPIO1_IO12 IOMUX_PADCFG(0x443c01a0, 0x5, 0x00000000, 0x00000000, 0x443c0350) +#define IOMUXC_PAD_SAI1_TXD0_SAI1_TX_DATA00 IOMUX_PADCFG(0x443c01a4, 0x0, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_LPUART2_RTS_B IOMUX_PADCFG(0x443c01a4, 0x1, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_LPSPI1_SCK IOMUX_PADCFG(0x443c01a4, 0x2, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_LPUART1_DTR_B IOMUX_PADCFG(0x443c01a4, 0x3, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_CAN1_TX IOMUX_PADCFG(0x443c01a4, 0x4, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_TXD0_GPIO1_IO13 IOMUX_PADCFG(0x443c01a4, 0x5, 0x00000000, 0x00000000, 0x443c0354) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_RX_DATA00 IOMUX_PADCFG(0x443c01a8, 0x0, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_SAI1_MCLK IOMUX_PADCFG(0x443c01a8, 0x1, 0x443c0448, 0x00000001, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_LPSPI1_SOUT IOMUX_PADCFG(0x443c01a8, 0x2, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_LPUART2_DSR_B IOMUX_PADCFG(0x443c01a8, 0x3, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_MQS1_RIGHT IOMUX_PADCFG(0x443c01a8, 0x4, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_SAI1_RXD0_GPIO1_IO14 IOMUX_PADCFG(0x443c01a8, 0x5, 0x00000000, 0x00000000, 0x443c0358) +#define IOMUXC_PAD_WDOG_ANY_WDOG1_WDOG_ANY IOMUX_PADCFG(0x443c01ac, 0x0, 0x00000000, 0x00000000, 0x443c035c) +#define IOMUXC_PAD_WDOG_ANY_GPIO1_IO15 IOMUX_PADCFG(0x443c01ac, 0x5, 0x00000000, 0x00000000, 0x443c035c) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX93_IMX93_PINMUX_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_gpio.h b/arch/arm64/src/imx9/hardware/imx9_gpio.h new file mode 100644 index 0000000000000..b13be0eaf6b6a --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_gpio.h @@ -0,0 +1,106 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H +#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_gpio.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define GPIO1 0 /* Port 1 index */ +#define GPIO2 1 /* Port 2 index */ +#define GPIO3 2 /* Port 3 index */ +#define GPIO4 3 /* Port 4 index */ +#define GPIO5 4 /* Port 5 index */ +#define GPIO6 5 /* Port 6 index */ +#define GPIO7 6 /* Port 7 index */ +#define GPIO8 7 /* Port 8 index */ +#define GPIO9 8 /* Port 9 index */ +#define GPIO10 9 /* Port 10 index */ +#define GPIO11 10 /* Port 11 index */ +#define GPIO12 11 /* Port 12 index */ +#define GPIO13 12 /* Port 13 index */ + +#define IMX9_GPIO_NPINS 32 /* Up to 32 pins per port */ + +/* Register bit definitions *************************************************/ + +/* Most registers are laid out simply with one bit per pin */ + +#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */ + +/* ICRN Register */ + +#define IMX9_GPIO_ICRN_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */ +#define IMX9_GPIO_ICRN_LK (1 << 23) /* Bit 23: Lock Register */ +#define IMX9_GPIO_ICRN_IRQS (1 << 20) /* Bit 20: Configures the selected interrupt, or DMA request. */ +#define IMX9_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */ +#define IMX9_GPIO_ICRN_MASK (0xf << IMX9_GPIO_ICRN_SHIFT) +# define IMX9_GPIO_ICRN_DISABLED (0 << IMX9_GPIO_ICRN_SHIFT) /* Interrupt Status Flag (ISF) is disabled */ +# define IMX9_GPIO_ICRN_DMARISING (1 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on rising edge */ +# define IMX9_GPIO_ICRN_DMAFALLING (2 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on falling edge */ +# define IMX9_GPIO_ICRN_DMABOTH (3 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on either edge */ +# define IMX9_GPIO_ICRN_ISFRISING (5 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on rising edge */ +# define IMX9_GPIO_ICRN_ISFFALLING (6 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on falling edge */ +# define IMX9_GPIO_ICRN_ISFBOTH (7 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on either edge */ +# define IMX9_GPIO_ICRN_ZERO (8 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 0 */ +# define IMX9_GPIO_ICRN_RISING (9 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on rising-edge */ +# define IMX9_GPIO_ICRN_FALLING (10 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on falling-edge */ +# define IMX9_GPIO_ICRN_BOTH (11 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on either edge */ +# define IMX9_GPIO_ICRN_ONE (12 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 1 */ + +/* Global Interrupt Control Low Register */ + +#define IMX9_GPIO_GICLR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ +#define IMX9_GPIO_GICLR_GIWD_MASK (0xffff << IMX9_GPIO_GICLR_GIWD_SHIFT) +# define IMX9_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWD_SHIFT) /* Pin n=0..15 */ + +#define IMX9_GPIO_GICLR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ +#define IMX9_GPIO_GICLR_GIWE_MASK (0xffff << IMX9_GPIO_GICLR_GIWE_SHIFT) +# define IMX9_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWE_SHIFT) /* Pin n=0..15 */ + +/* Global Interrupt Control High Register */ + +#define IMX9_GPIO_GICHR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */ +#define IMX9_GPIO_GICHR_GIWD_MASK (0xffff << IMX9_GPIO_GICHR_GIWD_SHIFT) +# define IMX9_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWD_SHIFT) /* Pin n=16..31 */ + +#define IMX9_GPIO_GICHR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */ +#define IMX9_GPIO_GICHR_GIWE_MASK (0xffff << IMX9_GPIO_GICHR_GIWE_SHIFT) +# define IMX9_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWE_SHIFT) /* Pin n=16..31 */ + +/* Interrupt Status Flag Register */ + +#define IMX9_GPIO_ISFR(n) (1 << (n)) /* Interrupt Status Flag, n=0-31 */ + +#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_iomuxc.h b/arch/arm64/src/imx9/hardware/imx9_iomuxc.h new file mode 100644 index 0000000000000..6e6fe9979c509 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_iomuxc.h @@ -0,0 +1,104 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_iomuxc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_iomux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Pad muxing */ + +#define IOMUXC_MUX_MODE_SHIFT (0) /* MODE: pin alternate function */ +#define IOMUXC_MUX_MODE_MASK (0x03 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT0 (0 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT1 (1 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT2 (2 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT3 (3 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT4 (4 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT5 (5 << IOMUXC_MUX_MODE_SHIFT) +#define IOMUXC_MUX_MODE_ALT6 (6 << IOMUXC_MUX_MODE_SHIFT) + +#define IOMUXC_MUX_SION_SHIFT (4) /* SION: Force input path */ +#define IPMUXC_MUX_SION_MASK (0x01 << IOMUXC_MUX_SION_SHIFT) +#define IOMUXC_MUX_SION_OFF (0 << IOMUXC_MUX_SION_SHIFT) +#define IOMUXC_MUX_SION_ON (1 << IOMUXC_MUX_SION_SHIFT) + +/* Pad control */ + +#define IOMUXC_PAD_DSE_SHIFT (1) /* DSE: Drive strength */ +#define IOMUXC_PAD_DSE_MASK (0x3f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X0 (0x00 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X1 (0x01 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X2 (0x03 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X3 (0x07 << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X4 (0x0f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X5 (0x1f << IOMUXC_PAD_DSE_SHIFT) +#define IOMUXC_PAD_DSE_X6 (0x3f << IOMUXC_PAD_DSE_SHIFT) + +#define IOMUXC_PAD_FSEL_SHIFT (7) /* FSEL: Slew rate control */ +#define IOMUXC_PAD_FSEL_MASK (0x02 << IOMUXC_PAD_FSEL_SHIFT) +#define IOMUXC_PAD_FSEL_SLOW (0 << IOMUXC_PAD_FSEL_SHIFT) +#define IOMUXC_PAD_FSEL_SSLOW (1 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly slow */ +#define IOMUXC_PAD_FSEL_SFAST (2 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly fast */ +#define IOMUXC_PAD_FSEL_FAST (3 << IOMUXC_PAD_FSEL_SHIFT) + +#define IOMUXC_PAD_PU_SHIFT (9) /* PU: Pull-up */ +#define IOMUXC_PAD_PU_MASK (0x01 << IOMUXC_PAD_PU_SHIFT) +#define IOMUXC_PAD_PU_OFF (0 << IOMUXC_PAD_PU_SHIFT) +#define IOMUXC_PAD_PU_ON (1 << IOMUXC_PAD_PU_SHIFT) + +#define IOMUXC_PAD_PD_SHIFT (10) /* PD: Pull-down */ +#define IOMUXC_PAD_PD_MASK (0x01 << IOMUXC_PAD_PD_SHIFT) +#define IOMUXC_PAD_PD_OFF (0 << IOMUXC_PAD_PD_SHIFT) +#define IOMUXC_PAD_PD_ON (1 << IOMUXC_PAD_PD_SHIFT) + +#define IOMUXC_PAD_OD_SHIFT (11) /* OD: Open-drain */ +#define IOMUXC_PAD_OD_MASK (0x01 << IOMUXC_PAD_OD_SHIFT) +#define IOMUXC_PAD_OD_DISABE (0 << IOMUXC_PAD_OD_SHIFT) +#define IOMUXC_PAD_OD_ENABLE (1 << IOMUXC_PAD_OD_SHIFT) + +#define IOMUXC_PAD_HYS_SHIFT (12) /* HYS: Enable schmitt-trigger on input */ +#define IOMUXC_PAD_HYS_MASK (0x01 << IOMUXC_PAD_HYS_SHIFT) +#define IOMUXC_PAD_HYS_ST_OFF (0 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger off */ +#define IOMUXC_PAD_HYS_ST_ON (1 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger on */ + +#define IOMUXC_PAD_APC_SHIFT (24) /* APC: Access control */ +#define IOMUXC_PAD_APC_MASK (0xff << IOMUXC_PAD_APC_SHIFT) + +/* Daisy chain control, 2 bits seems to be enough */ + +#define IOMUXC_DSY_SHIFT (0) +#define IOMUXC_DSY_MASK (0x03 << IOMUXC_DSY_SHIFT) + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H */ diff --git a/arch/arm64/src/imx9/hardware/imx9_pinmux.h b/arch/arm64/src/imx9/hardware/imx9_pinmux.h new file mode 100644 index 0000000000000..689485dff6db7 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_pinmux.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_pinmux.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_ARCH_CHIP_IMX93) +# include "hardware/imx93/imx93_pinmux.h" +#else +# error Unrecognized i.MX9 architecture +#endif + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_PINMUX_H */ diff --git a/arch/arm64/src/imx9/imx9_gpio.c b/arch/arm64/src/imx9/imx9_gpio.c new file mode 100644 index 0000000000000..54db67a1469b5 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpio.c @@ -0,0 +1,278 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpio.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#include "chip.h" +#include "arm64_internal.h" +#include "imx9_iomuxc.h" +#include "imx9_gpio.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpio_dirout + ****************************************************************************/ + +static inline void imx9_gpio_dirout(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMX9_GPIO_PDDR(port)); + regval |= GPIO_PIN(pin); + putreg32(regval, IMX9_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imx9_gpio_dirin + ****************************************************************************/ + +static inline void imx9_gpio_dirin(uint32_t port, uint32_t pin) +{ + uint32_t regval = getreg32(IMX9_GPIO_PDDR(port)); + regval &= ~GPIO_PIN(pin); + putreg32(regval, IMX9_GPIO_PDDR(port)); +} + +/**************************************************************************** + * Name: imx9_gpio_setoutput + ****************************************************************************/ + +static void imx9_gpio_setoutput(uint32_t port, uint32_t pin, bool value) +{ + uintptr_t regaddr = IMX9_GPIO_PDOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + if (value) + { + regval |= GPIO_PIN(pin); + } + else + { + regval &= ~GPIO_PIN(pin); + } + + putreg32(regval, regaddr); +} + +/**************************************************************************** + * Name: imx9_gpio_getpin_status + ****************************************************************************/ + +static inline bool imx9_gpio_get_pinstatus(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMX9_GPIO_PSOR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx9_gpio_getinput + ****************************************************************************/ + +static inline bool imx9_gpio_getinput(uint32_t port, uint32_t pin) +{ + uintptr_t regaddr = IMX9_GPIO_PDIR(port); + uint32_t regval; + + regval = getreg32(regaddr); + return ((regval & GPIO_PIN(pin)) != 0); +} + +/**************************************************************************** + * Name: imx9_gpio_configinput + ****************************************************************************/ + +static int imx9_gpio_configinput(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + /* Configure pin as in input */ + + imx9_gpio_dirin(port, pin); + + return OK; +} + +/**************************************************************************** + * Name: imx9_gpio_configoutput + ****************************************************************************/ + +static inline int imx9_gpio_configoutput(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value = ((pinset & GPIO_OUTPUT_ONE) != 0); + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + /* Set the output value */ + + imx9_gpio_setoutput(port, pin, value); + + /* Convert the configured input GPIO to an output */ + + imx9_gpio_dirout(port, pin); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_config_gpio + * + * Description: + * Configure a GPIO pin based on pin-encoded description of the pin. + * + ****************************************************************************/ + +int imx9_config_gpio(gpio_pinset_t pinset) +{ + irqstate_t flags; + int ret; + + /* Configure the pin as an input initially to avoid any spurious outputs */ + + flags = enter_critical_section(); + + /* Configure based upon the pin mode */ + + switch (pinset & GPIO_MODE_MASK) + { + case GPIO_INPUT: + { + /* Configure the pin as a GPIO input */ + + ret = imx9_gpio_configinput(pinset); + } + break; + + case GPIO_OUTPUT: + { + /* First configure the pin as a GPIO input to avoid output + * glitches. + */ + + ret = imx9_gpio_configinput(pinset); + if (ret >= 0) + { + /* Convert the input to an output */ + + ret = imx9_gpio_configoutput(pinset); + } + } + break; + +#ifdef CONFIG_IMX9_GPIO_IRQ + case GPIO_INTERRUPT: + { + /* Configure the pin as a GPIO input */ + + ret = imx9_gpio_configinput(pinset); + if (ret == OK) + { + ret = imx9_gpioirq_configure(pinset); + } + } + break; +#endif + + default: + ret = -EINVAL; + break; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: imx9_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imx9_gpio_write(gpio_pinset_t pinset, bool value) +{ + irqstate_t flags; + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + flags = enter_critical_section(); + imx9_gpio_setoutput(port, pin, value); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: imx9_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imx9_gpio_read(gpio_pinset_t pinset) +{ + irqstate_t flags; + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + bool value; + + DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS); + + flags = enter_critical_section(); + if ((pinset & (GPIO_OUTPUT)) == (GPIO_OUTPUT)) + { + value = imx9_gpio_get_pinstatus(port, pin); + } + else + { + value = imx9_gpio_getinput(port, pin); + } + + leave_critical_section(flags); + return value; +} diff --git a/arch/arm64/src/imx9/imx9_gpio.h b/arch/arm64/src/imx9/imx9_gpio.h new file mode 100644 index 0000000000000..229d4d635afa0 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpio.h @@ -0,0 +1,323 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpio.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_GPIO_H +#define __ARCH_ARM64_SRC_IMX9_IMX9_GPIO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "hardware/imx9_gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* GPIO pinset is a 16-bit word used to configure the GPIO settings. The + * encoding is as follows... + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MMVX BEEG GGGP PPPP + * GPIO INPUT 00.. BEEG GGGP PPPP + * INT INPUT 11.. BEEG GGGP PPPP + * GPIO OUTPUT 01V. ...G GGGP PPPP + */ + +/* Input/Output Selection: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * ENCODING MM.. .... .... .... + */ + +#define GPIO_MODE_SHIFT (14) /* Bits 14-15: Pin mode */ +#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT) +# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */ +# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */ +# define GPIO_INTERRUPT (2 << GPIO_MODE_SHIFT) /* Interrupt input */ + +/* Initial Output Value: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO OUTPUT 01V. .... .... .... + */ + +#define GPIO_OUTPUT_SHIFT (13) /* Bit 13: Initial output */ +#define GPIO_OUTPUT_MASK (0x1 << GPIO_OUTPUT_SHIFT) +# define GPIO_OUTPUT_ZERO (0 << GPIO_OUTPUT_SHIFT) /* Bit 29: 0=Initial output is low */ +# define GPIO_OUTPUT_ONE (1 << GPIO_OUTPUT_SHIFT) /* Bit 29: 1=Initial output is high */ + +/* Interrupt on both edges configuration + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * INT INPUT 11.. B... .... .... + */ + +#define GPIO_INTBOTHCFG_SHIFT (11) /* Bit 11: Interrupt both edges configuration */ +#define GPIO_INTBOTHCFG_MASK (1 << GPIO_INTBOTHCFG_SHIFT) +# define GPIO_INTBOTH_EDGES (1 << GPIO_INTBOTHCFG_SHIFT) + +/* Interrupt edge/level configuration + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * INT INPUT 11.. .EE. .... .... + */ + +#define GPIO_INTCFG_SHIFT (9) /* Bits 9-10: Interrupt edge/level configuration */ +#define GPIO_INTCFG_MASK (0x3 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_LOWLEVEL (0 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_HIGHLEVEL (1 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_RISINGEDGE (2 << GPIO_INTCFG_SHIFT) +# define GPIO_INT_FALLINGEDGE (3 << GPIO_INTCFG_SHIFT) + +/* GPIO Port Number + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO IN/OUT .... ...G GGG. .... + */ + +#define GPIO_PORT_SHIFT (5) /* Bits 5-8: GPIO port index */ +#define GPIO_PORT_MASK (0xf << GPIO_PORT_SHIFT) +# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */ +# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */ +# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */ +# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */ +# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */ +# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */ +# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */ +# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */ +# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */ +# define GPIO_PORT10 (GPIO10 << GPIO_PORT_SHIFT) /* GPIO10 */ +# define GPIO_PORT11 (GPIO11 << GPIO_PORT_SHIFT) /* GPIO11 */ +# define GPIO_PORT12 (GPIO12 << GPIO_PORT_SHIFT) /* GPIO12 */ +# define GPIO_PORT13 (GPIO13 << GPIO_PORT_SHIFT) /* GPIO13 */ + +/* GPIO Pin Number: + * + * 1111 1100 0000 0000 + * 5432 1098 7654 3210 + * GPIO IN/OUT .... .... ...P PPPP + */ + +#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO pin number */ +#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT) +# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */ +# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */ +# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */ +# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */ +# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */ +# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */ +# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */ +# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */ +# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */ +# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */ +# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */ +# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */ +# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */ +# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */ +# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */ +# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */ +# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */ +# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */ +# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */ +# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */ +# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */ +# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */ +# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */ +# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */ +# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */ +# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */ +# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */ +# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */ +# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */ +# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */ +# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */ +# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */ + +/* Port access via global LUT */ + +#define IMX9_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */ + +#define IMX9_GPIO_VERID(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_VERID_OFFSET) +#define IMX9_GPIO_PARAM(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PARAM_OFFSET) +#define IMX9_GPIO_LOCK(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_LOCK_OFFSET) +#define IMX9_GPIO_PCNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNS_OFFSET) +#define IMX9_GPIO_ICNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNS_OFFSET) +#define IMX9_GPIO_PCNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNP_OFFSET) +#define IMX9_GPIO_ICNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNP_OFFSET) +#define IMX9_GPIO_PDOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDOR_OFFSET) +#define IMX9_GPIO_PSOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PSOR_OFFSET) +#define IMX9_GPIO_PCOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCOR_OFFSET) +#define IMX9_GPIO_PTOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PTOR_OFFSET) +#define IMX9_GPIO_PDIR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDIR_OFFSET) +#define IMX9_GPIO_PDDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDDR_OFFSET) +#define IMX9_GPIO_PIDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PIDR_OFFSET) +#define IMX9_GPIO_GICLR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICLR_OFFSET) +#define IMX9_GPIO_GICHR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICHR_OFFSET) + +/* Interrupt status flags, these have two channels. Channel is selected by + * setting / clearing ICRN.IRQS bit. + */ + +#define IMX9_GPIO_ISFR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR0_OFFSET) +#define IMX9_GPIO_ISFR1(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR1_OFFSET) + +/* GPIO PIN[0...31] and ICR[0...31] */ + +#define IMX9_GPIO_P0DR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_P0DR_OFFSET) +#define IMX9_GPIO_PNDR(n, p) (IMX9_GPIO_P0DR(n) + ((p) * 0x4)) +#define IMX9_GPIO_ICR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICR0_OFFSET) +#define IMX9_GPIO_ICRN(n, p) (IMX9_GPIO_ICR0(n) + ((p) * 0x4)) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The smallest integer type that can hold the GPIO encoding */ + +typedef uint16_t gpio_pinset_t; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base + * addresses + */ + +EXTERN const uintptr_t g_gpio_base[]; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +void imx9_gpioirq_initialize(void); +#else +# define imx9_gpioirq_initialize() +#endif + +/**************************************************************************** + * Name: imx9_config_gpio + * + * Description: + * Configure a GPIO pin based on bit-encoded description of the pin. + * + ****************************************************************************/ + +int imx9_config_gpio(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imx9_gpio_write + * + * Description: + * Write one or zero to the selected GPIO pin + * + ****************************************************************************/ + +void imx9_gpio_write(gpio_pinset_t pinset, bool value); + +/**************************************************************************** + * Name: imx9_gpio_read + * + * Description: + * Read one or zero from the selected GPIO pin + * + ****************************************************************************/ + +bool imx9_gpio_read(gpio_pinset_t pinset); + +/**************************************************************************** + * Name: imx9_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_configure(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_configure(pinset) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_enable(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_enable(pinset) 0 +#endif + +/**************************************************************************** + * Name: imx9_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +#ifdef CONFIG_IMX9_GPIO_IRQ +int imx9_gpioirq_disable(gpio_pinset_t pinset); +#else +# define imx9_gpioirq_disable(pinset) 0 +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ARCH_ARM64_SRC_IMX9_IMX9_GPIO_H */ diff --git a/arch/arm64/src/imx9/imx9_gpiobase.c b/arch/arm64/src/imx9/imx9_gpiobase.c new file mode 100644 index 0000000000000..cf5e1f0ddb117 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpiobase.c @@ -0,0 +1,49 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpiobase.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "imx9_gpio.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_IMX93) +/* Base address for the GPIO memory mapped registers */ + +const uintptr_t g_gpio_base[] = +{ + IMX9_GPIO1_BASE, + IMX9_GPIO2_BASE, + IMX9_GPIO3_BASE, + IMX9_GPIO4_BASE, +}; +#else +# error Unrecognized i.MX9 architecture +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/arch/arm64/src/imx9/imx9_gpioirq.c b/arch/arm64/src/imx9/imx9_gpioirq.c new file mode 100644 index 0000000000000..e8ba83642c54e --- /dev/null +++ b/arch/arm64/src/imx9/imx9_gpioirq.c @@ -0,0 +1,356 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_gpioirq.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "arm64_internal.h" +#include "imx9_gpio.h" + +#ifdef CONFIG_IMX9_GPIO_IRQ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct imx9_portisr_s +{ + struct + { + xcpt_t isr; /* The interrupt service routine */ + void *arg; /* Argument passed to it */ + } + pins[IMX9_GPIO_NPINS]; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct imx9_portisr_s g_isrtab[IMX9_GPIO_NPORTS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioN_A_B_interrupt + * + * Description: + * GPIO interrupt handlers. + * + ****************************************************************************/ + +static int imx9_gpio_0_15_interrupt(int irq, void *context, void *arg) +{ + uint32_t port = *(uint32_t *)arg; + uint32_t status; + uint32_t pin; + uint32_t regaddr; + + /* Get the pending interrupt indications */ + + regaddr = IMX9_GPIO_ISFR0(port); + status = getreg32(regaddr) & 0x0000ffff; + + /* Decode the pending interrupts */ + + for (pin = 0; pin < 16 && status != 0; pin++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << pin); + if ((status & mask) != 0) + { + struct imx9_portisr_s *isrtab; + + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, regaddr); + status &= ~mask; + + /* Get the interrupt table for this port */ + + isrtab = &g_isrtab[port]; + if (isrtab->pins[pin].isr != NULL) + { + /* Run the user handler with the user's argument */ + + isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg); + } + } + } + + return OK; +} + +static int imx9_gpio_16_31_interrupt(int irq, void *context, void *arg) +{ + uint32_t port = *(uint32_t *)arg; + uint32_t status; + uint32_t pin; + uint32_t regaddr; + + /* Get the pending interrupt indications */ + + regaddr = IMX9_GPIO_ISFR0(port); + status = getreg32(regaddr) & 0xffff0000; + + /* Decode the pending interrupts */ + + for (pin = 16; pin < 32 && status != 0; pin++) + { + /* Is the IRQ associate with this pin pending? */ + + uint32_t mask = (1 << pin); + if ((status & mask) != 0) + { + struct imx9_portisr_s *isrtab; + + /* Yes, clear the status bit and dispatch the interrupt */ + + putreg32(mask, regaddr); + status &= ~mask; + + /* Get the interrupt table for this port */ + + isrtab = &g_isrtab[port]; + if (isrtab->pins[pin].isr != NULL) + { + /* Run the user handler with the user's argument */ + + isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg); + } + } + } + + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_gpioirq_initialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + ****************************************************************************/ + +void imx9_gpioirq_initialize(void) +{ + uint32_t port; + uint32_t pin; + + /* Disable all GPIO interrupts at the source */ + + for (port = 0; port < IMX9_GPIO_NPORTS; port++) + { + for (pin = 0; pin < IMX9_GPIO_NPINS; pin++) + { + /* Reset the interrupt configuration, disabling the interrupt */ + + putreg32(0, IMX9_GPIO_ICRN(port, pin)); + } + } + + /* Disable all unconfigured GPIO interrupts at the NVIC */ + + up_disable_irq(IMX9_IRQ_GPIO1_0_15); + up_disable_irq(IMX9_IRQ_GPIO1_16_31); + + up_disable_irq(IMX9_IRQ_GPIO2_0_15); + up_disable_irq(IMX9_IRQ_GPIO2_16_31); + + up_disable_irq(IMX9_IRQ_GPIO3_0_15); + up_disable_irq(IMX9_IRQ_GPIO3_16_31); + + up_disable_irq(IMX9_IRQ_GPIO4_0_15); + up_disable_irq(IMX9_IRQ_GPIO4_16_31); + + /* Attach all configured GPIO interrupts and enable the interrupt at the + * NVIC + */ + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO1_0_15, + imx9_gpio_0_15_interrupt, (void *)1)); + up_enable_irq(IMX9_IRQ_GPIO1_0_15); + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO1_16_31, + imx9_gpio_16_31_interrupt, (void *)1)); + up_enable_irq(IMX9_IRQ_GPIO1_16_31); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO2_0_15, + imx9_gpio_0_15_interrupt, (void *)2)); + up_enable_irq(IMX9_IRQ_GPIO1_0_15); + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO2_16_31, + imx9_gpio_16_31_interrupt, (void *)2)); + up_enable_irq(IMX9_IRQ_GPIO1_16_31); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO3_0_15, + imx9_gpio_0_15_interrupt, (void *)3)); + up_enable_irq(IMX9_IRQ_GPIO1_0_15); + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO3_16_31, + imx9_gpio_16_31_interrupt, (void *)3)); + up_enable_irq(IMX9_IRQ_GPIO1_16_31); + + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO4_0_15, + imx9_gpio_0_15_interrupt, (void *)4)); + up_enable_irq(IMX9_IRQ_GPIO1_0_15); + DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO4_16_31, + imx9_gpio_16_31_interrupt, (void *)4)); + up_enable_irq(IMX9_IRQ_GPIO1_16_31); +} + +/**************************************************************************** + * Name: imx9_gpioirq_attach + * + * Description: + * Attach a pin interrupt handler. + * + ****************************************************************************/ + +int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Atomically change the handler */ + + irqstate_t flags = enter_critical_section(); + + g_isrtab[port].pins[pin].isr = isr; + g_isrtab[port].pins[pin].arg = arg; + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_configure + * + * Description: + * Configure an interrupt for the specified GPIO pin. + * + ****************************************************************************/ + +int imx9_gpioirq_configure(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + + /* Nothing much to do here, just reset the IRQ config */ + + putreg32(0, IMX9_GPIO_ICRN(port, pin)); + + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_enable + * + * Description: + * Enable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +int imx9_gpioirq_enable(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t icr = (pinset & GPIO_INTCFG_MASK) >> GPIO_INTCFG_SHIFT; + uint32_t both = (pinset & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT; + uint32_t regval; + uintptr_t regaddr; + + /* Perform RMW to the specific pin */ + + regaddr = IMX9_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMX9_GPIO_ICRN_MASK; + + if (both) + { + regval |= IMX9_GPIO_ICRN_BOTH; + } + else if (icr == GPIO_INT_LOWLEVEL) + { + regval |= IMX9_GPIO_ICRN_ZERO; + } + else if (icr == GPIO_INT_HIGHLEVEL) + { + regval |= IMX9_GPIO_ICRN_ONE; + } + else if (icr == GPIO_INT_RISINGEDGE) + { + regval |= IMX9_GPIO_ICRN_RISING; + } + else /* GPIO_INT_FALLINGEDGE */ + { + regval |= IMX9_GPIO_ICRN_FALLING; + } + + putreg32(regval, regaddr); + return OK; +} + +/**************************************************************************** + * Name: imx9_gpioirq_disable + * + * Description: + * Disable the interrupt for specified GPIO IRQ + * + ****************************************************************************/ + +int imx9_gpioirq_disable(gpio_pinset_t pinset) +{ + uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT; + uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT; + uint32_t regval; + uintptr_t regaddr; + + /* Perform RMW to the specific pin */ + + regaddr = IMX9_GPIO_ICRN(port, pin); + regval = getreg32(regaddr); + regval &= ~IMX9_GPIO_ICRN_MASK; + + putreg32(regval, regaddr); + return OK; +} + +#endif /* CONFIG_IMX9_GPIO_IRQ */ diff --git a/arch/arm64/src/imx9/imx9_iomuxc.c b/arch/arm64/src/imx9/imx9_iomuxc.c new file mode 100644 index 0000000000000..b5f8b657cf996 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_iomuxc.c @@ -0,0 +1,116 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_iomuxc.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "arm64_internal.h" +#include "imx9_iomuxc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + * Input Parameters: + * cfg - The IOMUX configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_configure(iomux_cfg_t cfg) +{ + if (!cfg.padcfg.ctlreg) + { + return -EINVAL; + } + + putreg32(cfg.padcfg.mode | cfg.mux, cfg.padcfg.ctlreg); + + if (cfg.padcfg.dsyreg) + { + putreg32(cfg.padcfg.dsy, cfg.padcfg.dsyreg); + } + + if (cfg.padcfg.padreg) + { + putreg32(cfg.pad, cfg.padcfg.padreg); + } + + return OK; +} + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This can be used to forcibly set a pad to GPIO mode. This overrides and + * disconnects any peripheral using the pin. + * + * Input Parameters: + * cfg - The IOMUX configuration. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion) +{ + uint32_t reg_sion; + + if (!cfg.padcfg.ctlreg) + { + return -EINVAL; + } + + /* Set sion if requested to do so */ + + reg_sion = sion ? IOMUXC_MUX_SION_ON : 0; + + /* Based on pad number, either ALT0/ALT5 sets the pad as GPIO */ + + if ((cfg.padcfg.ctlreg >= IOMUXC_MUX_CTL_GPIO_IO00_OFFSET) && + (cfg.padcfg.ctlreg <= IOMUXC_MUX_CTL_GPIO_IO29_OFFSET)) + { + putreg32(IOMUXC_MUX_MODE_ALT0 | reg_sion, cfg.padcfg.ctlreg); + } + else + { + putreg32(IOMUXC_MUX_MODE_ALT5 | reg_sion, cfg.padcfg.ctlreg); + } + + return OK; +} diff --git a/arch/arm64/src/imx9/imx9_iomuxc.h b/arch/arm64/src/imx9/imx9_iomuxc.h new file mode 100644 index 0000000000000..80bacc7e5c8d6 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_iomuxc.h @@ -0,0 +1,117 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_iomuxc.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "hardware/imx9_iomuxc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IOMUX_PADCFG(_ctlreg, _mode, _dsyreg, _dsy, _padreg) \ + { \ + .ctlreg = (_ctlreg), \ + .mode = (_mode), \ + .dsyreg = (_dsyreg), \ + .dsy = (_dsy), \ + .padreg = (_padreg), \ + } + +#define IOMUX_CFG(_padcfg, _pad, _mux) \ + (iomux_cfg_t) \ + { \ + .padcfg = _padcfg, \ + .pad = (_pad), \ + .mux = (_mux), \ + } + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Information for the pad alternate function */ + +struct iomux_padcfg_s +{ + /* Register offsets for PAD */ + + uintptr_t ctlreg; + uintptr_t padreg; + uintptr_t dsyreg; + + /* ALT and input daisy configuration for pad */ + + uint32_t mode; + uint32_t dsy; +}; + +struct iomux_cfg_s +{ + struct iomux_padcfg_s padcfg; + + /* Register values */ + + uint32_t pad; + uint32_t mux; +}; +typedef struct iomux_cfg_s iomux_cfg_t; + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This function writes the encoded pad configuration to the Pad Control + * register. + * + * Input Parameters: + * cfg - The IOMUX configuration + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_configure(iomux_cfg_t cfg); + +/**************************************************************************** + * Name: imx9_iomux_configure + * + * Description: + * This can be used to forcibly set a pad to GPIO mode. This overrides and + * disconnects any peripheral using the pin. + * + * Input Parameters: + * cfg - The IOMUX configuration. + * sion - if true; sets SION, otherwise clears it. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion); diff --git a/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig b/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig index 9bf34ecc59718..90729bcb457ed 100644 --- a/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig +++ b/boards/arm64/imx9/imx93-evk/configs/nsh/defconfig @@ -32,6 +32,7 @@ CONFIG_FS_ROMFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y CONFIG_IDLETHREAD_STACKSIZE=8192 +CONFIG_IMX9_GPIO_IRQ=y CONFIG_IMX9_UART1=y CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INTELHEX_BINARY=y