From f8c96aad593785df3a7cdaec43bfdb92650f87fa Mon Sep 17 00:00:00 2001 From: Jukka Laitinen Date: Tue, 1 Oct 2024 15:27:17 +0300 Subject: [PATCH] WIP Signed-off-by: Jukka Laitinen --- arch/arm64/src/imx9/Kconfig | 113 ++ arch/arm64/src/imx9/Make.defs | 4 + arch/arm64/src/imx9/hardware/imx9_flexcan.h | 440 ++++ arch/arm64/src/imx9/imx9_flexcan.c | 2024 +++++++++++++++++++ arch/arm64/src/imx9/imx9_flexcan.h | 84 + 5 files changed, 2665 insertions(+) create mode 100644 arch/arm64/src/imx9/hardware/imx9_flexcan.h create mode 100644 arch/arm64/src/imx9/imx9_flexcan.c create mode 100644 arch/arm64/src/imx9/imx9_flexcan.h diff --git a/arch/arm64/src/imx9/Kconfig b/arch/arm64/src/imx9/Kconfig index 8b674acdd9735..4870d66de2af4 100644 --- a/arch/arm64/src/imx9/Kconfig +++ b/arch/arm64/src/imx9/Kconfig @@ -1040,6 +1040,119 @@ config IMX9_ENET1_PHYINIT endmenu # IMX9_ENET +config IMX9_FLEXCAN + bool + default n + select NET_CAN + select NET_CAN_HAVE_CANFD + select ARCH_HAVE_NETDEV_STATISTICS + +menu "FLEXCAN Peripherals" + +config IMX9_FLEXCAN1 + bool "FLEXCAN1" + default n + select IMX9_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + +config IMX9_FLEXCAN2 + bool "FLEXCAN2" + default n + select IMX9_FLEXCAN + select NET_CAN_HAVE_TX_DEADLINE + +if IMX9_FLEXCAN1 || IMX9_FLEXCAN2 + +config IMX9_FLEXCAN_TXMB + int "Number of TX message buffers" + default 3 + ---help--- + This defines number of TX messages buffers. Please note that + maximum number of all message buffers is 13 (one MB has to + be reserved for chip errata ERR005829). + +config IMX9_FLEXCAN_RXMB + int "Number of RX message buffers" + default 10 + ---help--- + This defines number of RX messages buffers. Please note that + maximum number of all message buffers is 13 (one MB has to + be reserved for chip errata ERR005829). + +endif + +endmenu # FLEXCAN Peripherals + +menu "FLEXCAN1 Configuration" + depends on IMX9_FLEXCAN1 + +config IMX9_FLEXCAN1_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config IMX9_FLEXCAN1_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config IMX9_FLEXCAN1_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config IMX9_FLEXCAN1_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config IMX9_FLEXCAN1_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config IMX9_FLEXCAN1_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMX9_FLEXCAN1 + +menu "FLEXCAN2 Configuration" + depends on IMX9_FLEXCAN2 + +config IMX9_FLEXCAN2_BITRATE + int "CAN bitrate" + depends on !NET_CAN_CANFD + default 1000000 + +config IMX9_FLEXCAN2_SAMPLEP + int "CAN sample point" + depends on !NET_CAN_CANFD + default 80 + +config IMX9_FLEXCAN2_ARBI_BITRATE + int "CAN FD Arbitration phase bitrate" + depends on NET_CAN_CANFD + default 1000000 + +config IMX9_FLEXCAN2_ARBI_SAMPLEP + int "CAN FD Arbitration phase sample point" + depends on NET_CAN_CANFD + default 80 + +config IMX9_FLEXCAN2_DATA_BITRATE + int "CAN FD Data phase bitrate" + depends on NET_CAN_CANFD + default 4000000 + +config IMX9_FLEXCAN2_DATA_SAMPLEP + int "CAN FD Data phase sample point" + depends on NET_CAN_CANFD + default 90 + +endmenu # IMX9_FLEXCAN2 + endmenu # iMX Peripheral Selection endif # ARCH_CHIP_IMX9 diff --git a/arch/arm64/src/imx9/Make.defs b/arch/arm64/src/imx9/Make.defs index 0c9291d2e5255..3dba163b288d0 100644 --- a/arch/arm64/src/imx9/Make.defs +++ b/arch/arm64/src/imx9/Make.defs @@ -87,3 +87,7 @@ ifeq ($(CONFIG_IMX9_BOOTLOADER), y) CHIP_CSRCS += $(DDR_CSRCS) endif endif + +ifeq ($(CONFIG_IMX9_FLEXCAN), y) + CHIP_CSRCS += imx9_flexcan.c +endif diff --git a/arch/arm64/src/imx9/hardware/imx9_flexcan.h b/arch/arm64/src/imx9/hardware/imx9_flexcan.h new file mode 100644 index 0000000000000..e1dc42f31a774 --- /dev/null +++ b/arch/arm64/src/imx9/hardware/imx9_flexcan.h @@ -0,0 +1,440 @@ +/**************************************************************************** + * arch/arm64/src/imx9/hardware/imx9_flexcan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_FLEXCAN_H +#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_FLEXCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Offsets *********************************************************/ + +#define IMX9_CAN_MCR_OFFSET 0x0000 /* Module Configuration Register */ +#define IMX9_CAN_CTRL1_OFFSET 0x0004 /* Control 1 Register */ +#define IMX9_CAN_TIMER_OFFSET 0x0008 /* Free Running Timer */ +#define IMX9_CAN_RXMGMASK_OFFSET 0x0010 /* Rx Mailboxes Global Mask Register */ +#define IMX9_CAN_RX14MASK_OFFSET 0x0014 /* Rx 14 Mask Register */ +#define IMX9_CAN_RX15MASK_OFFSET 0x0018 /* Rx 15 Mask Register */ +#define IMX9_CAN_ECR_OFFSET 0x001c /* Error Counter */ +#define IMX9_CAN_ESR1_OFFSET 0x0020 /* Error and Status 1 Register */ +#define IMX9_CAN_IMASK2_OFFSET 0x0024 /* Interrupt Masks 2 Register */ +#define IMX9_CAN_IMASK1_OFFSET 0x0028 /* Interrupt Masks 1 Register */ +#define IMX9_CAN_IFLAG2_OFFSET 0x002c /* Interrupt Flags 2 Register */ +#define IMX9_CAN_IFLAG1_OFFSET 0x0030 /* Interrupt Flags 1 Register */ +#define IMX9_CAN_CTRL2_OFFSET 0x0034 /* Control 2 Register */ +#define IMX9_CAN_ESR2_OFFSET 0x0038 /* Error and Status 2 Register */ +#define IMX9_CAN_CRCR_OFFSET 0x0044 /* CRC Register */ +#define IMX9_CAN_RXFGMASK_OFFSET 0x0048 /* Rx FIFO Global Mask Register */ +#define IMX9_CAN_RXFIR_OFFSET 0x004c /* Rx FIFO Information Register */ +#define IMX9_CAN_CBT_OFFSET 0x0050 /* CAN Bit Timing Register */ +#define IMX9_CAN_IMASK3_OFFSET 0x006C /* Interrupt Masks 3 Register */ +#define IMX9_CAN_IFLAG3_OFFSET 0x0074 /* Interrupt Flags 3 Register */ +#define IMX9_CAN_ET_OFFSET 0x0078 /* External Timer Register */ +#define IMX9_CAN_FLTC_IE_OFFSET 0x007c /* Fault Confinement Interrupt Enable Register */ + +#define IMX9_CAN_RXIMR_OFFSET(n) (0x0880+((n)<<2)) /* Rn Individual Mask Registers */ + +#define IMX9_CAN_MECR_OFFSET 0x0ae0 /* Memory Error Control Register */ +#define IMX9_CAN_ERRIAR_OFFSET 0x0ae4 /* Error Injection Address Register */ +#define IMX9_CAN_ERRIDPR_OFFSET 0x0ae8 /* Error Injection Data Pattern Register */ +#define IMX9_CAN_ERRIPPR_OFFSET 0x0aec /* Error Injection Parity Pattern Register */ +#define IMX9_CAN_REARRAR_OFFSET 0x0af0 /* Error Report Address Register */ +#define IMX9_CAN_RERRDR_OFFSET 0x0af4 /* Error Report Data Register */ +#define IMX9_CAN_RERRSYNR_OFFSET 0x0af8 /* Error Report Syndrome Register */ +#define IMX9_CAN_ERRSR_OFFSET 0x0afc /* Error Status Register */ +#define IMX9_CAN_EPRS_OFFSET 0x0bf0 /* Enhanced CAN Bit Timing Prescalers Register */ +#define IMX9_CAN_ENCBT_OFFSET 0x0bf4 /* Enhanced Nominal CAN Bit Timing Register */ +#define IMX9_CAN_EDCBT_OFFSET 0x0bf8 /* Enhanced Data Phase CAN Bit Timing Register */ +#define IMX9_CAN_ETDC_OFFSET 0x0bfc /* Enhanced Transceiver Delay Compensation Register */ + +#define IMX9_CAN_FDCTRL_OFFSET 0x0c00 /* CAN FD Control Register */ +#define IMX9_CAN_FDCBT_OFFSET 0x0c04 /* CAN FD Bit Timing Register */ +#define IMX9_CAN_FDCRC_OFFSET 0x0c08 /* CAN FD CRC register */ + +/* Register Bit Definitions *************************************************/ + +/* Module Configuration Register */ + +#define CAN_MCR_MAXMB_SHIFT (0) /* Bits 0-6: Number of the Last Message Buffer */ +#define CAN_MCR_MAXMB_MASK (0x7f << CAN_MCR_MAXMB_SHIFT) +#define CAN_MCR_TPOE (1 << 7) /* Bit 7: TX Pin Override Enable */ + +#define CAN_MCR_IDAM_SHIFT (8) /* Bits 8-9: ID Acceptance Mode */ +#define CAN_MCR_IDAM_MASK (3 << CAN_MCR_IDAM_SHIFT) +# define CAN_MCR_IDAM_FMTA (0 << CAN_MCR_IDAM_SHIFT) /* Format A: One full ID */ +# define CAN_MCR_IDAM_FMTB (1 << CAN_MCR_IDAM_SHIFT) /* Format B: Two full (or partial) IDs */ +# define CAN_MCR_IDAM_FMTC (2 << CAN_MCR_IDAM_SHIFT) /* Format C: Four partial IDs */ +# define CAN_MCR_IDAM_FMTD (3 << CAN_MCR_IDAM_SHIFT) /* Format D: All frames rejected */ + +#define CAN_MCR_TPOV (1 << 10) /* Bit 10: TX Pin Override Value */ +#define CAN_MCR_FDEN (1 << 11) /* Bit 11: CAN FD Operation Enable */ +#define CAN_MCR_AEN (1 << 12) /* Bit 12: Abort Enable */ +#define CAN_MCR_LPRIOEN (1 << 13) /* Bit 13: Local Priority Enable */ + /* Bit 14: Reserved */ +#define CAN_MCR_DMA (1 << 15) /* Bit 15: DMA Enable */ +#define CAN_MCR_IRMQ (1 << 16) /* Bit 16: Individual Rx Masking and Queue Enable */ +#define CAN_MCR_SRXDIS (1 << 17) /* Bit 17: Self Reception Disable */ +#define CAN_MCR_DOZE (1 << 18) /* Bit 18: Doze Mode Enable */ +#define CAN_MCR_WAKSRC (1 << 19) /* Bit 19: Wake Up Source */ +#define CAN_MCR_LPMACK (1 << 20) /* Bit 20: Low Power Mode Acknowledge */ +#define CAN_MCR_WRNEN (1 << 21) /* Bit 21: Warning Interrupt Enable */ +#define CAN_MCR_SLFWAK (1 << 22) /* Bit 22: Self Wake Up */ +#define CAN_MCR_SUPV (1 << 23) /* Bit 23: Supervisor Mode */ +#define CAN_MCR_FRZACK (1 << 24) /* Bit 24: Freeze Mode Acknowledge */ +#define CAN_MCR_SOFTRST (1 << 25) /* Bit 25: Soft Reset */ +#define CAN_MCR_WAKMSK (1 << 26) /* Bit 26: Wake Up Interrupt Mask */ +#define CAN_MCR_NOTRDY (1 << 27) /* Bit 27: FlexCAN Not Ready */ +#define CAN_MCR_HALT (1 << 28) /* Bit 28: Halt FlexCAN */ +#define CAN_MCR_RFEN (1 << 29) /* Bit 29: Legacy Rx FIFO Enable */ +#define CAN_MCR_FRZ (1 << 30) /* Bit 30: Freeze Enable */ +#define CAN_MCR_MDIS (1 << 31) /* Bit 31: Module Disable */ + +/* Control 1 Register */ + +#define CAN_CTRL1_PROPSEG_SHIFT (0) /* Bits 0-2: Propagation Segment */ +#define CAN_CTRL1_PROPSEG_MASK (7 << CAN_CTRL1_PROPSEG_SHIFT) +#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK) +#define CAN_CTRL1_LOM (1 << 3) /* Bit 3: Listen-Only Mode */ +#define CAN_CTRL1_LBUF (1 << 4) /* Bit 4: Lowest Buffer Transmitted First */ +#define CAN_CTRL1_TSYN (1 << 5) /* Bit 5: Timer Sync */ +#define CAN_CTRL1_BOFFREC (1 << 6) /* Bit 6: Bus Off Recovery */ +#define CAN_CTRL1_SMP (1 << 7) /* Bit 7: CAN Bit Sampling */ +#define CAN_CTRL1_ROM (1 << 7) /* Bit 8: Restricted Operation Mode */ + /* Bit 9: Reserved */ +#define CAN_CTRL1_RWRNMSK (1 << 10) /* Bit 10: Rx Warning Interrupt Mask */ +#define CAN_CTRL1_TWRNMSK (1 << 11) /* Bit 11: Tx Warning Interrupt Mask */ +#define CAN_CTRL1_LPB (1 << 12) /* Bit 12: Loop Back Mode */ +#define CAN_CTRL1_CLKSRC (1 << 13) /* Bit 13: CAN Engine Clock Source */ +#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Mask */ +#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Mask */ +#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 */ +#define CAN_CTRL1_PSEG2_MASK (7 << CAN_CTRL1_PSEG2_SHIFT) +#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK) +#define CAN_CTRL1_PSEG1_SHIFT (19) /* Bits 19-21: Phase Segment 1 */ +#define CAN_CTRL1_PSEG1_MASK (7 << CAN_CTRL1_PSEG1_SHIFT) +#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK) +#define CAN_CTRL1_RJW_SHIFT (22) /* Bits 22-23: Resync Jump Width */ +#define CAN_CTRL1_RJW_MASK (3 << CAN_CTRL1_RJW_SHIFT) +#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK) +#define CAN_CTRL1_PRESDIV_SHIFT (24) /* Bits 24-31: Prescaler Division Factor */ +#define CAN_CTRL1_PRESDIV_MASK (0xff << CAN_CTRL1_PRESDIV_SHIFT) +#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK) + +/* Free Running Timer */ + +#define CAN_TIMER_SHIFT (0) /* Bits 0-15: Timer value */ +#define CAN_TIMER_MASK (0xffff << CAN_TIMER_SHIFT) + /* Bits 16-31: Reserved */ + +/* Rx Mailboxes Global Mask Register (32 Rx Mailboxes Global Mask Bits) */ + +#define CAN_RXMGMASK(n) (1 << (n)) /* Bit n: Rx Mailboxe n Global Mask Bit */ + +/* Rx 14 Mask Register */ + +#define CAN_RX14MASK(n) (1 << (n)) /* Bit n: Rx Buffer 14 Mask Bit n */ + +/* Rx 15 Mask Register */ + +#define CAN_RX15MASK(n) (1 << (n)) /* Bit n: Rx Buffer 15 Mask Bit n */ + +/* Error Counter */ + +#define CAN_ECR_TXERRCNT_SHIFT (0) /* Bits 0-7: Transmit Error Counter */ +#define CAN_ECR_TXERRCNT_MASK (0xff << CAN_ECR_TXERRCNT_SHIFT) +#define CAN_ECR_RXERRCNT_SHIFT (8) /* Bits 8-15: Receive Error Counter */ +#define CAN_ECR_RXERRCNT_MASK (0xff << CAN_ECR_RXERRCNT_SHIFT) +#define CAN_ECR_TXERRCNTFAST_SHIFT (16) /* Bits 16-23: Transmit Error Counter for fast bits */ +#define CAN_ECR_TXERRCNTFAST_MASK (0xff << CAN_ECR_TXERRCNTFAST_SHIFT) +#define CAN_ECR_RXERRCNTFAST_SHIFT (24) /* Bits 24-31: Receive Error Counter for fast bits */ +#define CAN_ECR_RXERRCNTFAST_MASK (0xff << CAN_ECR_RXERRCNTFAST_SHIFT) + /* Bits 16-31: Reserved for FlexCAN1 and FlexCAN2 */ + +/* Error and Status 1 Register */ + +#define CAN_ESR1_WAKINT (1 << 0) /* Bit 0: Wake-Up Interrupt */ +#define CAN_ESR1_ERRINT (1 << 1) /* Bit 1: Error Interrupt */ +#define CAN_ESR1_BOFFINT (1 << 2) /* Bit 2: 'Bus Off' Interrupt */ +#define CAN_ESR1_RX (1 << 3) /* Bit 3: FlexCAN in Reception */ +#define CAN_ESR1_FLTCONF_SHIFT (4) /* Bits 4-5: Fault Confinement State */ +#define CAN_ESR1_FLTCONF_MASK (3 << CAN_ESR1_FLTCONF_SHIFT) +# define CAN_ESR1_FLTCONF_ACTV (0 << CAN_ESR1_FLTCONF_SHIFT) + /* Error Active */ +# define CAN_ESR1_FLTCONF_PASV (1 << CAN_ESR1_FLTCONF_SHIFT) + /* Error Passive */ +# define CAN_ESR1_FLTCONF_OFF (2 << CAN_ESR1_FLTCONF_SHIFT) + /* Bus Off */ +#define CAN_ESR1_TX (1 << 6) /* Bit 6: FlexCAN in Transmission */ +#define CAN_ESR1_IDLE (1 << 7) /* Bit 7: CAN bus is in IDLE state */ +#define CAN_ESR1_RXWRN (1 << 8) /* Bit 8: Rx Error Warning */ +#define CAN_ESR1_TXWRN (1 << 9) /* Bit 9: TX Error Warning */ +#define CAN_ESR1_STFERR (1 << 10) /* Bit 10: Stuffing Error */ +#define CAN_ESR1_FRMERR (1 << 11) /* Bit 11: Form Error */ +#define CAN_ESR1_CRCERR (1 << 12) /* Bit 12: Cyclic Redundancy Check Error */ +#define CAN_ESR1_ACKERR (1 << 13) /* Bit 13: Acknowledge Error */ +#define CAN_ESR1_BIT0ERR (1 << 14) /* Bit 14: Bit0 Error */ +#define CAN_ESR1_BIT1ERR (1 << 15) /* Bit 15: Bit1 Error */ +#define CAN_ESR1_RWRNINT (1 << 16) /* Bit 16: Rx Warning Interrupt Flag */ +#define CAN_ESR1_TWRNINT (1 << 17) /* Bit 17: Tx Warning Interrupt Flag */ +#define CAN_ESR1_SYNCH (1 << 18) /* Bit 18: CAN Synchronization Status */ +#define CAN_ESR1_BOFFDONEINT (1 << 19) /* Bit 19: Bus Off Done Interrupt */ +#define CAN_ESR1_ERRINTFAST (1 << 20) /* Bit 20: Error Iterrupt for Errors Detected in Data Phase of CAN FD frames */ +#define CAN_ESR1_ERROVR (1 << 21) /* Bit 21: Error Overrun */ +#define CAN_ESR1_ATP (1 << 22) /* Bit 22: Active to Passive State */ +#define CAN_ESR1_PTA (1 << 23) /* Bit 23: Passive to Active State */ + /* Bits 24-25: Reserved */ +#define CAN_ESR1_STFERRFAST (1 << 26) /* Bit 26: Stuffing Error in the Data Phase of CAN FD frames */ +#define CAN_ESR1_FRMERRFAST (1 << 27) /* Bit 27: Form Error in the Data Phase of CAN FD frames */ +#define CAN_ESR1_CRCERRFAST (1 << 28) /* Bit 28: Cyclic Redundancy Check Error in the CRC field of CAN FD frames */ + /* Bit 29: Reserved */ +#define CAN_ESR1_BIT0ERRFAST (1 << 30) /* Bit 30: Bit0 Error in the Data Phase of CAN FD frames */ +#define CAN_ESR1_BIT1ERRFAST (1 << 31) /* Bit 31: Bit1 Error in the Data Phase of CAN FD frames */ + /* Bits 19-31: Reserved for FlexCAN1 and FlexCAN2 */ + +/* Interrupt Masks 2 Register */ + +#define CAN_IMASK2(n) (1 << (n)) /* Bit n: Buffer MBn Mask */ + +/* Interrupt Masks 1 Register */ + +#define CAN_IMASK1(n) (1 << (n)) /* Bit n: Buffer MBn Mask */ + +/* Interrupt Flags 2 Register */ + +#define CAN_IFLAG2(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt */ + +/* Interrupt Flags 1 Register */ + +#define CAN_IFLAG1(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt, n=0..4,8..31 */ + +/* Control 2 Register */ + + /* Bits 0-1: Reserved */ +#define CAN_CTRL2_RETRY_SHIFT (2) /* Bits 2-4: Number of Retransmission Requests */ +#define CAN_CTRL2_RETRY_MASK (7 << CAN_CTRL2_RETRY_SHIFT) +#define CAN_CTRL2_RETRY(x) (((x) << CAN_CTRL2_RETRY_SHIFT) & CAN_CTRL2_RETRY_MASK) + /* Bit 5: Reserved */ +#define CAN_CTRL2_TSTAMPCAP_SHIFT (6) /* Bits 6-7: Timestamp Capture Point */ +#define CAN_CTRL2_TSTAMPCAP_MASK (3 << CAN_CTRL2_TSTAMPCAP_SHIFT) +# define CAN_CTRL2_TSTAMPCAP_DIS (0 << CAN_CTRL2_TSTAMPCAP_SHIFT) /* Disabled */ +# define CAN_CTRL2_TSTAMPCAP_EOF (1 << CAN_CTRL2_TSTAMPCAP_SHIFT) /* End of CAN frame */ +# define CAN_CTRL2_TSTAMPCAP_SOF (2 << CAN_CTRL2_TSTAMPCAP_SHIFT) /* Start of CAN frame */ +# define CAN_CTRL2_TSTAMPCAP_CSOF (3 << CAN_CTRL2_TSTAMPCAP_SHIFT) /* Start of classical CAN frame or res for CAN FD */ + +#define CAN_CTRL2_MBTSBASE_SHIFT (8) /* Bits 8-9: Message Buffer Timestamp Base */ +#define CAN_CTRL2_MBTSBASE_MASK (3 << CAN_CTRL2_MBTSBASE_SHIFT) +# define CAN_CTRL2_MBTSBASE_TIMER (0 << CAN_CTRL2_MBTSBASE_SHIFT) /* TIMER */ +# define CAN_CTRL2_MBTSBASE_LOWER (1 << CAN_CTRL2_MBTSBASE_SHIFT) /* Lower 16 bits of high-resolution timer */ +# define CAN_CTRL2_MBTSBASE_UPPER (2 << CAN_CTRL2_MBTSBASE_SHIFT) /* Upper 16 bits of high-resolution timer */ + +#define CAN_CTRL2_FLTRXN (1 << 10) /* Bit 10: Fault reaction */ +#define CAN_CTRL2_EDFLTDIS (1 << 11) /* Bit 11: Edge Filter Disable */ +#define CAN_CTRL2_ISOCANFDEN (1 << 12) /* Bit 12: ISO CAN FD Enable */ +#define CAN_CTRL2_BTE (1 << 13) /* Bit 13: Bit Timing Expansion Enable */ +#define CAN_CTRL2_PREXCEN (1 << 14) /* Bit 14: Protocol Exception Enable */ +#define CAN_CTRL2_TIMERSRC (1 << 15) /* Bit 15: Timer Source */ +#define CAN_CTRL2_EACEN (1 << 16) /* Bit 16: Entire Frame Arbitration Field Comparison Enable (Rx) */ +#define CAN_CTRL2_RRS (1 << 17) /* Bit 17: Remote Request Storing */ +#define CAN_CTRL2_MRP (1 << 18) /* Bit 18: Mailboxes Reception Priority */ +#define CAN_CTRL2_TASD_SHIFT (19) /* Bits 19-23: Tx Arbitration Start Delay */ +#define CAN_CTRL2_TASD_MASK (31 << CAN_CTRL2_TASD_SHIFT) +#define CAN_CTRL2_RFFN_SHIFT (24) /* Bits 24-27: Number of Rx FIFO Filters */ +#define CAN_CTRL2_RFFN_MASK (15 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_8MB (0 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_16MB (1 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_24MB (2 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_32MB (3 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_40MB (4 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_48MB (5 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_56MB (6 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_64MB (7 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_72MB (8 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_80MB (9 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_88MB (10 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_96MB (11 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_104MB (12 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_112MB (13 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_120MB (14 << CAN_CTRL2_RFFN_SHIFT) +# define CAN_CTRL2_RFFN_128MB (15 << CAN_CTRL2_RFFN_SHIFT) + +#define CAN_CTRL2_WRMFRZ (1 << 28) /* Bit 28: Write Access to Memory in Freeze Mode */ +#define CAN_CTRL2_ECRWRE (1 << 29) /* Bit 28: Error Correction Configuration Register Write Enable */ +#define CAN_CTRL2_BOFFDONEMSK (1 << 30) /* Bit 30: Bus Off Done Interrupt Mask */ +#define CAN_CTRL2_ERRMSKFAST (1 << 31) /* Bit 31: Error Interrupt for Errors Detected in the Data Phase of CAN FD frames */ +#define CAN_CTRL2_WRMFRZ (1 << 28) /* Bit 28: Enable unrestricted write access to FlexCAN memory in Freeze mode */ + /* Bits 29-31: Reserved */ + +/* Error and Status 2 Register */ + + /* Bits 0-11: Reserved */ +#define CAN_ESR2_RX_PIN_ST (1 << 12) /* Bit 12: RX Pin Status */ +#define CAN_ESR2_IMB (1 << 13) /* Bit 13: Inactive Mailbox */ +#define CAN_ESR2_VPS (1 << 14) /* Bit 14: Valid Priority Status */ + /* Bit 15: Reserved */ +#define CAN_ESR2_LPTM_SHIFT (16) /* Bits 16-22: Lowest Priority Tx Mailbox */ +#define CAN_ESR2_LPTM_MASK (0x7f << CAN_ESR2_LPTM_SHIFT) + /* Bits 23-31: Reserved */ + +/* CRC Register */ + +#define CAN_CRCR_TXCRC_SHIFT (0) /* Bits 0-14: CRC Transmitted */ +#define CAN_CRCR_TXCRC_MASK (0x7fff << CAN_CRCR_TXCRC_SHIFT) + /* Bit 15: Reserved */ +#define CAN_CRCR_MBCRC_SHIFT (16) /* Bits 16-22: CRC Mailbox */ +#define CAN_CRCR_MBCRC_MASK (0x7f << CAN_CRCR_MBCRC_SHIFT) + /* Bits 23-31: Reserved */ + +/* Rx FIFO Global Mask Register (32 Rx FIFO Global Mask Bits) */ + +#define CAN_RXFGMASK(n) (1 << (n)) /* Bit n: Rx FIFO n Global Mask Bit */ + +/* Rx FIFO Information Register */ + + /* Bits 9-31: Reserved */ +#define CAN_RXFIR_IDHIT_SHIFT (0) /* Bits 0-8: Identifier Acceptance Filter Hit Indicator */ +#define CAN_RXFIR_IDHIT_MASK (0x1ff << CAN_RXFIR_IDHIT_SHIFT) + +/* Rx Individual Mask Registers */ + +#define CAN_RXIMR(n) (1 << (n)) /* Bit n: Individual Mask Bits */ + +/* CAN Bit Timing register */ + +#define CAN_CBT_EPSEG2_SHIFT (0) /* Bits 0-4: Extended Phase Segment 2 */ +#define CAN_CBT_EPSEG2_MASK (0x1f << CAN_CBT_EPSEG2_SHIFT) +#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK) +#define CAN_CBT_EPSEG1_SHIFT (5) /* Bits 5-9: Extended Phase Segment 1 */ +#define CAN_CBT_EPSEG1_MASK (0x1f << CAN_CBT_EPSEG1_SHIFT) +#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK) +#define CAN_CBT_EPROPSEG_SHIFT (10) /* Bits 10-15: Extended Propagation Segment */ +#define CAN_CBT_EPROPSEG_MASK (0x1f << CAN_CBT_EPROPSEG_SHIFT) +#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK) +#define CAN_CBT_ERJW_SHIFT (16) /* Bits 16-20: Extended Resync Jump Width */ +#define CAN_CBT_ERJW_MASK (0x1f << CAN_CBT_ERJW_SHIFT) +#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK) +#define CAN_CBT_EPRESDIV_SHIFT (21) /* Bits 21-30: Extendet Prescaler Division Factor */ +#define CAN_CBT_EPRESDIV_MASK (0x3ff << CAN_CBT_EPRESDIV_SHIFT) +#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK) +#define CAN_CBT_BTF (1 << 31) /* Bit 31: Bit Timing Format Enable */ + +/* Interrupt Masks 3 Register */ + +#define CAN_IMASK3(n) (1 << (n)) /* Bit n: Buffer MBn Mask (95TO64) */ + +/* Interrupt Flags 3 Register */ + +#define CAN_IFLAG3(n) (1 << (n)) /* Bit n: Buffer MBn Interrupt (95TO64) */ + +/* TODO: add bit definitions for FLTCONF_IO to ETDC registers when needed */ + +/* CAN FD Control register */ + +#define CAN_FDCTRL_TDCVAL_SHIFT (0) /* Bits 0-5: Transceiver Delay Compensation Value */ +#define CAN_FDCTRL_TDCVAL_MASK (0x3f << CAN_FDCTRL_TDCVAL_SHIFT) + /* Bits 6-7: Reserved */ +#define CAN_FDCTRL_TDCOFF_SHIFT (8) /* Bits 8-12: Transceiver Delay Compensation Offset */ +#define CAN_FDCTRL_TDCOFF_MASK (0x3f << CAN_FDCTRL_TDCOFF_SHIFT) +#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK) + /* Bit 13: Reserved */ +#define CAN_FDCTRL_TDCFAIL (1 << 14) /* Bit 14: Transceiver Delay Compensation Fail */ +#define CAN_FDCTRL_TDCEN (1 << 15) /* Bit 15: Transceiver Delay Compensation Enable */ +#define CAN_FDCTRL_MBDSR0_SHIFT (16) /* Bits 16-17: Message Buffer Data Size for Region 0 */ +#define CAN_FDCTRL_MBDSR0_MASK (0x3 << CAN_FDCTRL_MBDSR0_SHIFT) +#define CAN_FDCTRL_MSBSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK) + /* Bit 18: Reserved */ +#define CAN_FDCTRL_MBDSR1_SHIFT (19) /* Bits 19-20: Message Buffer Data Size for Region 1 */ +#define CAN_FDCTRL_MBDSR1_MASK (0x3 << CAN_FDCTRL_MBDSR1_SHIFT) +#define CAN_FDCTRL_MSBSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK) + +#define CAN_FDCTRL_MBDSR2_SHIFT (22) /* Bits 22-23: Message Buffer Data Size for Region 2 */ +#define CAN_FDCTRL_MBDSR2_MASK (0x3 << CAN_FDCTRL_MBDSR2_SHIFT) +#define CAN_FDCTRL_MSBSR2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR2_SHIFT)) & CAN_FDCTRL_MBDSR2_MASK) + /* Bits 24-30: Reserved */ +#define CAN_FDCTRL_FDRATE (1 << 31) /* Bit 31: Bit Rate Switch Enable */ + +/* CAN FD Bit Timing register */ + +#define CAN_FDCBT_FPSEG2_SHIFT (0) /* Bits 0-2: Fast Phase Segment 2 */ +#define CAN_FDCBT_FPSEG2_MASK (0x7 << CAN_FDCBT_FPSEG2_SHIFT) +#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK) + /* Bits 3-4: Reserved */ +#define CAN_FDCBT_FPSEG1_SHIFT (5) /* Bits 5-7: Fast Phase Segment 1 */ +#define CAN_FDCBT_FPSEG1_MASK (0x7 << CAN_FDCBT_FPSEG1_SHIFT) +#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK) + /* Bits 8-9: Reserved */ +#define CAN_FDCBT_FPROPSEG_SHIFT (10) /* Bits 10-14: Fast Propagation Segment */ +#define CAN_FDCBT_FPROPSEG_MASK (0x1f << CAN_FDCBT_FPROPSEG_SHIFT) +#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK) + /* Bit 15: Reserved */ +#define CAN_FDCBT_FRJW_SHIFT (16) /* Bits 16-18: Fast Propagation Segment */ +#define CAN_FDCBT_FRJW_MASK (0x7 << CAN_FDCBT_FRJW_SHIFT) +#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK) + /* Bit 19: Reserved */ +#define CAN_FDCBT_FPRESDIV_SHIFT (20) /* Bits 20-29: Fast Propagation Segment */ +#define CAN_FDCBT_FPRESDIV_MASK (0x3ff << CAN_FDCBT_FPRESDIV_SHIFT) +#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK) + /* Bits 30-31: Reserved */ + +/* CAN FD CRC register */ + +#define CAN_FDCRC_FD_TXCRC_SHIFT (0) /* Bits 0-20: Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_TXCRC_MASK (0x1fffff << CAN_FDCRC_FD_TXCRC_SHIFT) +#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK) + /* Bits 21-23: Reserved */ +#define CAN_FDCRC_FD_MBCRC_SHIFT (24) /* Bits 24-30: Extended Transmitted CRC value */ +#define CAN_FDCRC_FD_MBCRC_MASK (0x7f << CAN_FDCRC_FD_MBCRC_SHIFT) +#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK) + /* Bit 31: Reserved */ + +/* CAN MB RX codes */ + +#define CAN_RXMB_INACTIVE 0x0 /* MB is inactive */ +#define CAN_RXMB_FULL 0x2 /* MB is full */ +#define CAN_RXMB_EMPTY 0x4 /* MB is empty */ +#define CAN_RXMB_OVERRUN 0x6 /* overrun */ +#define CAN_RXMB_BUSY_BIT 0x1 /* BUSY, orred with any of the above */ + +/* CAN MB TX codes */ + +#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */ +#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */ +#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */ + /* MB is a TX Remote Request Frame (when MB RTR = 1). */ +#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */ + /* an incoming Remote Request Frame. */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_FLEXCAN_H */ diff --git a/arch/arm64/src/imx9/imx9_flexcan.c b/arch/arm64/src/imx9/imx9_flexcan.c new file mode 100644 index 0000000000000..9589b00494173 --- /dev/null +++ b/arch/arm64/src/imx9/imx9_flexcan.c @@ -0,0 +1,2024 @@ +/**************************************************************************** + * arch/arm64/src/imx9/imx9_flexcan.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +//#include +#include +#include +#include + +#include "arm64_internal.h" +#include "imx9_flexcan.h" +#include "imx9_ccm.h" +#include "imx9_iomuxc.h" +#include "hardware/imx9_ccm.h" +#include "hardware/imx9_pinmux.h" + +#include + +#include + +#ifdef CONFIG_IMX9_FLEXCAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* If processing is not done at the interrupt level, then work queue support + * is required. + */ + +#define CANWORK LPWORK +#define CANRCVWORK HPWORK + +/* CONFIG_IMX9_FLEXCAN_NETHIFS determines the number of physical + * interfaces that will be supported. + */ + +#define MASKSTDID 0x000007ff +#define MASKEXTID 0x1fffffff +#define FLAGEFF (1 << 31) /* Extended frame format */ +#define FLAGRTR (1 << 30) /* Remote transmission request */ + +#define RXMBCOUNT CONFIG_IMX9_FLEXCAN_RXMB +#define TXMBCOUNT (CONFIG_IMX9_FLEXCAN_TXMB + 1) +#define TOTALMBCOUNT RXMBCOUNT + TXMBCOUNT + +#define IFLAG1_RX ((1 << RXMBCOUNT)-1) +#define IFLAG1_TX (((1 << TXMBCOUNT)-2) << RXMBCOUNT) + +#define CAN_FIFO_NE (1 << 5) +#define CAN_FIFO_OV (1 << 6) +#define CAN_FIFO_WARN (1 << 7) +#define CAN_EFF_FLAG 0x80000000 /* EFF/SFF is set in the MSB */ + +#define POOL_SIZE 1 + +#define MSG_DATA sizeof(struct timeval) + +/* CAN bit timing values */ +#define CLK_FREQ 80000000 +#define PRESDIV_MAX 256 + +#define SEG_MAX 8 +#define SEG_MIN 1 +#define TSEG_MIN 2 +#define TSEG1_MAX 17 +#define TSEG2_MAX 9 +#define NUMTQ_MAX 26 + +#define SEG_FD_MAX 32 +#define SEG_FD_MIN 1 +#define TSEG_FD_MIN 2 +#define TSEG1_FD_MAX 39 +#define TSEG2_FD_MAX 9 +#define NUMTQ_FD_MAX 49 + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + +# if !defined(CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +# endif + +#define TX_TIMEOUT_WQ +#endif + +#if (CONFIG_IMX9_FLEXCAN_RXMB + CONFIG_IMX9_FLEXCAN_TXMB) > 21 +# error Only 21 MB are allowed to be used +#endif + +/* Interrupt flags for RX fifo */ +#define IFLAG1_RXFIFO (CAN_FIFO_NE | CAN_FIFO_WARN | CAN_FIFO_OV) + +static int peak_tx_mailbox_index_ = 0; + +static uint8_t mb_address[] = + { + 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, + 0x1e, 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, + 0x10, 0x19, 0x22, 0x2b, 0x34, 0x3d, 0x46, + 0x50, 0x59, 0x62, 0x6b, 0x74, 0x7d, 0x86 + }; + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +union cs_e +{ + volatile uint32_t cs; + struct + { + volatile uint32_t time_stamp : 16; + volatile uint32_t dlc : 4; + volatile uint32_t rtr : 1; + volatile uint32_t ide : 1; + volatile uint32_t srr : 1; + volatile uint32_t res : 1; + volatile uint32_t code : 4; + volatile uint32_t res2 : 1; + volatile uint32_t esi : 1; + volatile uint32_t brs : 1; + volatile uint32_t edl : 1; + }; +}; + +union id_e +{ + volatile uint32_t w; + struct + { + volatile uint32_t ext : 29; + volatile uint32_t resex : 3; + }; + struct + { + volatile uint32_t res : 18; + volatile uint32_t std : 11; + volatile uint32_t resstd : 3; + }; +}; + +union data_e +{ + volatile uint32_t w00; + struct + { + volatile uint32_t b03 : 8; + volatile uint32_t b02 : 8; + volatile uint32_t b01 : 8; + volatile uint32_t b00 : 8; + }; +}; + +struct mb_s +{ + union cs_e cs; + union id_e id; + union data_e data[]; +}; + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE +#define TX_ABORT -1 +#define TX_FREE 0 +#define TX_BUSY 1 + +struct txmbstats +{ + struct timeval deadline; + uint32_t pending; /* -1 = abort, 0 = free, 1 = busy */ +}; +#endif + +/* FlexCAN Device hardware configuration */ + +struct flexcan_timeseg +{ + uint32_t bitrate; + int32_t samplep; + uint8_t propseg; + uint8_t pseg1; + uint8_t pseg2; + uint8_t presdiv; +}; + +/* The imx9_driver_s encapsulates all state information for a single + * hardware interface + */ + +struct imx9_driver_s +{ + /* This holds the information visible to the NuttX network */ + struct net_driver_s dev; /* Interface understood by the network */ + + const uintptr_t base; /* FLEXCAN base address */ + const int irq; /* irq number */ + const bool canfd_capable; + const int mb_address_offset; + bool bifup; /* true:ifup false:ifdown */ +#ifdef TX_TIMEOUT_WQ + struct wdog_s txtimeout[TXMBCOUNT]; /* TX timeout timer */ +#endif + struct work_s rcvwork; /* For deferring interrupt work to the wq */ + struct work_s irqwork; /* For deferring interrupt work to the wq */ + struct work_s pollwork; /* For deferring poll work to the work wq */ + struct canfd_frame *txdesc_fd; /* A pointer to the list of TX descriptor for FD frames */ + struct canfd_frame *rxdesc_fd; /* A pointer to the list of RX descriptors for FD frames */ + struct can_frame *txdesc; /* A pointer to the list of TX descriptor */ + struct can_frame *rxdesc; /* A pointer to the list of RX descriptors */ + struct flexcan_timeseg arbi_timing; /* Timing for arbitration phase */ + struct flexcan_timeseg data_timing; /* Timing for data phase */ + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + struct txmbstats txmb[TXMBCOUNT]; +#endif +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_IMX9_FLEXCAN1 +static struct imx9_driver_s g_flexcan1 = + { + .base = IMX9_CAN1_BASE, + .irq = IMX9_IRQ_CAN1, +# if defined(CONFIG_NET_CAN_CANFD) + .canfd_capable = true, + .mb_address_offset = 14, +# else + .canfd_capable = false, + .mb_address_offset = 0, +# endif + + /* Default bitrate configuration */ + +# if defined(CONFIG_NET_CAN_CANFD) + .arbi_timing = + { + .bitrate = CONFIG_IMX9_FLEXCAN1_ARBI_BITRATE, + .samplep = CONFIG_IMX9_FLEXCAN1_ARBI_SAMPLEP, + }, + .data_timing = + { + .bitrate = CONFIG_IMX9_FLEXCAN1_DATA_BITRATE, + .samplep = CONFIG_IMX9_FLEXCAN1_DATA_SAMPLEP, + }, +# else + .arbi_timing = + { + .bitrate = CONFIG_IMX9_FLEXCAN1_BITRATE, + .samplep = CONFIG_IMX9_FLEXCAN1_SAMPLEP, + } +# endif + }; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 +static struct imx9_driver_s g_flexcan2 = + { + .base = IMX9_CAN2_BASE, + .irq = IMX9_IRQ_CAN2, +# if defined(CONFIG_NET_CAN_CANFD) + .canfd_capable = true, + .mb_address_offset = 14, +# else + .canfd_capable = false, + .mb_address_offset = 0, +# endif + + /* Default bitrate configuration */ + +# if defined(CONFIG_NET_CAN_CANFD) + .arbi_timing = + { + .bitrate = CONFIG_IMX9_FLEXCAN2_ARBI_BITRATE, + .samplep = CONFIG_IMX9_FLEXCAN2_ARBI_SAMPLEP, + }, + .data_timing = + { + .bitrate = CONFIG_IMX9_FLEXCAN2_DATA_BITRATE, + .samplep = CONFIG_IMX9_FLEXCAN2_DATA_SAMPLEP, + }, +# else + .arbi_timing = + { + .bitrate = CONFIG_IMX9_FLEXCAN2_BITRATE, + .samplep = CONFIG_IMX9_FLEXCAN2_SAMPLEP, + } +# endif + }; +#endif + +#ifdef CONFIG_NET_CAN_CANFD +static uint8_t g_tx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE]; +static uint8_t g_rx_pool[(sizeof(struct canfd_frame)+MSG_DATA)*POOL_SIZE]; +#else +static uint8_t g_tx_pool[sizeof(struct can_frame)*POOL_SIZE]; +static uint8_t g_rx_pool[sizeof(struct can_frame)*POOL_SIZE]; +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: arm64_lsb + * + * Description: + * Calculate position of lsb that's equal to 1 + * + * Input Parameters: + * value - The value to perform the operation on + * + * Returned Value: + * location of lsb which is equal to 1, returns 32 when value is 0 + * + ****************************************************************************/ + +static inline uint32_t arm64_lsb(unsigned int value) +{ + uint32_t ret; + volatile uint32_t rvalue = value; + __asm__ __volatile__ ("rbit %1,%0" : "=r" (rvalue) : "r" (rvalue)); + __asm__ __volatile__ ("clz %0, %1" : "=r"(ret) : "r"(rvalue)); + return ret; +} + +/**************************************************************************** + * Name: imx9_bitratetotimeseg + * + * Description: + * Convert bitrate to timeseg + * + * Input Parameters: + * timeseg - structure to store bit timing + * sp_tolerance - allowed difference in sample point from calculated + * bit timings (recommended value: 1) + * can_fd - if set to calculate CAN FD bit timings, otherwise calculate + * classical can timings + * + * Returned Value: + * return 1 on success, return 0 on failure + * + ****************************************************************************/ + +uint32_t imx9_bitratetotimeseg(struct flexcan_timeseg *timeseg, + int32_t sp_tolerance, + uint32_t can_fd) +{ + int32_t tmppresdiv; + int32_t numtq; + int32_t tmpsample; + int32_t tseg1; + int32_t tseg2; + int32_t tmppseg1; + int32_t tmppseg2; + int32_t tmppropseg; + + const int32_t TSEG1MAX = (can_fd ? TSEG1_FD_MAX : TSEG1_MAX); + const int32_t TSEG2MAX = (can_fd ? TSEG2_FD_MAX : TSEG2_MAX); + const int32_t SEGMAX = (can_fd ? SEG_FD_MAX : SEG_MAX); + const int32_t NUMTQMAX = (can_fd ? NUMTQ_FD_MAX : NUMTQ_MAX); + + for (tmppresdiv = 0; tmppresdiv < PRESDIV_MAX; tmppresdiv++) + { + numtq = (CLK_FREQ / ((tmppresdiv + 1) * timeseg->bitrate)); + + if (numtq == 0) + { + continue; + } + + /* The number of time quanta in 1 bit time must be + * lower than the one supported + */ + + if ((CLK_FREQ / ((tmppresdiv + 1) * numtq) == timeseg->bitrate) + && (numtq >= 8) && (numtq < NUMTQMAX)) + { + /* Compute time segments based on the value of the sampling point */ + + tseg1 = (numtq * timeseg->samplep / 100) - 1; + tseg2 = numtq - 1 - tseg1; + + /* Adjust time segment 1 and time segment 2 */ + + while (tseg1 >= TSEG1MAX || tseg2 < TSEG_MIN) + { + tseg2++; + tseg1--; + } + + tmppseg2 = tseg2 - 1; + + /* Start from pseg1 = pseg2 and adjust until propseg is valid */ + + tmppseg1 = tmppseg2; + tmppropseg = tseg1 - tmppseg1 - 2; + + while (tmppropseg <= 0) + { + tmppropseg++; + tmppseg1--; + } + + while (tmppropseg >= SEGMAX) + { + tmppropseg--; + tmppseg1++; + } + + if (((tseg1 >= TSEG1MAX) || (tseg2 >= TSEG2MAX) || + (tseg2 < TSEG_MIN) || (tseg1 < TSEG_MIN)) || + ((tmppropseg >= SEGMAX) || (tmppseg1 >= SEGMAX) || + (tmppseg2 < SEG_MIN) || (tmppseg2 >= SEGMAX))) + { + continue; + } + + tmpsample = ((tseg1 + 1) * 100) / numtq; + + if ((tmpsample - timeseg->samplep) <= sp_tolerance && + (timeseg->samplep - tmpsample) <= sp_tolerance) + { + if (can_fd == 1) + { + timeseg->propseg = tmppropseg + 1; + } + else + { + timeseg->propseg = tmppropseg; + } + timeseg->pseg1 = tmppseg1; + timeseg->pseg2 = tmppseg2; + timeseg->presdiv = tmppresdiv; + timeseg->samplep = tmpsample; + return 1; + } + } + } + + return 0; +} + +/* Common TX logic */ + +static bool imx9_txringfull(struct imx9_driver_s *priv); +static int imx9_transmit(struct imx9_driver_s *priv); +static int imx9_txpoll(struct net_driver_s *dev); + +/* Helper functions */ + +static void imx9_setenable(uint32_t base, uint32_t enable); +static void imx9_setfreeze(uint32_t base, uint32_t freeze); +static uint32_t imx9_waitmcr_change(uint32_t base, + uint32_t mask, + uint32_t target_state); +static struct mb_s *flexcan_get_mb(struct imx9_driver_s *priv, + uint32_t mbi); + +/* Interrupt handling */ + +static void imx9_receive(struct imx9_driver_s *priv, + uint32_t flags); +static void imx9_txdone_work(void *arg); +static void imx9_txdone(struct imx9_driver_s *priv); + +static int imx9_flexcan_interrupt(int irq, void *context, + void *arg); +static void imx9_flexcan_interrupt_work(void *arg); + +/* Watchdog timer expirations */ +#ifdef TX_TIMEOUT_WQ +static void imx9_txtimeout_work(void *arg); +static void imx9_txtimeout_expiry(wdparm_t arg); +#endif + +/* NuttX callback functions */ + +static int imx9_ifup(struct net_driver_s *dev); +static int imx9_ifdown(struct net_driver_s *dev); + +static void imx9_txavail_work(void *arg); +static int imx9_txavail(struct net_driver_s *dev); + +#ifdef CONFIG_NETDEV_IOCTL +static int imx9_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Initialization */ + +static int imx9_initialize(struct imx9_driver_s *priv); +static void imx9_reset(struct imx9_driver_s *priv); + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imx9_txringfull + * + * Description: + * Check if all of the TX descriptors are in use. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * true is the TX ring is full; false if there are free slots at the + * head index. + * + ****************************************************************************/ + +static bool imx9_txringfull(struct imx9_driver_s *priv) +{ + uint32_t mbi = RXMBCOUNT + 1; + struct mb_s *mb; + + while (mbi < TOTALMBCOUNT) + { + mb = flexcan_get_mb(priv, mbi); + if (mb->cs.code != CAN_TXMB_DATAORREMOTE) + { + return 0; + } + + mbi++; + } + + return 1; +} + +/**************************************************************************** + * Function: imx9_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int imx9_transmit(struct imx9_driver_s *priv) +{ + /* Attempt to write frame */ + + uint32_t mbi = 0; + uint32_t mb_bit; + uint32_t regval; +#ifdef CONFIG_NET_CAN_CANFD + uint32_t *frame_data_word; + uint32_t i; +#endif +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + int32_t timeout; + uint32_t txmb = 0; +#endif + + mbi = RXMBCOUNT + 1; + mb_bit = 1 << mbi; + + while (mbi < TOTALMBCOUNT) + { + /* Check whether message buffer is not currently transmitting */ + + struct mb_s *mb = flexcan_get_mb(priv, mbi); + if (mb->cs.code != CAN_TXMB_DATAORREMOTE) + { + putreg32(mb_bit, priv->base + IMX9_CAN_IFLAG1_OFFSET); + break; + } + + mb_bit <<= 1; + mbi++; +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + txmb++; +#endif + } + + if (mbi == TOTALMBCOUNT) + { + nwarn("No TX MB available mbi %" PRIi32 "\n", mbi); + NETDEV_TXERRORS(&priv->dev); + return 0; /* No transmission for you! */ + } + +#ifdef CONFIG_NET_CAN_RAW_TX_DEADLINE + struct timespec ts; + clock_systime_timespec(&ts); + + if (priv->dev.d_sndlen > priv->dev.d_len) + { + struct timeval *tv = + (struct timeval *)(priv->dev.d_buf + priv->dev.d_len); + priv->txmb[txmb].deadline = *tv; + timeout = (tv->tv_sec - ts.tv_sec)*CLK_TCK + + ((tv->tv_usec - ts.tv_nsec / 1000)*CLK_TCK) / 1000000; + if (timeout < 0) + { + return 0; /* No transmission for you! */ + } + } + else + { + /* Default TX deadline defined in NET_CAN_RAW_DEFAULT_TX_DEADLINE */ + + if (CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE > 0) + { + timeout = ((CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000) + *CLK_TCK); + priv->txmb[txmb].deadline.tv_sec = ts.tv_sec + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE / 1000000; + priv->txmb[txmb].deadline.tv_usec = (ts.tv_nsec / 1000) + + CONFIG_NET_CAN_RAW_DEFAULT_TX_DEADLINE % 1000000; + } + else + { + priv->txmb[txmb].deadline.tv_sec = 0; + priv->txmb[txmb].deadline.tv_usec = 0; + timeout = -1; + } + } +#endif + + peak_tx_mailbox_index_ = + (peak_tx_mailbox_index_ > mbi ? peak_tx_mailbox_index_ : mbi); + + union cs_e cs; + cs.code = CAN_TXMB_DATAORREMOTE; + struct mb_s *mb = flexcan_get_mb(priv, mbi); + mb->cs.code = CAN_TXMB_INACTIVE; + + if (priv->dev.d_len == sizeof(struct can_frame)) + { + struct can_frame *frame = (struct can_frame *)priv->dev.d_buf; + + if (frame->can_id & CAN_EFF_FLAG) + { + cs.ide = 1; + mb->id.ext = frame->can_id & MASKEXTID; + } + else + { + mb->id.std = frame->can_id & MASKSTDID; + } + + cs.rtr = frame->can_id & FLAGRTR ? 1 : 0; + cs.dlc = frame->can_dlc; + + mb->data[0].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[0]); + mb->data[1].w00 = __builtin_bswap32(*(uint32_t *)&frame->data[4]); + } +#ifdef CONFIG_NET_CAN_CANFD + else /* CAN FD frame */ + { + struct canfd_frame *frame = (struct canfd_frame *)priv->dev.d_buf; + + cs.edl = 1; /* CAN FD Frame */ + + if (frame->can_id & CAN_EFF_FLAG) + { + cs.ide = 1; + mb->id.ext = frame->can_id & MASKEXTID; + } + else + { + mb->id.std = frame->can_id & MASKSTDID; + } + + cs.rtr = frame->can_id & FLAGRTR ? 1 : 0; + + cs.dlc = g_len_to_can_dlc[frame->len]; + + frame_data_word = (uint32_t *)&frame->data[0]; + + for (i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + mb->data[i].w00 = __builtin_bswap32(frame_data_word[i]); + } + } +#endif + + mb->cs = cs; /* Go. */ + + struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); + buffer->cs.code = CAN_TXMB_DATAORREMOTE; + + regval = getreg32(priv->base + IMX9_CAN_IMASK1_OFFSET); + regval |= mb_bit; + putreg32(regval, priv->base + IMX9_CAN_IMASK1_OFFSET); + + /* Increment statistics */ + + NETDEV_TXPACKETS(&priv->dev); + +#ifdef TX_TIMEOUT_WQ + /* Setup the TX timeout watchdog (perhaps restarting the timer) */ + + if (timeout > 0) + { + wd_start(&priv->txtimeout[txmb], timeout + 1, + imx9_txtimeout_expiry, (wdparm_t)priv); + } +#endif + + return OK; +} + +/**************************************************************************** + * Function: imx9_txpoll + * + * Description: + * The transmitter is available, check if the network has any outgoing + * packets ready to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int imx9_txpoll(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + irqstate_t flags; + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + flags = spin_lock_irqsave(NULL); + + if (priv->dev.d_len > 0) + { + imx9_txdone(priv); + + /* Send the packet */ + + imx9_transmit(priv); + + /* Check if there is room in the device to hold another packet. If + * not, return a non-zero value to terminate the poll. + */ + + if (imx9_txringfull(priv)) + { + spin_unlock_irqrestore(NULL, flags); + return -EBUSY; + } + } + + spin_unlock_irqrestore(NULL, flags); + + /* If zero is returned, the polling will continue until all connections + * have been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: imx9_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void imx9_receive(struct imx9_driver_s *priv, + uint32_t flags) +{ + uint32_t mbi; + uint32_t mbj; + struct mb_s *rf; +#ifdef CONFIG_NET_CAN_CANFD + uint32_t *frame_data_word; + uint32_t i; +#endif + uint32_t f; + + while ((f = flags) != 0) + { + mbj = mbi = arm64_lsb(f); + rf = flexcan_get_mb(priv, mbi); + uint32_t t = rf->cs.time_stamp; + while ((f &= ~(1 << mbj)) != 0) + { + mbj = arm64_lsb(f); + struct mb_s *rf_next = flexcan_get_mb(priv, mbj); + uint16_t t_next = rf_next->cs.time_stamp; + if ((int16_t)(t - t_next) > 0) + { + t = t_next; + mbi = mbj; + } + } + + rf = flexcan_get_mb(priv, mbi); + + /* Read the frame contents */ + +#ifdef CONFIG_NET_CAN_CANFD + if (rf->cs.edl) + { + /* CAN FD frame */ + + struct canfd_frame *frame = (struct canfd_frame *)priv->rxdesc_fd; + + if (rf->cs.ide) + { + frame->can_id = MASKEXTID & rf->id.ext; + frame->can_id |= FLAGEFF; + } + else + { + frame->can_id = MASKSTDID & rf->id.std; + } + + if (rf->cs.rtr) + { + frame->can_id |= FLAGRTR; + } + + frame->len = g_can_dlc_to_len[rf->cs.dlc]; + + frame_data_word = (uint32_t *)&frame->data[0]; + + for (i = 0; i < (frame->len + 4 - 1) / 4; i++) + { + frame_data_word[i] = __builtin_bswap32(rf->data[i].w00); + } + + /* Clear MB interrupt flag */ + + putreg32(1 << mbi, + priv->base + IMX9_CAN_IFLAG1_OFFSET); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct canfd_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + else +#endif + { + /* CAN 2.0 Frame */ + + struct can_frame *frame = (struct can_frame *)priv->rxdesc; + + if (rf->cs.ide) + { + frame->can_id = MASKEXTID & rf->id.ext; + frame->can_id |= FLAGEFF; + } + else + { + frame->can_id = MASKSTDID & rf->id.std; + } + + if (rf->cs.rtr) + { + frame->can_id |= FLAGRTR; + } + + frame->can_dlc = rf->cs.dlc; + + *(uint32_t *)&frame->data[0] = __builtin_bswap32(rf->data[0].w00); + *(uint32_t *)&frame->data[4] = __builtin_bswap32(rf->data[1].w00); + + /* Clear MB interrupt flag */ + + putreg32(1 << mbi, + priv->base + IMX9_CAN_IFLAG1_OFFSET); + + /* Copy the buffer pointer to priv->dev.. Set amount of data + * in priv->dev.d_len + */ + + priv->dev.d_len = sizeof(struct can_frame); + priv->dev.d_buf = (uint8_t *)frame; + } + + /* Send to socket interface */ + + NETDEV_RXPACKETS(&priv->dev); + + can_input(&priv->dev); + + /* Point the packet buffer back to the next Tx buffer that will be + * used during the next write. If the write queue is full, then + * this will point at an active buffer, which must not be written + * to. This is OK because devif_poll won't be called unless the + * queue is not full. + */ + + if (priv->canfd_capable) + { + priv->dev.d_buf = (uint8_t *)priv->txdesc_fd; + } + else + { + priv->dev.d_buf = (uint8_t *)priv->txdesc; + } + + flags &= ~(1 << mbi); + + /* Reread interrupt flags and process them in this loop */ + + if (flags == 0) + { + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + } + } +} + +/**************************************************************************** + * Function: imx9_txdone + * + * Description: + * Check transmit interrupt flags and clear them + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void imx9_txdone(struct imx9_driver_s *priv) +{ + uint32_t flags; + uint32_t mbi; + uint32_t mb_bit; +#ifdef TX_TIMEOUT_WQ + uint32_t txmb; +#endif + + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_TX; + + /* Process TX completions */ + + mbi = RXMBCOUNT + 1; + mb_bit = 1 << mbi; +#ifdef TX_TIMEOUT_WQ + txmb = 0; +#endif + + while (mbi < TOTALMBCOUNT) + { + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= ~mb_bit; + NETDEV_TXDONE(&priv->dev); +#ifdef TX_TIMEOUT_WQ + /* We are here because a transmission completed, so the + * corresponding watchdog can be canceled + * mailbox be set to inactive + */ + + wd_cancel(&priv->txtimeout[txmb]); + struct mb_s *mb = flexcan_get_mb(priv, mbi); + mb->cs.code = CAN_TXMB_INACTIVE; +#endif + } + + mb_bit <<= 1; + mbi++; +#ifdef TX_TIMEOUT_WQ + txmb++; +#endif + } +} + +/**************************************************************************** + * Function: imx9_txdone_work + * + * Description: + * An interrupt was received indicating that the last TX packet(s) is done + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * We are not in an interrupt context so that we can lock the network. + * + ****************************************************************************/ + +static void imx9_txdone_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + imx9_txdone(priv); + + /* There should be space for a new TX in any event. Poll the network for + * new XMIT data + */ + + net_lock(); + devif_poll(&priv->dev, imx9_txpoll); + net_unlock(); +} + +/**************************************************************************** + * Function: imx9_flexcan_interrupt_work + * + * Description: + * Three interrupt sources will vector this this function: + * 1. CAN MB transmit interrupt handler + * 2. CAN MB receive interrupt handler + * 3. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_flexcan_interrupt_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + uint32_t flags; + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + + net_lock(); + imx9_receive(priv, flags); + net_unlock(); + + /* Mask MB again */ + + modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, 0, IFLAG1_RX); +} + +/**************************************************************************** + * Function: imx9_flexcan_interrupt + * + * Description: + * Three interrupt sources will vector this this function: + * 1. CAN MB transmit interrupt handler + * 2. CAN MB receive interrupt handler + * 3. + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_flexcan_interrupt(int irq, void *context, + void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + if (irq == priv->irq) + { + uint32_t flags; + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_RX; + + if (flags) + { + modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, IFLAG1_RX, 0); + work_queue(CANRCVWORK, &priv->rcvwork, + imx9_flexcan_interrupt_work, priv, 0); + } + + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + flags &= IFLAG1_TX; + + if (flags) + { + /* Disable further TX MB CAN interrupts. here can be no race + * condition here. + */ + + modifyreg32(priv->base + IMX9_CAN_IMASK1_OFFSET, IFLAG1_TX, 0); + work_queue(CANWORK, &priv->irqwork, imx9_txdone_work, priv, 0); + } + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ +#ifdef TX_TIMEOUT_WQ + +static void imx9_txtimeout_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + uint32_t flags; + uint32_t mbi; + uint32_t mb_bit; + + struct timespec ts; + struct timeval *now = (struct timeval *)&ts; + clock_systime_timespec(&ts); + now->tv_usec = ts.tv_nsec / 1000; /* timespec to timeval conversion */ + + /* The watchdog timed out, yet we still check mailboxes in case the + * transmit function transmitted a new frame + */ + + flags = getreg32(priv->base + IMX9_CAN_IFLAG1_OFFSET); + + for (mbi = 0; mbi < TXMBCOUNT; mbi++) + { + if (priv->txmb[mbi].deadline.tv_sec != 0 + && (now->tv_sec > priv->txmb[mbi].deadline.tv_sec + || now->tv_usec > priv->txmb[mbi].deadline.tv_usec)) + { + NETDEV_TXTIMEOUTS(&priv->dev); + + mb_bit = 1 << (RXMBCOUNT + mbi); + + if (flags & mb_bit) + { + putreg32(mb_bit, priv->base + IMX9_CAN_IFLAG1_OFFSET); + } + + struct mb_s *mb = flexcan_get_mb(priv, mbi + RXMBCOUNT); + mb->cs.code = CAN_TXMB_ABORT; + priv->txmb[mbi].pending = TX_ABORT; + } + } +} + +/**************************************************************************** + * Function: imx9_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * arg - The argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +static void imx9_txtimeout_expiry(wdparm_t arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Schedule to perform the TX timeout processing on the worker thread + */ + + work_queue(CANWORK, &priv->irqwork, imx9_txtimeout_work, priv, 0); +} + +#endif + +static void imx9_setenable(uint32_t base, uint32_t enable) +{ + uint32_t regval; + + if (enable) + { + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_MDIS); + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } + else + { + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_MDIS; + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } + + imx9_waitmcr_change(base, CAN_MCR_LPMACK, 1); +} + +static void imx9_setfreeze(uint32_t base, uint32_t freeze) +{ + uint32_t regval; + if (freeze) + { + /* Enter freeze mode */ + + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval |= (CAN_MCR_HALT | CAN_MCR_FRZ); + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } + else + { + /* Exit freeze mode */ + + regval = getreg32(base + IMX9_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_HALT | CAN_MCR_FRZ); + putreg32(regval, base + IMX9_CAN_MCR_OFFSET); + } +} + +static uint32_t imx9_waitmcr_change(uint32_t base, uint32_t mask, + uint32_t target_state) +{ + const uint32_t timeout = 1000; + uint32_t wait_ack; + + for (wait_ack = 0; wait_ack < timeout; wait_ack++) + { + const bool state = (getreg32(base + IMX9_CAN_MCR_OFFSET) & mask) + != 0; + if (state == target_state) + { + return true; + } + + up_udelay(10); + } + + return false; +} + +static uint32_t imx9_waitfreezeack_change(uint32_t base, + uint32_t target_state) +{ + return imx9_waitmcr_change(base, CAN_MCR_FRZACK, target_state); +} + +static struct mb_s *flexcan_get_mb(struct imx9_driver_s *priv, + uint32_t mbi) +{ + return (struct mb_s *)(priv->base + + (mb_address[priv->mb_address_offset + mbi] << 3)); +} + +/**************************************************************************** + * Function: imx9_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifup(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + + if (!imx9_initialize(priv)) + { + nerr("initialize failed"); + return -1; + } + + priv->bifup = true; + priv->txdesc = (struct can_frame *)&g_tx_pool; + priv->rxdesc = (struct can_frame *)&g_rx_pool; + if (priv->canfd_capable) + { + priv->txdesc_fd = (struct canfd_frame *)&g_tx_pool; + priv->rxdesc_fd = (struct canfd_frame *)&g_rx_pool; + priv->dev.d_buf = (uint8_t *)priv->txdesc_fd; + } + else + { + priv->dev.d_buf = (uint8_t *)priv->txdesc; + } + + /* Set interrupts */ + + up_enable_irq(priv->irq); + + return OK; +} + +/**************************************************************************** + * Function: imx9_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_ifdown(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + + imx9_reset(priv); + + priv->bifup = false; + return OK; +} + +/**************************************************************************** + * Function: imx9_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void imx9_txavail_work(void *arg) +{ + struct imx9_driver_s *priv = (struct imx9_driver_s *)arg; + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->bifup) + { + /* Check if there is room in the hardware to hold another outgoing + * packet. + */ + + if (!imx9_txringfull(priv)) + { + /* No, there is space for another transfer. Poll the network for + * new XMIT data. + */ + + devif_poll(&priv->dev, imx9_txpoll); + } + } + + net_unlock(); +} + +/**************************************************************************** + * Function: imx9_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int imx9_txavail(struct net_driver_s *dev) +{ + struct imx9_driver_s *priv = + (struct imx9_driver_s *)dev->d_private; + + /* Is our single work structure available? It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + imx9_txavail_work(priv); + } + + return OK; +} + +/**************************************************************************** + * Function: imx9_ioctl + * + * Description: + * PHY ioctl command handler + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * cmd - ioctl command + * arg - Argument accompanying the command + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int imx9_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg) +{ + int ret; + + switch (cmd) + { +#ifdef CONFIG_NETDEV_CAN_BITRATE_IOCTL + case SIOCGCANBITRATE: /* Get bitrate from a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + req->arbi_bitrate = priv->arbi_timing.bitrate / 1000; /* kbit/s */ + req->arbi_samplep = priv->arbi_timing.samplep; + if (priv->canfd_capable) + { + req->data_bitrate = priv->data_timing.bitrate / 1000; /* kbit/s */ + req->data_samplep = priv->data_timing.samplep; + } + else + { + req->data_bitrate = 0; + req->data_samplep = 0; + } + + ret = OK; + } + break; + + case SIOCSCANBITRATE: /* Set bitrate of a CAN controller */ + { + struct can_ioctl_data_s *req = + (struct can_ioctl_data_s *)((uintptr_t)arg); + + struct flexcan_timeseg arbi_timing; + arbi_timing.bitrate = req->arbi_bitrate * 1000; + arbi_timing.samplep = req->arbi_samplep; + + if (imx9_bitratetotimeseg(&arbi_timing, 10, 0)) + { + ret = OK; + } + else + { + ret = -EINVAL; + } + + if (priv->canfd_capable) + { + data_timing.bitrate = req->data_bitrate * 1000; + data_timing.samplep = req->data_samplep; + + if (ret == OK && imx9_bitratetotimeseg(&data_timing, 10, 1)) + { + ret = OK; + } + else + { + ret = -EINVAL; + } + } + + if (ret == OK) + { + /* Reset CAN controller and start with new timings */ + + priv->arbi_timing = arbi_timing; + if (priv->canfd_capable) + { + priv->data_timing = data_timing; + } + + imx9_ifup(dev); + } + } + break; +#endif + default: + ret = -ENOTTY; + break; + } + + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +#ifdef CONFIG_IMX9_FLEXCAN_ECC + +/**************************************************************************** + * Function: imx9_init_eccram + * + * Description: + * Initialize FLEXCAN ECC RAM + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_init_eccram(struct imx9_driver_s *priv) +{ + uint32_t i; + uint32_t regval; + irqstate_t flags; + + flags = enter_critical_section(); + + regval = getreg32(priv->base + IMX9_CAN_CTRL2_OFFSET); + + /* Set WRMFRZ bit in CTRL2 Register to grant write access to memory */ + + regval |= CAN_CTRL2_WRMFRZ; + + putreg32(regval, priv->base + IMX9_CAN_CTRL2_OFFSET); + + for (i = IMX9_CAN_MB_OFFSET; i < IMX9_CAN_MB_END; i += 4) + { + putreg32(0, priv->base + i); + } + + for (i = IMX9_CAN_MB2_OFFSET; i < IMX9_CAN_MB2_END; i += 4) + { + putreg32(0, priv->base + i); + } + + regval = getreg32(priv->base + IMX9_CAN_CTRL2_OFFSET); + + /* Clear WRMFRZ bit in CTRL2 Register */ + + regval &= ~CAN_CTRL2_WRMFRZ; + + leave_critical_section(flags); + + return 0; +} + +#endif + +/**************************************************************************** + * Function: imx9_initalize + * + * Description: + * Initialize FLEXCAN device + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static int imx9_initialize(struct imx9_driver_s *priv) +{ + uint32_t regval; + uint32_t i; + + /* initialize CAN device */ + + imx9_setenable(priv->base, 1); + +#ifdef CONFIG_IMX9_FLEXCAN_ECC + imx9_init_eccram(priv); +#endif + + imx9_reset(priv); + + /* Enter freeze mode */ + + imx9_setfreeze(priv->base, 1); + if (!imx9_waitfreezeack_change(priv->base, 1)) + { + nerr("FLEXCAN: freeze fail\n"); + return -1; + } + + if (!priv->canfd_capable) + { + regval = getreg32(priv->base + IMX9_CAN_CTRL1_OFFSET); + regval &= ~(CAN_CTRL1_PRESDIV_MASK | CAN_CTRL1_PROPSEG_MASK | + CAN_CTRL1_PSEG1_MASK | CAN_CTRL1_PSEG2_MASK | + CAN_CTRL1_RJW_MASK); + regval |= CAN_CTRL1_PRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */ + CAN_CTRL1_PROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */ + CAN_CTRL1_PSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_CTRL1_PSEG2(priv->arbi_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_CTRL1_RJW(1); /* Resynchronization jump width */ + putreg32(regval, priv->base + IMX9_CAN_CTRL1_OFFSET); + } + else + { + regval = getreg32(priv->base + IMX9_CAN_CBT_OFFSET); + regval &= ~(CAN_CBT_EPRESDIV_MASK | CAN_CBT_EPROPSEG_MASK | + CAN_CBT_EPSEG1_MASK | CAN_CBT_EPSEG2_MASK | + CAN_CBT_ERJW_MASK); + regval |= CAN_CBT_BTF | /* Enable extended bit timing + * configurations for CAN-FD for setting up + * separately nominal and data phase */ + CAN_CBT_EPRESDIV(priv->arbi_timing.presdiv) | /* Prescaler divisor factor */ + CAN_CBT_EPROPSEG(priv->arbi_timing.propseg) | /* Propagation segment */ + CAN_CBT_EPSEG1(priv->arbi_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_CBT_EPSEG2(priv->arbi_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_CBT_ERJW(1); /* Resynchronization jump width */ + putreg32(regval, priv->base + IMX9_CAN_CBT_OFFSET); + + /* Enable CAN FD feature */ + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_FDEN; + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + regval = getreg32(priv->base + IMX9_CAN_FDCBT_OFFSET); + regval &= ~(CAN_FDCBT_FPRESDIV_MASK | CAN_FDCBT_FPROPSEG_MASK | + CAN_FDCBT_FPSEG1_MASK | CAN_FDCBT_FPSEG2_MASK | + CAN_FDCBT_FRJW_MASK); + regval |= CAN_FDCBT_FPRESDIV(priv->data_timing.presdiv) | /* Prescaler divisor factor of 1 */ + CAN_FDCBT_FPROPSEG(priv->data_timing.propseg) | /* Propagation + * segment (only register that doesn't add 1) */ + CAN_FDCBT_FPSEG1(priv->data_timing.pseg1) | /* Phase buffer segment 1 */ + CAN_FDCBT_FPSEG2(priv->data_timing.pseg2) | /* Phase buffer segment 2 */ + CAN_FDCBT_FRJW(priv->data_timing.pseg2); /* Resynchorinzation jump width same as PSEG2 */ + putreg32(regval, priv->base + IMX9_CAN_FDCBT_OFFSET); + + /* Additional CAN-FD configurations */ + + regval = getreg32(priv->base + IMX9_CAN_FDCTRL_OFFSET); + + regval |= CAN_FDCTRL_FDRATE | /* Enable bit rate switch in data phase of frame */ + CAN_FDCTRL_TDCEN | /* Enable transceiver delay compensation */ + CAN_FDCTRL_TDCOFF(5) | /* Setup 5 cycles for data phase sampling delay */ + CAN_FDCTRL_MSBSR0(3) | /* Setup 64 bytes per MB 0-6 */ + CAN_FDCTRL_MSBSR1(3) | /* Setup 64 bytes per MB 7-13 */ + CAN_FDCTRL_MSBSR2(3); /* Setup 64 bytes per MB 14-20 */ + putreg32(regval, priv->base + IMX9_CAN_FDCTRL_OFFSET); + + regval = getreg32(priv->base + IMX9_CAN_CTRL2_OFFSET); + regval |= CAN_CTRL2_ISOCANFDEN; + putreg32(regval, priv->base + IMX9_CAN_CTRL2_OFFSET); + } + + struct mb_s *buffer = flexcan_get_mb(priv, RXMBCOUNT); + buffer->cs.code = 0xc; + + for (i = RXMBCOUNT + 1; i < TOTALMBCOUNT; i++) + { + struct mb_s *rx = flexcan_get_mb(priv, i); + rx->id.w = 0x0; + } + + putreg32(0x0, priv->base + IMX9_CAN_RXFGMASK_OFFSET); + + for (i = 0; i < TOTALMBCOUNT; i++) + { + putreg32(0, priv->base + IMX9_CAN_RXIMR_OFFSET(i)); + } + + for (i = 0; i < RXMBCOUNT; i++) + { + struct mb_s *rx = flexcan_get_mb(priv, i); + ninfo("Set MB%" PRIi32 " to receive %p\n", i, rx); + rx->cs.code = CAN_RXMB_EMPTY; + } + + putreg32(IFLAG1_RX, priv->base + IMX9_CAN_IFLAG1_OFFSET); + putreg32(IFLAG1_RX, priv->base + IMX9_CAN_IMASK1_OFFSET); + + /* Exit freeze mode */ + + imx9_setfreeze(priv->base, 0); + if (!imx9_waitfreezeack_change(priv->base, 0)) + { + nerr("FLEXCAN: unfreeze fail\n"); + return -1; + } + + return 1; +} + +/**************************************************************************** + * Function: imx9_reset + * + * Description: + * Put the EMAC in the non-operational, reset state + * + * Input Parameters: + * priv - Reference to the private FLEXCAN driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void imx9_reset(struct imx9_driver_s *priv) +{ + uint32_t regval; + uint32_t i; + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_SOFTRST; + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + if (!imx9_waitmcr_change(priv->base, CAN_MCR_SOFTRST, 0)) + { + nerr("Reset failed"); + return; + } + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_SUPV); + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + /* Initialize all MB rx and tx */ + + for (i = 0; i < TOTALMBCOUNT; i++) + { + struct mb_s *rx = flexcan_get_mb(priv, i); + ninfo("MB %" PRIi32 " %p\n", i, rx); + ninfo("MB %" PRIi32 " %p\n", i, &rx->id.w); + rx->cs.cs = 0x0; + rx->id.w = 0x0; + rx->data[0].w00 = 0x0; + rx->data[1].w00 = 0x0; + } + + regval = getreg32(priv->base + IMX9_CAN_MCR_OFFSET); + regval |= CAN_MCR_SLFWAK | CAN_MCR_WRNEN | CAN_MCR_SRXDIS | + CAN_MCR_IRMQ | CAN_MCR_AEN | + (((TOTALMBCOUNT - 1) << CAN_MCR_MAXMB_SHIFT) & + CAN_MCR_MAXMB_MASK); + putreg32(regval, priv->base + IMX9_CAN_MCR_OFFSET); + + regval = CAN_CTRL2_RRS | CAN_CTRL2_EACEN; + putreg32(regval, priv->base + IMX9_CAN_CTRL2_OFFSET); + + for (i = 0; i < TOTALMBCOUNT; i++) + { + putreg32(0, priv->base + IMX9_CAN_RXIMR_OFFSET(i)); + } + + /* Filtering catchall */ + + putreg32(0x3fffffff, priv->base + IMX9_CAN_RX14MASK_OFFSET); + putreg32(0x3fffffff, priv->base + IMX9_CAN_RX15MASK_OFFSET); + putreg32(0x3fffffff, priv->base + IMX9_CAN_RXMGMASK_OFFSET); + putreg32(0x0, priv->base + IMX9_CAN_RXFGMASK_OFFSET); +} + +/**************************************************************************** + * Function: imx9_canpinmux + * + * Description: + * Mux the pins used for CAN RX&TX + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +void imx9_canpinmux() +{ +#ifdef CONFIG_IMX9_FLEXCAN1 + imx9_iomux_configure(MUX_FLEXCAN1_TX); + imx9_iomux_configure(MUX_FLEXCAN1_RX); +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 + imx9_iomux_configure(MUX_FLEXCAN2_TX); + imx9_iomux_configure(MUX_FLEXCAN2_RX); +#endif +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: imx9_caninitialize + * + * Description: + * Initialize the CAN controller and driver + * + * Input Parameters: + * intf - In the case where there are multiple CAN, this value + * identifies which CAN is to be initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int imx9_caninitialize(int intf) +{ + struct imx9_driver_s *priv; + int ret; + + switch (intf) + { +#ifdef CONFIG_IMX9_FLEXCAN1 + case 1: + /* Configure root clock to 24MHz OSC and enable peripheral clock */ + + imx9_ccm_configure_root_clock(CCM_CR_CAN1, OSC_24M, 1); + imx9_ccm_gate_on(CCM_LPCG_CAN1, true); + priv = &g_flexcan1; + break; +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 + case 2: + /* Configure root clock to 24MHz OSC and enable peripheral clock */ + + imx9_ccm_configure_root_clock(CCM_CR_CAN1, OSC_24M, 1); + imx9_ccm_gate_on(CCM_LPCG_CAN1, true); + priv = &g_flexcan2; + break; +#endif + + default: + return -ENODEV; + } + + if (!imx9_bitratetotimeseg(&priv->arbi_timing, 1, 0)) + { + nerr("ERROR: Invalid CAN timings please try another sample point " + "or refer to the reference manual\n"); + return -1; + } + + if (priv->canfd_capable) + { + if (!imx9_bitratetotimeseg(&priv->data_timing, 1, 1)) + { + nerr("ERROR: Invalid CAN data phase timings please try another " + "sample point or refer to the reference manual\n"); + return -1; + } + } + + /* Mux the can RX&TX pins */ + + imx9_canpinmux(); + + if (irq_attach(priv->irq, imx9_flexcan_interrupt, priv)) + { + /* We could not attach the ISR to the interrupt */ + + nerr("ERROR: Failed to attach CAN bus IRQ\n"); + return -EAGAIN; + } + + /* Initialize the driver structure */ + + priv->dev.d_ifup = imx9_ifup; /* I/F up (new IP address) callback */ + priv->dev.d_ifdown = imx9_ifdown; /* I/F down callback */ + priv->dev.d_txavail = imx9_txavail; /* New TX data callback */ +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = imx9_ioctl; /* Support CAN ioctl() calls */ +#endif + priv->dev.d_private = (void *)priv; /* Used to recover private state from dev */ + + /* Put the interface in the down state. This usually amounts to resetting + * the device and/or calling imx9_ifdown(). + */ + + ninfo("callbacks done\n"); + + imx9_ifdown(&priv->dev); + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + netdev_register(&priv->dev, NET_LL_CAN); + + UNUSED(ret); + return OK; +} + +/**************************************************************************** + * Name: arm64_caninitialize + * + * Description: + * Initialize the can network interfaces. + * + ****************************************************************************/ + +#if !defined(CONFIG_NETDEV_LATEINIT) +void arm64_caninitialize(void) +{ +#ifdef CONFIG_IMX9_FLEXCAN1 + imx9_caninitialize(1); +#endif + +#ifdef CONFIG_IMX9_FLEXCAN2 + imx9_caninitialize(2); +#endif +} +#endif + +#endif /* CONFIG_IMX9_FLEXCAN */ diff --git a/arch/arm64/src/imx9/imx9_flexcan.h b/arch/arm64/src/imx9/imx9_flexcan.h new file mode 100644 index 0000000000000..fcb56026ec51d --- /dev/null +++ b/arch/arm64/src/imx9/imx9_flexcan.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/arm/src/imx9/imx9_flexcan.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H +#define __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "hardware/imx9_flexcan.h" + +#ifdef CONFIG_IMX9_FLEXCAN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Function: imx9_caninitialize + * + * Description: + * Initialize the enabled CAN device interfaces. If there are more + * different network devices in the chip, then board-specific logic will + * have to provide this function to determine which, if any, network + * devices should be initialized. + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called very early in the initialization sequence. + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_LATEINIT +int imx9_caninitialize(int intf); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_IMX9_FLEXCAN */ +#endif /* __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H */