CPU.hdl

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/05/CPU.hdl

/**
 * The Hack CPU (Central Processing unit), consisting of an ALU,
 * two registers named A and D, and a program counter named PC.
 * The CPU is designed to fetch and execute instructions written in 
 * the Hack machine language. In particular, functions as follows:
 * Executes the inputted instruction according to the Hack machine 
 * language specification. The D and A in the language specification
 * refer to CPU-resident registers, while M refers to the external
 * memory location addressed by A, i.e. to Memory[A]. The inM input 
 * holds the value of this location. If the current instruction needs 
 * to write a value to M, the value is placed in outM, the address 
 * of the target location is placed in the addressM output, and the 
 * writeM control bit is asserted. (When writeM==0, any value may 
 * appear in outM). The outM and writeM outputs are combinational: 
 * they are affected instantaneously by the execution of the current 
 * instruction. The addressM and pc outputs are clocked: although they 
 * are affected by the execution of the current instruction, they commit 
 * to their new values only in the next time step. If reset==1 then the 
 * CPU jumps to address 0 (i.e. pc is set to 0 in next time step) rather 
 * than to the address resulting from executing the current instruction. 
 */

CHIP CPU {

    IN  inM[16],         // M value input  (M = contents of RAM[A])
        instruction[16], // Instruction for execution
        reset;           // Signals whether to re-start the current
                         // program (reset==1) or continue executing
                         // the current program (reset==0).

    OUT outM[16],        // M value output
        writeM,          // Write to M? 
        addressM[15],    // Address in data memory (of M)
        pc[15];          // address of next instruction

    PARTS:
    // Put your code here:
    Not(in=instruction[15],out=isA);//判定是不是A指令
    Not(in=isA,out=isC);//判定是不是C指令
    And(a=isC,b=instruction[5],out=ALUtoA);//控制A暫存
    Mux16(a=instruction,b=ALUout,sel=isC,out=a0);//選擇A暫存的輸入
    Or(a=isA,b=ALUtoA,out=Aload);//A指令或ALU輸出進到A暫存
    ARegister(in=a0,load=Aload,out=Aout);
    And(a=isC,b=instruction[4],out=Dload);//控制D暫存
    DRegister(in=ALUout,load=Dload,out=Dout);//Dloda控制ALUout的暫存
    Mux16(a=Aout,b=inM,sel=instruction[12],out=AorM);//選擇ALU的輸入為A暫存或記憶體
    ALU(x=Dout,y=AorM,zx=instruction[11],nx=instruction[10],zy=instruction[9],
        ny=instruction[8],f=instruction[7],no=instruction[6],out=ALUout,zr=zr,ng=ng);//instruction[6...11]控制運算
    Or16(a=ALUout,b=false,out=outM);//把ALUout放進記憶體
    Or16(a=Aout,b=false,out[0..14]=addressM);//把A暫存的輸出寫入記憶體
    And(a=isC,b=instruction[3],out=writeM);//若為C指令則寫入記憶體
    And(a=zr,b=instruction[1],out=JEQ);//若輸出為0且控制jmp的instruction[1]為1，跳躍指令為JEQ(X = 0)
    And(a=ng,b=instruction[2],out=JLT);//若輸出小於0且控制jmp的instruction[2]為1，跳躍指令為JLT(X < 0)
    Or(a=zr,b=ng,out=zrorng);//輸出小於或等於零
    Not(in=zrorng,out=N);//輸出是否為正數
    And(a=N,b=instruction[0],out=JGT);//若輸出為正且控制jmp的instruction[0]為1，跳躍指令為JGT(X > 0)
    Or(a=JEQ,b=JLT,out=JLE);//若輸出小於或等於0則跳躍指令為JLE(X <= 0)
    Or(a=JLE,b=JGT,out=JMP);//若輸出小於等於或大於0，則跳躍指令為JMP
    And(a=isC,b=JUMP,out=PCload);//若為C指令，並且有JMP指令時，PC載入
    Not(in=PCload,out=PCinc);//PC非載入時則+1
    PC(in=Aout,inc=PCinc,load=PCload,reset=reset,out[0..14]=pc);//以inc/load/reset處理A暫存的輸出
}