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a004580.rcw
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/*
* Work-around for erratum A-004580.
*
* Description:
* An internal tracking loop may falsely lock to an incorrect setting when
* receive noise is not detected on the SerDes Rx lanes. This can cause
* unrecoverable bit errors to occur in each protocol.
*
* Impact:
* Unrecoverable bit errors can lead to link issues for all protocols. SATA
* is not affected by this erratum.
*
* The work-around should be applied to all non-SATA SerDes lanes. Use the
* A4580_xxx macros to disable lanes that don't exist or are connected to
* SATA for that particular SerDes protocol.
*
* Note that the P5040 has a fourth SerDes bank, but that bank is only used
* for SATA, so we just skip it.
*/
.pbi
#ifdef A4580_HAS_B1_LAB
write 0xea420, 0x1b000001 // B1TTLCRA0
write 0xea428, 0x880000
write 0xea430, 0x40000000
write 0xea460, 0x1b000001 // B1TTLCRB0
write 0xea468, 0x880000
write 0xea470, 0x40000000
#endif
write 0xea4a0, 0x1b000001 // B1TTLCRC0
write 0xea4a8, 0x880000
write 0xea4b0, 0x40000000
write 0xea4e0, 0x1b000001 // B1TTLCRD0
write 0xea4e8, 0x880000
write 0xea4f0, 0x40000000
write 0xea520, 0x1b000001 // B1TTLCRE0
write 0xea528, 0x880000
write 0xea530, 0x40000000
write 0xea560, 0x1b000001 // B1TTLCRF0
write 0xea568, 0x880000
write 0xea570, 0x40000000
write 0xea5a0, 0x1b000001 // B1TTLCRG0
write 0xea5a8, 0x880000
write 0xea5b0, 0x40000000
write 0xea5e0, 0x1b000001 // B1TTLCRH0
write 0xea5e8, 0x880000
write 0xea5f0, 0x40000000
write 0xea620, 0x1b000001 // B1TTLCRI0
write 0xea628, 0x880000
write 0xea630, 0x40000000
write 0xea660, 0x1b000001 // B1TTLCRJ0
write 0xea668, 0x880000
write 0xea670, 0x40000000
write 0xea820, 0x1b000001 // B2TTLCRA0
write 0xea828, 0x880000
write 0xea830, 0x40000000
write 0xea860, 0x1b000001 // B2TTLCRB0
write 0xea868, 0x880000
write 0xea870, 0x40000000
#ifdef A4580_HAS_B2_LCD
write 0xea8a0, 0x1b000001 // B2TTLCRC0
write 0xea8a8, 0x880000
write 0xea8b0, 0x40000000
write 0xea8e0, 0x1b000001 // B2TTLCRD0
write 0xea8e8, 0x880000
write 0xea8f0, 0x40000000
#endif
#ifdef A4580_HAS_B3_LAB
write 0xea920, 0x1b000001 // B3TTLCRA0
write 0xea928, 0x880000
write 0xea930, 0x40000000
write 0xea960, 0x1b000001 // B3TTLCRB0
write 0xea968, 0x880000
write 0xea970, 0x40000000
#endif
#ifdef A4580_HAS_B3_LCD
write 0xea9a0, 0x1b000001 // B3TTLCRC0
write 0xea9a8, 0x880000
write 0xea9b0, 0x40000000
write 0xea9e0, 0x1b000001 // B3TTLCRD0
write 0xea9e8, 0x880000
write 0xea9f0, 0x40000000
#endif
flush
.end