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Griffin.cpp
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Griffin.cpp
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#include <stdio.h>
#include <stdlib.h>
#include "Signal.h"
#ifdef _WIN32
#include <windows.h>
#include "OlsApi.h"
#endif
#ifdef __linux
#include "cpuPrimitives.h"
#include <string.h>
#endif
#include "Processor.h"
#include "Griffin.h"
#include "MSRObject.h"
#include "PCIRegObject.h"
#include "PerformanceCounter.h"
//Griffin Class constructor
Griffin::Griffin () {
DWORD eax,ebx,ecx,edx;
//Check extended CpuID Information - CPUID Function 0000_0001 reg EAX
if (Cpuid(0x1,&eax,&ebx,&ecx,&edx)!=TRUE) {
printf ("Griffin::Griffin - Fatal error during querying for Cpuid(0x1) instruction.\n");
return;
}
int familyBase = (eax & 0xf00) >> 8;
int model = (eax & 0xf0) >> 4;
int stepping = eax & 0xf;
int familyExtended = ((eax & 0xff00000) >> 20)+familyBase;
int modelExtended = ((eax & 0xf0000) >> 12)+model;
//Check Brand ID and Package type - CPUID Function 8000_0001 reg EBX
if (Cpuid(0x80000001,&eax,&ebx,&ecx,&edx)!=TRUE) {
printf ("Griffin::Griffin - Fatal error during querying for Cpuid(0x80000001) instruction.\n");
return;
}
int brandId=(ebx & 0xffff);
int processorModel=(brandId >> 4) & 0x7f;
int string1=(brandId >> 11) & 0xf;
int string2=(brandId & 0xf);
int pkgType=(ebx >> 28);
//Sets processor Specs
setSpecFamilyBase (familyBase);
setSpecModel (model);
setSpecStepping (stepping);
setSpecFamilyExtended (familyExtended);
setSpecModelExtended (modelExtended);
setSpecBrandId (brandId);
setSpecProcessorModel (processorModel);
setSpecString1 (string1);
setSpecString2 (string2);
setSpecPkgType (pkgType);
setBoostStates (0);
setMaxSlots(4);
//Check how many physical cores are present - CPUID Function 8000_0008 reg ECX
if (Cpuid(0x80000008,&eax,&ebx,&ecx,&edx)!=TRUE) {
printf ("Griffin::Griffin - Fatal error during querying for Cpuid(0x80000008) instruction.\n");
return;
}
int physicalCores=(ecx & 0xff) + 1;
//Sets Physical cores number
setProcessorCores (physicalCores);
//Sets Physical number of processors
setProcessorNodes (1);
//Set Power states number
setPowerStates (8);
//Detects a Turion ZM processor
if ((physicalCores==2) && (string1==0) && (pkgType==0x2)) {
setProcessorIdentifier (TURION_ULTRA_ZM_FAMILY);
setProcessorStrId ("Turion Ultra ZM Processor");
}
//Detects a Turion RM processor
if ((physicalCores==2) && (string1==1) && (pkgType==0x2)) {
setProcessorIdentifier (TURION_X2_RM_FAMILY);
setProcessorStrId ("Turion X2 RM Processor");
}
//Detects a Turion QL processor
if ((physicalCores==2) && (string1==2) && (pkgType==0x2)) {
setProcessorIdentifier (ATHLON_X2_QL_FAMILY);
setProcessorStrId ("Athlon X2 QL Processor");
}
//Detects a Sempron SI processor
if ((physicalCores==1) && (string1==0) && (pkgType==0x2)) {
setProcessorIdentifier (SEMPRON_SI_FAMILY);
setProcessorStrId ("Sempron SI Processor");
}
}
/*
* Static methods to allow external Main to detect current configuration status
* without instantiating an object. This method that detects if the system
* has a processor supported by this module
*/
bool Griffin::isProcessorSupported () {
DWORD eax;
DWORD ebx;
DWORD ecx;
DWORD edx;
//Check base CpuID information
if (Cpuid(0x0,&eax,&ebx,&ecx,&edx)!=TRUE) return false;
//Checks if eax is 0x1, 0x5 or 0x6. It determines the largest CPUID function available
//Family 11h returns eax=0x1
if ((eax!=0x1)) return false;
//Check for "AuthenticAMD" string
if ((ebx!=0x68747541) || (ecx!=0x444D4163) || (edx!=0x69746E65)) return false;
//Check extended CpuID Information - CPUID Function 0000_0001 reg EAX
if (Cpuid(0x1,&eax,&ebx,&ecx,&edx)!=TRUE) return false;
int familyBase = (eax & 0xf00) >> 8;
//int model = (eax & 0xf0) >> 4;
//int stepping = eax & 0xf;
int familyExtended = ((eax & 0xff00000) >> 20)+familyBase;
//int modelExtended = ((eax & 0xf0000) >> 16)+model;
//Check how many physical cores are present - CPUID Function 8000_0008 reg ECX
if (Cpuid(0x80000008,&eax,&ebx,&ecx,&edx)!=TRUE) return false;
int physicalCores=(ecx & 0xff) + 1;
//Check Brand ID and Package type - CPUID Function 8000_0001 reg EBX
if (Cpuid(0x80000001,&eax,&ebx,&ecx,&edx)!=TRUE) return false;
int brandId=(ebx & 0xffff);
//int processorModel=(brandId >> 4) & 0x7f;
int string1=(brandId >> 11) & 0xf;
//int string2=(brandId & 0xf);
int pkgType=(ebx >> 28);
if (familyExtended!=0x11) return false;
//We will say that a processor is supported ONLY and if ONLY all parameters gathered
//above are precisely as stated below. In any other case, we don't detect a valid processor
if (familyExtended==0x11) {
//Detects a Turion ZM processor
if ((physicalCores==2) && (string1==0) && (pkgType==0x2))
return true;
//Detects a Turion RM processor
if ((physicalCores==2) && (string1==1) && (pkgType==0x2))
return true;
//Detects a Turion QL processor
if ((physicalCores==2) && (string1==2) && (pkgType==0x2))
return true;
//Detects a Sempron SI processor
if ((physicalCores==1) && (string1==0) && (pkgType==0x2))
return true;
}
return false;
}
//Shows specific informations about current processor family
void Griffin::showFamilySpecs () {
DWORD clock_ramp_hyst;
DWORD clock_ramp_hyst_ns;
DWORD psi_l_enable;
DWORD psi_thres;
DWORD vddGanged;
DWORD pstateId;
unsigned int i;
PCIRegObject *pciRegObject;
//Shows Northbridge VID, SMAF7 and C1E info only if we detect a family 11h processor.
//family 10h processors have a different approach
printf ("Processor Northbridge VID: %d (%0.4fV)\n",getNBVid(),convertVIDtoVcore(getNBVid()));
printf ("\n");
if (getSMAF7Enabled()==true)
printf ("SMAF7 is enabled; processor is using ACPI SMAF7 tables\n");
else
printf ("SMAF7 is disabled; using LMM Configuration registers for power management\n");
printf ("DID to apply when in C1E state: %d\n",c1eDID());
printf ("\n");
for (i=0;i<getProcessorCores();i++) {
setCore(i);
if (getC1EStatus()==false)
printf ("Core %d C1E CMP halt bit is disabled\n", i);
else
printf ("Core %d C1E CMP halt bit is enabled\n", i);
}
printf ("\nVoltage Regulator Slamming time register: %d\n",getSlamTime());
printf ("Voltage Regulator AltVID Slamming time register: %d\n",getAltVidSlamTime());
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3, 0xa0, getNodeMask (ALL_NODES))) {
printf ("Unable to read PCI Register\n");
} else {
//Shows Dual plane/Triple plane only on family 11h processors
vddGanged=pciRegObject->getBits(0,30,1);
if (vddGanged==0)
printf ("Processor is operating in Triple Plane mode\n");
else
printf ("Processor is operating in Dual Plane mode\n");
pstateId=pciRegObject->getBits(0,16,12);
printf ("Processor PState Identifier: 0x%x\n", pstateId);
}
free (pciRegObject);
psi_l_enable=getPsiEnabled();
psi_thres=getPsiThreshold();
printf ("Processor is using Serial VID Interface\n");
if (psi_l_enable)
{
printf ("PSI_L bit enabled (improve VRM efficiency in low power)\n");
printf ("PSI voltage threshold VID: %d (%0.4fV)\n", psi_thres, convertVIDtoVcore(psi_thres));
}
else
printf ("PSI_L bit not enabled\n");
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3, 0xd4, getNodeMask (ALL_NODES))) {
printf ("Unable to read PCI Register\n");
} else {
//Shows Clock ramp hysteresis only on family 11h processors
clock_ramp_hyst=pciRegObject->getBits(0, 8, 4);
clock_ramp_hyst_ns=(clock_ramp_hyst+1)*320;
printf ("Clock ramp hysteresis register: %d (%d ns)\n", clock_ramp_hyst, clock_ramp_hyst_ns);
}
free (pciRegObject);
//testMSR();
}
//Miscellaneous function for some conversions
float Griffin::convertVIDtoVcore (DWORD curVid) {
return (float)((124-curVid)*0.0125);
}
DWORD Griffin::convertVcoretoVID (float vcore) {
DWORD vid;
vid=round(((1.55-vcore)/0.0125));
return vid;
}
DWORD Griffin::convertFDtoFreq (DWORD curFid, DWORD curDid) {
return (100*(curFid+0x8))/(1<<curDid);
}
void Griffin::convertFreqtoFD (DWORD freq, int *oFid, int *oDid) {
/*Needs to calculate the approximate frequency using FID and DID right
combinations. Take in account that base frequency is always 200 MHz
(that is Hypertransport 1x link speed).
For family 11h processor the right formula is:
(100*(Fid+8))/(2^Did)
Inverse formulas are:
fid = (((2^Did) * freq) / 100) - 8
did = log2 ((100 * (fid + 8))/f)
The approach I choose here is to minimize DID and maximize FID,
with respect to the fact that it can't go over the maximum FID.
Note: Family 11h processors don't like very much changing FID
between pstates, and often this results in system freezes.
I still can't figure the reason.
As you can see, part of the argument of the log of the DID is obtained
dividing 100*(fid+8) with required frequency.
Since our maximum FID determines also a maximum operating frequency
we can calculate the argument doing MaximumFrequency/WantedFrequency
this way we get the argument of the logarithm. Now we calculate
the DID calculating the logarithm and then taking only the integer
part of the result.
FID then is calculated accordingly, using the inverse formula.
*/
float fid;
float did;
float argument;
if (freq==0) return;
if (maxCPUFrequency()!=0) {
//Normally all family 11h processors have locked upper multiplier
//so we can use the idea above to obtain did and fid
argument=maxCPUFrequency()/(float)freq;
did=(int)(log(argument)/log((float)2));
} else {
//If we got an unlocked multiplier on a Family 11h processor
//(which is very very unlikely), we fix did=2 and then calculate
//a valid fid. This is because we can give lower voltages to
//higher DIDs.
did=2;
}
fid=(((1<<(int)did)*freq)/100)-8;
if (fid>31) fid=31;
//printf ("\n\nFor frequency %d, FID is %f, DID %f\n", freq, fid, did);
*oDid=(int)did;
*oFid=(int)fid;
return;
}
//-----------------------setVID-----------------------------
//Overloads abstract class setVID to allow per-core and per-node personalization
void Griffin::setVID (PState ps, DWORD vid) {
MSRObject *msrObject;
if ((vid<maxVID()) || (vid>minVID())) {
printf ("Griffin.cpp::setVID - VID Allowed range %d-%d\n", maxVID(), minVID());
return;
}
msrObject=new MSRObject();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR+ps.getPState(), getMask ())) {
printf ("Griffin.cpp::setVID - unable to read MSR\n");
free (msrObject);
return;
}
//To set VID, base offset is 9 bits and value is 7 bit wide.
msrObject->setBitsLow(9,7,vid);
if (!msrObject->writeMSR()) {
printf ("Griffin.cpp::setVID - unable to write MSR\n");
free (msrObject);
return;
}
free (msrObject);
return;
}
//-----------------------setFID-----------------------------
//Overloads abstract Processor method to allow per-core personalization
void Griffin::setFID (PState ps, float floatFid) {
unsigned int fid;
MSRObject *msrObject;
fid=(unsigned int) floatFid;
if (fid>31) {
printf ("Griffin.cpp::setFID - FID Allowed range 0-31\n");
return;
}
msrObject=new MSRObject();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR+ps.getPState(), getMask ())) {
printf ("Griffin.cpp::setFID - unable to read MSR\n");
free (msrObject);
return;
}
//To set FID, base offset is 0 bits and value is 6 bit wide
msrObject->setBitsLow(0,6,fid);
if (!msrObject->writeMSR()) {
printf ("Griffin.cpp::setFID - unable to write MSR\n");
free (msrObject);
return;
}
free (msrObject);
return;
}
//-----------------------setDID-----------------------------
//Overloads abstract Processor method to allow per-core personalization
void Griffin::setDID(PState ps, float floatDid) {
unsigned int did;
MSRObject *msrObject;
did=(unsigned int)floatDid;
if (did >= 4) {
printf("Griffin.cpp::setDID - DID Allowed range 0-3\n");
return;
}
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR + ps.getPState(), getMask())) {
printf("Griffin.cpp::setDID - unable to read MSR\n");
free(msrObject);
return;
}
//To set DID, base offset is 6 bits and value is 3 bit wide
msrObject->setBitsLow(6, 3, did);
if (!msrObject->writeMSR()) {
printf("Griffin.cpp::setDID - unable to write MSR\n");
free(msrObject);
return;
}
free (msrObject);
return;
}
//-----------------------getVID-----------------------------
DWORD Griffin::getVID (PState ps) {
MSRObject *msrObject;
DWORD vid;
msrObject=new MSRObject ();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR+ps.getPState(), getMask())) {
printf ("Griffin.cpp::getVID - unable to read MSR\n");
free (msrObject);
return false;
}
//Returns data for the first cpu in cpuMask.
//VID is stored after 9 bits of offset and is 7 bits wide
vid=msrObject->getBitsLow(0, 9, 7);
free (msrObject);
return vid;
}
//-----------------------getFID-----------------------------
float Griffin::getFID (PState ps) {
MSRObject *msrObject;
DWORD fid;
msrObject=new MSRObject ();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR+ps.getPState(), getMask())) {
printf ("Griffin.cpp::getFID - unable to read MSR\n");
free (msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//FID is stored after 0 bits of offset and is 6 bits wide
fid=msrObject->getBitsLow(0, 0, 6);
free (msrObject);
return fid;
}
//-----------------------getDID-----------------------------
float Griffin::getDID (PState ps) {
MSRObject *msrObject;
DWORD did;
msrObject=new MSRObject ();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR+ps.getPState(), getMask())) {
printf ("Griffin.cpp::getDID - unable to read MSR\n");
free (msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//DID is stored after 6 bits of offset and is 3 bits wide
did=msrObject->getBitsLow(0, 6, 3);
free (msrObject);
return (float)did;
}
//-----------------------setFrequency-----------------------------
void Griffin::setFrequency (PState ps, DWORD freq) {
int fid, did;
convertFreqtoFD (freq, &fid, &did);
setFID (ps, (DWORD)fid);
setDID (ps, (DWORD)did);
return;
}
//-----------------------setVCore-----------------------------
void Griffin::setVCore (PState ps, float vcore) {
DWORD vid;
vid=convertVcoretoVID (vcore);
//Check if VID is below maxVID value set by the processor.
//If it is, then there are no chances the processor will accept it and
//we reply with an error
if (vid<maxVID()) {
printf ("Unable to set vcore: %0.4fV (vid %d) exceeds maximum allowed vcore (%0.4fV)\n", vcore, vid, convertVIDtoVcore(maxVID()));
return;
}
//Again we che if VID is above minVID value set by processor.
if (vid>minVID()) {
printf ("Unable to set vcore: %0.4fV is below minimum allowed vcore (%0.4fV)\n", vcore, convertVIDtoVcore(minVID()));
return;
}
setVID (ps,vid);
return;
}
//-----------------------getFrequency-----------------------------
DWORD Griffin::getFrequency (PState ps) {
DWORD curFid, curDid;
DWORD curFreq;
curFid=getFID (ps);
curDid=getDID (ps);
curFreq=convertFDtoFreq(curFid, curDid);
return curFreq;
}
//-----------------------getVCore-----------------------------
float Griffin::getVCore (PState ps) {
DWORD curVid;
float curVcore;
curVid=getVID (ps);
curVcore=convertVIDtoVcore(curVid);
return curVcore;
}
void Griffin::testMSR() {
PCIRegObject *pciRegObject;
unsigned int temp;
pciRegObject = new PCIRegObject ();
if (!pciRegObject->readPCIReg(0x3, 0x18, 0x64, 0x1)) {
printf ("Unable to read PCIRegister\n");
free (pciRegObject);
return;
}
printf ("HTC is locked %d\n" , pciRegObject->getBits(0, 31, 1));
printf ("HTC PState limit %d\n" , pciRegObject->getBits(0, 28, 3));
printf ("Hysteresis %d\n" , (pciRegObject->getBits(0, 24, 4)>>1));
printf ("HTC slew %d\n" , pciRegObject->getBits(0, 23, 1));
temp=52 + (pciRegObject->getBits(0, 16, 7)>>1);
printf ("Temp limit: %d\n" , temp);
pciRegObject->setBits(24,4,6);
pciRegObject->writePCIReg();
free (pciRegObject);
return;
}
//PStates enable/disable/peek
void Griffin::pStateDisable (PState ps) {
MSRObject *msrObject;
msrObject=new MSRObject();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR+ps.getPState(), getMask ())) {
printf ("Griffin.cpp::pStateDisable - unable to read MSR\n");
free (msrObject);
return;
}
//To disable a pstate, base offset is 63 bits (31th bit of edx) and value is 1 bit wide
msrObject->setBitsHigh(31,1,0x0);
if (!msrObject->writeMSR()) {
printf ("Griffin.cpp::pStateDisable - unable to write MSR\n");
free (msrObject);
return;
}
free (msrObject);
return;
}
void Griffin::pStateEnable (PState ps) {
MSRObject *msrObject;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR + ps.getPState(), getMask())) {
printf("Griffin.cpp::pStateEnable - unable to read MSR\n");
free(msrObject);
return;
}
//To enable a pstate, base offset is 63 bits (31th bit of edx) and value is 1 bit wide
msrObject->setBitsHigh(31, 1, 0x1);
if (!msrObject->writeMSR()) {
printf("Griffin.cpp::pStateEnable - unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
bool Griffin::pStateEnabled(PState ps) {
MSRObject *msrObject;
unsigned int status;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_ZM_PSTATEMSR + ps.getPState(), getMask())) {
printf("Griffin.cpp::pStateEnabled - unable to read MSR\n");
free(msrObject);
return false;
}
//To peek a pstate, base offset is 63 bits (31th bit of edx) and value is 1 bit wide
//We consider just the first cpu in cpuMask
status=msrObject->getBitsHigh(0, 31, 1);
free(msrObject);
if (status==0) return false; else return true;
}
void Griffin::setMaximumPState (PState ps) {
PCIRegObject *pciRegObject;
pciRegObject=new PCIRegObject ();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3, 0xdc, getNodeMask())) {
printf ("Griffin.cpp::setMaximumPState - unable to read PCI register\n");
free (pciRegObject);
return;
}
/*
* Maximum pstate is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xdc
* bits from 8 to 10
*/
pciRegObject->setBits(8,3,ps.getPState());
if (!pciRegObject->writePCIReg()) {
printf ("Griffin.cpp::setMaximumPState - unable to write PCI register\n");
free (pciRegObject);
return;
}
free (pciRegObject);
return;
}
PState Griffin::getMaximumPState () {
PCIRegObject *pciRegObject;
PState pState (0);
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3, 0xdc, getNodeMask())) {
printf ("Griffin.cpp::getMaximumPState - unable to read PCI register\n");
free (pciRegObject);
return 0;
}
/*
* Maximum pstate is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xdc
* bits from 8 to 10
*/
pState.setPState(pciRegObject->getBits(0, 8 ,3));
free (pciRegObject);
return pState;
}
void Griffin::setNBVid(DWORD nbvid) {
PCIRegObject *pciRegObject;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3, 0xdc,
getNodeMask())) {
printf("Griffin.cpp::setNBVid - unable to read PCI Register\n");
free(pciRegObject);
return;
}
/* Northbridge VID is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xdc
* bits from 12 to 18
*/
pciRegObject->setBits(12, 7, nbvid);
if (!pciRegObject->writePCIReg()) {
printf("Griffin.cpp::setNBVid - unable to write PCI register\n");
free(pciRegObject);
return;
}
free (pciRegObject);
return;
}
DWORD Griffin::getNBVid(void) {
PCIRegObject *pciRegObject;
DWORD nbVid;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xdc, getNodeMask())) {
printf("Griffin.cpp::getNBVid - unable to read PCI register\n");
free(pciRegObject);
return 0;
}
/*
* Northbridge VID is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xdc
* bits from 12 to 18
*/
nbVid = pciRegObject->getBits(0, 12, 7);
free (pciRegObject);
return nbVid;
}
void Griffin::forcePState (PState ps) {
MSRObject *msrObject;
msrObject=new MSRObject();
if (!msrObject->readMSR(BASE_PSTATE_CTRL_REG, getMask ())) {
printf ("Griffin.cpp::forcePState - unable to read MSR\n");
free (msrObject);
return;
}
//To force a pstate, we act on setting the first 3 bits of register. All other bits must be zero
msrObject->setBitsLow(0,32,0x0);
msrObject->setBitsHigh(0,32,0x0);
msrObject->setBitsLow(0,3,ps.getPState());
if (!msrObject->writeMSR()) {
printf ("Griffin.cpp::forcePState - unable to write MSR\n");
free (msrObject);
return;
}
free (msrObject);
return;
}
bool Griffin::getSMAF7Enabled () {
PCIRegObject *pciRegObject;
DWORD smaf7;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xd4, getNodeMask())) {
printf("Griffin.cpp::getSMAF7Enabled - unable to read PCI register\n");
free(pciRegObject);
return NULL;
}
/*
* SMAF7 bit is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xd4
* bit 18
*/
smaf7 = !pciRegObject->getBits(0, 18, 1);
free(pciRegObject);
return (bool) smaf7;
}
DWORD Griffin::c1eDID() {
PCIRegObject *pciRegObject;
DWORD c1eDid;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0x1ec, getNodeMask())) {
printf("Griffin.cpp::c1eDID - unable to read PCI register\n");
free(pciRegObject);
return 0;
}
/*
* C1E DID bit is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xd4
* bits from 16 to 18
*/
c1eDid = pciRegObject->getBits(0, 16, 3);
free(pciRegObject);
return c1eDid;
}
//Be careful, minVid is supposed to work per-node
DWORD Griffin::minVID() {
MSRObject *msrObject;
DWORD minVid;
msrObject = new MSRObject();
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Griffin.cpp::minVID - unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0).
//MinVid has base offset at 10 bits of high register (edx) and is 7 bit wide
minVid = msrObject->getBitsHigh(0, 10, 7);
free(msrObject);
return minVid;
}
//MaxVID is supposed to work per-node
DWORD Griffin::maxVID () {
MSRObject *msrObject;
DWORD maxVid;
msrObject = new MSRObject();
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Griffin.cpp::maxVID - unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//MaxVid has base offset at 3 bits of high register (edx) and is 7 bit wide
maxVid = msrObject->getBitsHigh(0, 3, 7);
free(msrObject);
return maxVid;
}
//StartupPstate is supposed to be retrieved per node
DWORD Griffin::startupPState() {
MSRObject *msrObject;
DWORD pstate;
msrObject = new MSRObject();
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Griffin.cpp::startupPState - unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//StartupPState has base offset at 0 bits of high register (edx) and is 3 bit wide
pstate = msrObject->getBitsHigh(0, 0, 3);
free(msrObject);
return pstate;
}