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Llano.cpp
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#include <stdio.h>
#include <stdlib.h>
#include "Signal.h"
#ifdef _WIN32
#include <windows.h>
#include "OlsApi.h"
#endif
#ifdef __linux
#include "cpuPrimitives.h"
#include <string.h>
#endif
#include "Processor.h"
#include "Llano.h"
#include "PCIRegObject.h"
#include "MSRObject.h"
#include "PerformanceCounter.h"
//Llano class constructor
Llano::Llano() {
DWORD eax, ebx, ecx, edx;
DWORD nodes;
DWORD cores;
didDivisors[0] = 1;
didDivisors[1] = 1.5;
didDivisors[2] = 2;
didDivisors[3] = 3;
didDivisors[4] = 4;
didDivisors[5] = 6;
didDivisors[6] = 8;
didDivisors[7] = 12;
didDivisors[8] = 16;
//Check extended CpuID Information - CPUID Function 0000_0001 reg EAX
if (Cpuid(0x1, &eax, &ebx, &ecx, &edx) != TRUE) {
printf(
"Llano::Llano - Fatal error during querying for Cpuid(0x1) instruction.\n");
return;
}
int familyBase = (eax & 0xf00) >> 8;
int model = (eax & 0xf0) >> 4;
int stepping = eax & 0xf;
int familyExtended = ((eax & 0xff00000) >> 20) + familyBase;
int modelExtended = ((eax & 0xf0000) >> 12) + model; /* family 12h: modelExtended is valid */
//Check Brand ID and Package type - CPUID Function 8000_0001 reg EBX
if (Cpuid(0x80000001, &eax, &ebx, &ecx, &edx) != TRUE) {
printf(
"Llano::Llano - Fatal error during querying for Cpuid(0x80000001) instruction.\n");
return;
}
int brandId = (ebx & 0xffff);
int processorModel = (brandId >> 4) & 0x7f;
int string1 = (brandId >> 11) & 0xf;
int string2 = (brandId & 0xf);
int pkgType = (ebx >> 28);
//Sets processor Specs
setSpecFamilyBase(familyBase);
setSpecModel(model);
setSpecStepping(stepping);
setSpecFamilyExtended(familyExtended);
setSpecModelExtended(modelExtended);
setSpecBrandId(brandId);
setSpecProcessorModel(processorModel);
setSpecString1(string1);
setSpecString2(string2);
setSpecPkgType(pkgType);
setBoostStates(0);
setMaxSlots(4);
//Llano platform will always contain one node per system, since it has no Hypertransport Link.
//Maybe can change in the future.
nodes = 1;
//Check how many physical cores are present - CPUID Function 8000_0008 reg ECX
if (Cpuid(0x80000008, &eax, &ebx, &ecx, &edx) != TRUE) {
printf(
"Llano::Llano- Fatal error during querying for Cpuid(0x80000008) instruction.\n");
return;
}
cores = (ecx & 0xff) + 1; /* cores per package */
setProcessorNodes(nodes);
setProcessorCores(cores);
setPowerStates(8);
setProcessorIdentifier(PROCESSOR_12H_FAMILY);
setProcessorStrId("Family 12h Llano Processor");
}
/*
* Static methods to allow external Main to detect current configuration status
* without instantiating an object. This method that detects if the system
* has a processor supported by this module
*/
bool Llano::isProcessorSupported() {
DWORD eax;
DWORD ebx;
DWORD ecx;
DWORD edx;
//TODO: remove to avoid simulation
//return true;
//Check base CpuID information
if (Cpuid(0x0, &eax, &ebx, &ecx, &edx) != TRUE)
return false;
//Checks if eax is 0x6. It determines the largest CPUID function available
//Family 12h returns eax=0x6
if (eax != 0x6)
return false;
//Check "AuthenticAMD" string
if ((ebx != 0x68747541) || (ecx != 0x444D4163) || (edx != 0x69746E65))
return false;
//Check extended CpuID Information - CPUID Function 0000_0001 reg EAX
if (Cpuid(0x1, &eax, &ebx, &ecx, &edx) != TRUE)
return false;
int familyBase = (eax & 0xf00) >> 8;
int familyExtended = ((eax & 0xff00000) >> 20) + familyBase;
if (familyExtended != 0x12)
return false;
//Detects a Family 12h processor, i.e. Llano processor (A-series or E2-series)
return true;
}
void Llano::showFamilySpecs() {
printf("Not yet implemented.\n");
}
//Miscellaneous function inherited by Processor abstract class and that
//needs to be reworked for family 10h
float Llano::convertVIDtoVcore(DWORD curVid) {
/*How to calculate VID from Vcore.
Serial VID Interface is simple to calculate. Family 12h uses only Serial VID
To obtain vcore from VID you need to do:
vcore = 1,55 – (VID * 0.0125)
The inverse formula to obtain VID from vcore is:
vid = (1.55-vcore)/0.0125
*/
float curVcore;
if (curVid >= 0x7c)
curVcore = 0;
else
curVcore = (float) (1.550 - (0.0125 * curVid));
return curVcore;
}
DWORD Llano::convertVcoretoVID(float vcore) {
DWORD vid;
vid = round(((1.55 - vcore) / 0.0125));
return vid;
}
float Llano::roundDivisor(float divisor) {
int i;
for (i = 0; i < 9; i++)
if (divisor <= didDivisors[i])
return didDivisors[i];
return didDivisors[7];
}
int Llano::roundDivisorToDid(float divisor) {
int i;
for (i = 0; i < 9; i++)
if (divisor <= didDivisors[i])
return i;
return 7;
}
DWORD Llano::convertFDtoFreq(float fid, float divisor) {
return (int) ((100 * ((int) fid + 0x10)) / divisor);
}
void Llano::convertFreqtoFD(DWORD freq, float *oFid, float *oDivisor) {
/*
*
For family 12h processor the right formula is:
(cfr. BKDG for AMD Family 12h, doc #41131 rev 3.00 - page 468)
(100 * (fid + 16)) / (divisor specified by DID)
Inverse formula is
fid= ((divisor * freq) / 100) - 16
did = roundDivisorToDid ((100 * (fid +16))/f)
*/
float fid;
int did;
if (freq == 0)
return;
did = 0;
do {
fid = (((didDivisors[did]) * (float) freq) / 100) - 16;
if (fid < 0)
did++;
} while (fid < 0);
if (fid > 31)
fid = 31;
//Actually we don't need to reculate DID, since we guessed a
//valid one due to the fact that the argument is positive.
*oFid = round(fid);
*oDivisor = didDivisors[did];
//TODO: Debug printf:
printf("\n\nFor frequency %d, FID is %f, DID %f\n", freq, *oFid, *oDivisor);
return;
}
//-----------------------setVID-----------------------------
//Overloads abstract class setVID to allow per-core personalization
void Llano::setVID(PState ps, DWORD vid) {
MSRObject *msrObject;
if ((vid > minVID()) || (vid < maxVID())) {
printf("Llano.cpp: VID Allowed range %d-%d\n", minVID(), maxVID());
return;
}
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp: unable to read MSR\n");
free(msrObject);
return;
}
//To set VID, base offset is 9 bits and value is 7 bit wide.
msrObject->setBitsLow(9, 7, vid);
if (!msrObject->writeMSR()) {
printf("Llano.cpp: unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
//-----------------------setFID-----------------------------
//Overloads abstract Processor method to allow per-core personalization
void Llano::setFID(PState ps, float floatFid) {
unsigned int fid;
MSRObject *msrObject;
fid = (unsigned int) round(floatFid);
if (fid > 31) {
printf("Llano.cpp: FID Allowed range 0-31\n");
return;
}
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp: unable to read MSR\n");
free(msrObject);
return;
}
//To set FID, base offset is 4 bits and value is 5 bit wide
msrObject->setBitsLow(4, 5, fid);
if (!msrObject->writeMSR()) {
printf("Llano.cpp: unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
//-----------------------setDID-----------------------------
//Overloads abstract Processor method to allow per-core personalization
void Llano::setDID(PState ps, float divisor) {
unsigned int did;
MSRObject *msrObject;
did = roundDivisorToDid(divisor);
if (divisor < 1 || divisor > 16) {
printf("Llano.cpp: divisor(DID) allowed range 1-16\n");
return;
}
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp: unable to read MSR\n");
free(msrObject);
return;
}
//To set DID, base offset is 0 bits and value is 4 bit wide
msrObject->setBitsLow(0, 4, did);
if (!msrObject->writeMSR()) {
printf("Llano.cpp: unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
//-----------------------getVID-----------------------------
DWORD Llano::getVID(PState ps) {
MSRObject *msrObject;
DWORD vid;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp::getVID - unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask.
//VID is stored after 9 bits of offset and is 7 bits wide
vid = msrObject->getBitsLow(0, 9, 7);
free(msrObject);
return vid;
}
//-----------------------getFID-----------------------------
float Llano::getFID(PState ps) {
MSRObject *msrObject;
DWORD fid;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp::getFID - unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//FID is stored after 4 bits of offset and is 5 bits wide
fid = msrObject->getBitsLow(0, 4, 5);
free(msrObject);
return fid;
}
//-----------------------getDID-----------------------------
float Llano::getDID(PState ps) {
MSRObject *msrObject;
float divisor;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp::getDID - unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//DID is stored after 0 bits of offset and is 4 bits wide
divisor = didDivisors[msrObject->getBitsLow(0, 0, 4)];
free(msrObject);
return divisor;
}
//-----------------------setFrequency-----------------------------
void Llano::setFrequency(PState ps, DWORD freq) {
float did;
float fid;
convertFreqtoFD(freq, &fid, &did);
setFID(ps, fid);
setDID(ps, did);
return;
}
//-----------------------setVCore-----------------------------
void Llano::setVCore(PState ps, float vcore) {
DWORD vid;
vid = convertVcoretoVID(vcore);
//Check if VID is below maxVID value set by the processor.
//If it is, then there are no chances the processor will accept it and
//we reply with an error
if (vid < maxVID()) {
printf(
"Unable to set vcore: %0.4fV exceeds maximum allowed vcore (%0.4fV)\n",
vcore, convertVIDtoVcore(maxVID()));
return;
}
//Again we che if VID is above minVID value set by processor.
if (vid > minVID()) {
printf(
"Unable to set vcore: %0.4fV is below minimum allowed vcore (%0.4fV)\n",
vcore, convertVIDtoVcore(minVID()));
return;
}
setVID(ps, vid);
return;
}
//-----------------------getFrequency-----------------------------
DWORD Llano::getFrequency(PState ps) {
float curDid;
float curFid;
DWORD curFreq;
curFid = getFID(ps);
curDid = getDID(ps);
curFreq = convertFDtoFreq(curFid, curDid);
return curFreq;
}
//-----------------------getVCore-----------------------------
float Llano::getVCore(PState ps) {
DWORD curVid;
float curVcore;
curVid = getVID(ps);
curVcore = convertVIDtoVcore(curVid);
return curVcore;
}
//PStates enable/disable/peek
void Llano::pStateDisable(PState ps) {
MSRObject *msrObject;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp::pStateDisable - unable to read MSR\n");
free(msrObject);
return;
}
//To disable a pstate, base offset is 63 bits (31th bit of edx) and value is 1 bit wide
msrObject->setBitsHigh(31, 1, 0x0);
if (!msrObject->writeMSR()) {
printf("Llano.cpp::pStateDisable - unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
void Llano::pStateEnable(PState ps) {
MSRObject *msrObject;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp::pStateEnable - unable to read MSR\n");
free(msrObject);
return;
}
//To disable a pstate, base offset is 63 bits (31th bit of edx) and value is 1 bit wide
msrObject->setBitsHigh(31, 1, 0x1);
if (!msrObject->writeMSR()) {
printf("Llano.cpp:pStateEnable - unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
bool Llano::pStateEnabled(PState ps) {
MSRObject *msrObject;
unsigned int status;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_12H_PSTATEMSR + ps.getPState(), getMask())) {
printf("Llano.cpp::pStateEnabled - unable to read MSR\n");
free(msrObject);
return false;
}
//To peek a pstate, base offset is 63 bits (31th bit of edx) and value is 1 bit wide
//We consider just the first cpu in cpuMask
status = msrObject->getBitsHigh(0, 31, 1);
free(msrObject);
if (status == 0)
return false;
else
return true;
}
void Llano::setMaximumPState(PState ps) {
PCIRegObject *pciRegObject;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xdc, getNodeMask())) {
printf("Llano.cpp::setMaximumPState - unable to read PCI register\n");
free(pciRegObject);
return;
}
/*
* Maximum pstate is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xdc
* bits from 8 to 10
*/
pciRegObject->setBits(8, 3, ps.getPState());
if (!pciRegObject->writePCIReg()) {
printf("Llano.cpp::setMaximumPState - unable to write PCI register\n");
free(pciRegObject);
return;
}
free(pciRegObject);
return;
}
PState Llano::getMaximumPState() {
PCIRegObject *pciRegObject;
PState pState(0);
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xdc, getNodeMask())) {
printf("Llano.cpp::getMaximumPState - unable to read PCI register\n");
free(pciRegObject);
return 0;
}
/*
* Maximum pstate is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xdc
* bits from 8 to 10
*/
pState.setPState(pciRegObject->getBits(0, 8, 3));
free(pciRegObject);
return pState;
}
void Llano::forcePState(PState ps) {
MSRObject *msrObject;
msrObject = new MSRObject();
if (!msrObject->readMSR(BASE_PSTATE_CTRL_REG, getMask())) {
printf("Llano.cpp::forcePState - unable to read MSR\n");
free(msrObject);
return;
}
//To force a pstate, we act on setting the first 3 bits of register. All other bits must be zero
msrObject->setBitsLow(0, 32, 0x0);
msrObject->setBitsHigh(0, 32, 0x0);
msrObject->setBitsLow(0, 3, ps.getPState());
if (!msrObject->writeMSR()) {
printf("Llano.cpp::forcePState - unable to write MSR\n");
free(msrObject);
return;
}
free(msrObject);
return;
}
//minVID is reported per-node, so selected core is always discarded
DWORD Llano::minVID() {
MSRObject *msrObject;
DWORD minVid;
msrObject = new MSRObject;
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Llano::minVID - Unable to read MSR\n");
free(msrObject);
return false;
}
//minVid is stored in COFVID_STATUS_REG in high half register (edx)
//from bit 10 to bit 16
minVid = msrObject->getBitsHigh(0, 10, 7);
free(msrObject);
//If minVid==0, then there's no minimum vid.
//Since the register is 7-bit wide, then 127 is
//the maximum value allowed.
if (getPVIMode()) {
//Parallel VID mode, allows minimum vcore VID up to 0x5d
if (minVid == 0)
return 0x5d;
else
return minVid;
} else {
//Serial VID mode, allows minimum vcore VID up to 0x7b
if (minVid == 0)
return 0x7b;
else
return minVid;
}
}
//maxVID is reported per-node, so selected core is always discarded
DWORD Llano::maxVID() {
MSRObject *msrObject;
DWORD maxVid;
msrObject = new MSRObject;
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Llano::maxVID - Unable to read MSR\n");
free(msrObject);
return false;
}
//maxVid is stored in COFVID_STATUS_REG in high half register (edx)
//from bit 3 to bit 9
maxVid = msrObject->getBitsHigh(0, 3, 7);
free(msrObject);
//If maxVid==0, then there's no maximum set in hardware
if (maxVid == 0)
return 0;
else
return maxVid;
}
//StartupPState is reported per-node. Selected core is discarded
DWORD Llano::startupPState() {
MSRObject *msrObject;
DWORD pstate;
msrObject = new MSRObject();
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Llano.cpp::startupPState unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//StartupPState has base offset at 0 bits of high register (edx) and is 3 bit wide
pstate = msrObject->getBitsHigh(0, 0, 3);
free(msrObject);
return pstate;
}
DWORD Llano::maxCPUFrequency() {
//return (0+0x10)*100; //Returns 1600 Mhz processor --- simulated stub!!!
MSRObject *msrObject;
DWORD maxCPUFid;
msrObject = new MSRObject();
if (!msrObject->readMSR(COFVID_STATUS_REG, getMask(0, selectedNode))) {
printf("Llano.cpp::maxCPUFrequency unable to read MSR\n");
free(msrObject);
return false;
}
//Returns data for the first cpu in cpuMask (cpu 0)
//maxCPUFid has base offset at 17 bits of high register (edx) and is 6 bits wide
maxCPUFid = msrObject->getBitsHigh(0, 17, 6);
free(msrObject);
return (maxCPUFid + 0x10) * 100;
}
//Temperature registers ------------------
DWORD Llano::getTctlRegister(void) {
PCIRegObject *pciRegObject;
DWORD temp;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xa4, getNodeMask())) {
printf("Llano.cpp::getTctlRegister - unable to read PCI register\n");
free(pciRegObject);
return 0;
}
/*
* Tctl data is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xa4
* bits from 21 to 31
*/
temp = pciRegObject->getBits(0, 21, 11);
free(pciRegObject);
return temp >> 3;
}
DWORD Llano::getTctlMaxDiff() {
PCIRegObject *pciRegObject;
DWORD maxDiff;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xa4, getNodeMask())) {
printf("Llano.cpp::getTctlMaxDiff unable to read PCI register\n");
free(pciRegObject);
return 0;
}
/*
* Tctl Max diff data is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xa4
* bits from 5 to 6
*/
maxDiff = pciRegObject->getBits(0, 5, 2);
free(pciRegObject);
return maxDiff;
}
//Voltage Slamming time
DWORD Llano::getRampTime(void) {
PCIRegObject *pciRegObject;
DWORD slamTime;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xd8, getNodeMask())) {
printf("Llano.cpp::getRampTime unable to read PCI register\n");
free(pciRegObject);
return 0;
}
/*
* voltage ramptime is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xd8
* bits from 4 to 6
*/
slamTime = pciRegObject->getBits(0, 4, 3);
free(pciRegObject);
return slamTime;
}
void Llano::setRampTime(DWORD slmTime) {
PCIRegObject *pciRegObject;
if (slmTime < 0 || slmTime > 7) {
printf("Invalid Ramp Time: must be between 0 and 7\n");
return;
}
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xd8, getNodeMask())) {
printf("Llano::setRampTime - unable to read PCI Register\n");
free(pciRegObject);
return;
}
/*
* voltage slamtime is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xd8
* bits from 4 to 6
*/
pciRegObject->setBits(4, 3, slmTime);
if (!pciRegObject->writePCIReg()) {
printf("Llano.cpp::setRampTime - unable to write PCI register\n");
free(pciRegObject);
return;
}
free(pciRegObject);
return;
}
// AltVID - HTC Thermal features
bool Llano::HTCisCapable() {
PCIRegObject *pciRegObject;
DWORD isCapable;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0xe8, getNodeMask())) {
printf("Llano::HTCisCapable - unable to read PCI register\n");
free(pciRegObject);
return false;
}
/*
* HTC-capable bit is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0xe8
* bit 10
*/
isCapable = pciRegObject->getBits(0, 10, 1);
free(pciRegObject);
return (bool) isCapable;
}
bool Llano::HTCisEnabled() {
PCIRegObject *pciRegObject;
DWORD isEnabled;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0x64, getNodeMask())) {
printf("Llano::HTCisEnabled - unable to read PCI register\n");
free(pciRegObject);
return false;
}
/*
* HTC-enabled bit is stored in PCI register with
* device PCI_DEV_NORTHBRIDGE
* function PC_FUNC_MISC_CONTROL_3
* register 0x64
* bit 0
*/
isEnabled = pciRegObject->getBits(0, 0, 1);
free(pciRegObject);
return (bool) isEnabled;
}
bool Llano::HTCisActive() {
PCIRegObject *pciRegObject;
DWORD isActive;
pciRegObject = new PCIRegObject();
if (!pciRegObject->readPCIReg(PCI_DEV_NORTHBRIDGE, PCI_FUNC_MISC_CONTROL_3,
0x64, getNodeMask())) {
printf("Llano::HTCisActive - unable to read PCI register\n");
free(pciRegObject);
return false;
}