samples: ping-pong: remove the hack to fix the

cache coherence issue, and replace by creating the shared ram memory with no-cached attribute. Signed-off-by: Felipe Neves <[email protected]>
uLipe · Oct 29, 2024 · 54014d7 · 54014d7
1 parent dbd2d20
commit 54014d7
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diff --git a/samples/ping-pong/README.rst b/samples/ping-pong/README.rst
@@ -74,24 +74,3 @@ message from primary core arriving to it:
 
 You should see also the LED0 (if present) on your board blinking
 every time an event arrives to one of the CPUs.
-
-STM32H74xx dual core users, please read!
-****************************************
-
-We use for the shared memory the SRAM4 region, and for some reason the Zephyr
-kernel does not map this region as a non-cacheable area, which may cause issues
-and data loss when using ZIPM, the current workaround I found was to patch
-the `mpu_regions.c` files located under `zephyr/soc/st/stm32h7/mpu_regions.c`,
-
-Inside of this file, there is an vector with memory regions, to make sure 
-ZIPM will work proper add on the vector the SRAM4 and set the non-cacheable
-attribute as shown below:
-
-.. code-block:: c
-
-    MPU_REGION_ENTRY("SRAM4",
-                    DT_REG_ADDR(DT_NODELABEL(sram4)),
-                    REGION_RAM_NOCACHE_ATTR(REGION_64K)),
-
-It probably there is an way of doing this out-of-tree, that needs
-to be investigated later.
diff --git a/samples/ping-pong/rx/boards/arduino_giga_r1_stm32h747xx_m4.overlay b/samples/ping-pong/rx/boards/arduino_giga_r1_stm32h747xx_m4.overlay
@@ -4,7 +4,23 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-&sram4 {
+ / {
+	chosen {
+		/delete-property/ zephyr,ipc_shm;
+	};
+
+	/* We redefine the memory and remove the cache attr due to cache coherence issues */
+	/delete-node/ memory@38000000;
+
+	shared_ram: memory@38000000 {
+		 zephyr,memory-region = "shared_ram";
+		 compatible = "zephyr,memory-region", "mmio-sram";
+		 reg = <0x38000000 0x10000>;
+		 zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+	 };
+};
+
+&shared_ram {
 	#address-cells = <1>;
 	#size-cells = <0>;
 

diff --git a/samples/ping-pong/tx/boards/arduino_giga_r1_stm32h747xx_m7.overlay b/samples/ping-pong/tx/boards/arduino_giga_r1_stm32h747xx_m7.overlay
@@ -10,6 +10,17 @@
 		zephyr,shell-uart = &cdc_acm_uart0;
 		zephyr,cdc-acm-uart0 = &cdc_acm_uart0;
 	};
+
+	/* We redefine the memory and remove the cache attr due to cache coherence issues */
+	/delete-node/ memory@38000000;
+
+	shared_ram: memory@38000000 {
+			zephyr,memory-region = "shared_ram";
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x38000000 0x10000>;
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+	};
+
 };
 
 zephyr_udc0: &usbotg_fs {
@@ -26,7 +37,7 @@ zephyr_udc0: &usbotg_fs {
 	status = "okay";
 };
 
-&sram4 {
+&shared_ram {
 	#address-cells = <1>;
 	#size-cells = <0>;