Makefrag

SBT ?= sbt

lookup_scala_srcs = $(shell find $(1)/ -iname "*.scala" 2> /dev/null)

PACKAGES=rocket-chip
SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)

ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/target/scala-2.11/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-2.11/*"
FIRRTL ?= sbt runMain firrtl.Driver

build_dir=$(sim_dir)/generated-src

CHISEL_ARGS ?=

FIRRTL_FILE=$(build_dir)/$(CFG_PROJECT).$(CONFIG).fir
ANNO_FILE=$(build_dir)/$(CFG_PROJECT).$(CONFIG).anno.json
VERILOG_FILE=$(build_dir)/$(CFG_PROJECT).$(CONFIG).v

$(FIRRTL_FILE) $(ANNO_FILE): $(SCALA_SOURCES) $(bootrom_img) $(FIRRTL_JAR)
	mkdir -p $(build_dir)
	cd $(base_dir) && $(SBT) "runMain $(PROJECT).Generator $(CHISEL_ARGS) $(build_dir) $(PROJECT) $(MODEL) $(CFG_PROJECT) $(CONFIG)"

$(VERILOG_FILE): $(FIRRTL_FILE) $(ANNO_FILE) $(FIRRTL_JAR)
	cd $(base_dir) && $(SBT) "runMain firrtl.Driver -i $(FIRRTL_FILE) -o $(VERILOG_FILE) -X verilog -faf $(ANNO_FILE) -fct firrtl.transforms.BlackBoxSourceHelper -td $(build_dir)"

regression-tests = \
	rv64ud-v-fcvt \
        rv64ud-p-fdiv \
        rv64ud-v-fadd \
        rv64uf-v-fadd \
        rv64um-v-mul \
        rv64mi-p-breakpoint \
        rv64uc-v-rvc \
        rv64ud-v-structural \
        rv64si-p-wfi \
        rv64um-v-divw \
        rv64ua-v-lrsc \
        rv64ui-v-fence_i \
        rv64ud-v-fcvt_w \
        rv64uf-v-fmin \
        rv64ui-v-sb \
        rv64ua-v-amomax_d \
        rv64ud-v-move \
        rv64ud-v-fclass \
        rv64ua-v-amoand_d \
        rv64ua-v-amoxor_d \
        rv64si-p-sbreak \
        rv64ud-v-fmadd \
        rv64uf-v-ldst \
        rv64um-v-mulh \
        rv64si-p-dirty

output_dir=$(sim_dir)/output

$(output_dir)/%: $(RISCV)/riscv64-unknown-elf/share/riscv-tests/isa/%
	mkdir -p $(output_dir)
	ln -sf $< $@