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pcileech_sp605_mig.ucf
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pcileech_sp605_mig.ucf
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###############################################################################
# DEFINES RELATED TO THE DDR3 DRAM INTERACE OPTIONALLY USED IN THE DESIGN
# AS A LARGER BUFFER. NB! NO BIG TRANSFER SPEED INCREASES HAVE BEEN NOTED
# WHEN USING LARGER DDR3 "BUFFER" INSTEAD OF SMALL BRAM "BUFFER" PROBABLY
# DUE TO PCIe BOTTLENECK AND OTHER INEFFICIENCIES ...
# THIS IS COMMENDED AWAY BY DEFAULT IN THIS FILE AND IN pcileech_top.v
# BUT MAY BE COMMENDED IN IF ONE WISH TO LOOK INTO THIS FURTHER...
###############################################################################
# CONFIG VCCAUX=2.5;
# CONFIG MCB_PERFORMANCE=STANDARD;
# NET "i_pcileech_out_buffer_ram/i_mig/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
# NET "i_pcileech_out_buffer_ram/i_mig/c?_pll_lock" TIG;
# INST "i_pcileech_out_buffer_ram/i_mig/memc?_wrapper_inst/mcb_ui_top_inst/mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL*" TIG;
# PIN "i_pcileech_out_buffer_ram/i_mig/memc3_infrastructure_inst/U_BUFG_CLK0.O" CLOCK_DEDICATED_ROUTE = FALSE; // MUST BE HERE FOR IT TO COMPILE...
# NET "i_pcileech_out_buffer_ram/i_mig/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK3";
# TIMESPEC "TS_SYS_CLK3" = PERIOD "SYS_CLK3" 5 ns HIGH 50 %; // SP605 200MHz
# NET "mcb3_dram_dq[*]" IN_TERM = UNTUNED_SPLIT_50;
# NET "mcb3_dram_dqs" IN_TERM = UNTUNED_SPLIT_50;
# NET "mcb3_dram_dqs_n" IN_TERM = UNTUNED_SPLIT_50;
# NET "mcb3_dram_udqs" IN_TERM = UNTUNED_SPLIT_50;
# NET "mcb3_dram_udqs_n" IN_TERM = UNTUNED_SPLIT_50;
# NET "mcb3_dram_dq[*]" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_a[*]" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_ba[*]" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_dqs" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_udqs" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_dqs_n" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_udqs_n" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_ck" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_ck_n" IOSTANDARD = DIFF_SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_cke" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_ras_n" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_cas_n" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_we_n" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_odt" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_reset_n" IOSTANDARD = LVCMOS15;
# NET "mcb3_dram_dm" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_dram_udm" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_rzq" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "mcb3_zio" IOSTANDARD = SSTL15_II | OUT_TERM = UNTUNED_50;
# NET "c3_sys_clk_p" IOSTANDARD = LVDS_25;
# NET "c3_sys_clk_n" IOSTANDARD = LVDS_25;
# NET "c3_sys_rst_i" IOSTANDARD = LVCMOS15;
# NET "mcb3_dram_a[0]" LOC = "K2";
# NET "mcb3_dram_a[10]" LOC = "J4";
# NET "mcb3_dram_a[11]" LOC = "E1";
# NET "mcb3_dram_a[12]" LOC = "F1";
# NET "mcb3_dram_a[1]" LOC = "K1";
# NET "mcb3_dram_a[2]" LOC = "K5";
# NET "mcb3_dram_a[3]" LOC = "M6";
# NET "mcb3_dram_a[4]" LOC = "H3";
# NET "mcb3_dram_a[5]" LOC = "M3";
# NET "mcb3_dram_a[6]" LOC = "L4";
# NET "mcb3_dram_a[7]" LOC = "K6";
# NET "mcb3_dram_a[8]" LOC = "G3";
# NET "mcb3_dram_a[9]" LOC = "G1";
# NET "mcb3_dram_ba[0]" LOC = "J3";
# NET "mcb3_dram_ba[1]" LOC = "J1";
# NET "mcb3_dram_ba[2]" LOC = "H1";
# NET "mcb3_dram_cas_n" LOC = "M4";
# NET "mcb3_dram_ck" LOC = "K4";
# NET "mcb3_dram_ck_n" LOC = "K3";
# NET "mcb3_dram_cke" LOC = "F2";
# NET "mcb3_dram_dm" LOC = "N4";
# NET "mcb3_dram_dq[0]" LOC = "R3";
# NET "mcb3_dram_dq[10]" LOC = "U3";
# NET "mcb3_dram_dq[11]" LOC = "U1";
# NET "mcb3_dram_dq[12]" LOC = "W3";
# NET "mcb3_dram_dq[13]" LOC = "W1";
# NET "mcb3_dram_dq[14]" LOC = "Y2";
# NET "mcb3_dram_dq[15]" LOC = "Y1";
# NET "mcb3_dram_dq[1]" LOC = "R1";
# NET "mcb3_dram_dq[2]" LOC = "P2";
# NET "mcb3_dram_dq[3]" LOC = "P1";
# NET "mcb3_dram_dq[4]" LOC = "L3";
# NET "mcb3_dram_dq[5]" LOC = "L1";
# NET "mcb3_dram_dq[6]" LOC = "M2";
# NET "mcb3_dram_dq[7]" LOC = "M1";
# NET "mcb3_dram_dq[8]" LOC = "T2";
# NET "mcb3_dram_dq[9]" LOC = "T1";
# NET "mcb3_dram_dqs" LOC = "N3";
# NET "mcb3_dram_dqs_n" LOC = "N1";
# NET "mcb3_dram_odt" LOC = "L6";
# NET "mcb3_dram_ras_n" LOC = "M5";
# NET "mcb3_dram_reset_n" LOC = "E3";
# NET "c3_sys_clk_n" LOC = "K22"; ## SP605 200MHz LVDS Clock
# NET "c3_sys_clk_p" LOC = "K21"; ## SP605 200MHz LVDS Clock
# NET "c3_sys_rst_i" LOC = "H8"; ## SP605 CPU_RESET pushbutton switch
# NET "mcb3_dram_udm" LOC = "P3";
# NET "mcb3_dram_udqs" LOC = "V2";
# NET "mcb3_dram_udqs_n" LOC = "V1";
# NET "mcb3_dram_we_n" LOC = "H2";
# NET "mcb3_rzq" LOC = "K7";
# NET "mcb3_zio" LOC = "M7";