From 50c97757dd78b7d21ef8a6d3b66d5a7270e9d3d9 Mon Sep 17 00:00:00 2001
From: Glen Wienecke <glen.wienecke@nxp.com>
Date: Tue, 23 Jan 2024 15:36:43 -0600
Subject: [PATCH] SM-73:  Implement PLL lock timeouts and PLL power up delays.

Signed-off-by: Glen Wienecke <glen.wienecke@nxp.com>
---
 devices/MIMX9/drivers/fsl_fract_pll.c | 45 ++++++++++++++++++++-------
 devices/MIMX95/MIMX95_elec_spec.h     |  4 +++
 2 files changed, 37 insertions(+), 12 deletions(-)

diff --git a/devices/MIMX9/drivers/fsl_fract_pll.c b/devices/MIMX9/drivers/fsl_fract_pll.c
index dd9990b..e255ef1 100755
--- a/devices/MIMX9/drivers/fsl_fract_pll.c
+++ b/devices/MIMX9/drivers/fsl_fract_pll.c
@@ -86,6 +86,9 @@ bool FRACTPLL_SetEnable(uint32_t pllIdx, uint32_t enMask, bool enable)
             {
                 uint32_t pllNum = pll->NUMERATOR.RW;
                 pll->NUMERATOR.RW = pllNum;
+
+                /* Wait before POWERUP */
+                SystemTimeDelay(ES_MAX_USEC_PLL_PREP);
             }
 #endif
             pll->CTRL.SET = enMask;
@@ -93,16 +96,24 @@ bool FRACTPLL_SetEnable(uint32_t pllIdx, uint32_t enMask, bool enable)
             /* If powering up, wait for lock */
             if ((enMask & PLL_CTRL_POWERUP_MASK) != 0U)
             {
-                while ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0U)
+                uint32_t pllLockUsec = 0U;
+                while (((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0U) &&
+                    (pllLockUsec < ES_MAX_USEC_PLL_LOCK))
                 {
-                    ; /* Intentional empty default */
+                    SystemTimeDelay(1U);
+                    pllLockUsec++;
                 }
             }
 
-            /* If enabling PLL output, disable bypass */
-            if ((enMask & PLL_CTRL_CLKMUX_EN_MASK) != 0U)
+            if ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) != 0U)
             {
-                pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK;
+                /* If enabling PLL output, disable bypass */
+                if ((enMask & PLL_CTRL_CLKMUX_EN_MASK) != 0U)
+                {
+                    pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK;
+                }
+
+                enableUpdate = true;
             }
         }
         else
@@ -113,9 +124,10 @@ bool FRACTPLL_SetEnable(uint32_t pllIdx, uint32_t enMask, bool enable)
                 pll->CTRL.SET = PLL_CTRL_CLKMUX_BYPASS_MASK;
             }
             pll->CTRL.CLR = enMask;
+
+            enableUpdate = true;
         }
 
-        enableUpdate = true;
     }
 
     return enableUpdate;
@@ -216,18 +228,27 @@ bool FRACTPLL_UpdateRate(uint32_t pllIdx, uint32_t mfi, uint32_t mfn,
             pll->DENOMINATOR.RW = PLL_DENOMINATOR_MFD(CLOCK_PLL_MFD);
         }
 
+        /* Wait before POWERUP */
+        SystemTimeDelay(ES_MAX_USEC_PLL_PREP);
+
         /* Power up for locking */
         pll->CTRL.SET = PLL_CTRL_POWERUP_MASK;
-        while ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0U)
+        uint32_t pllLockUsec = 0U;
+        while (((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) == 0U) &&
+            (pllLockUsec < ES_MAX_USEC_PLL_LOCK))
         {
-            ; /* Intentional empty default */
+            SystemTimeDelay(1U);
+            pllLockUsec++;
         }
 
-        /* Enable PLL and clean bypass*/
-        pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK;
-        pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK;
+        if ((pll->PLL_STATUS & PLL_PLL_STATUS_PLL_LOCK_MASK) != 0U)
+        {
+            /* Enable PLL and clean bypass*/
+            pll->CTRL.SET = PLL_CTRL_CLKMUX_EN_MASK;
+            pll->CTRL.CLR = PLL_CTRL_CLKMUX_BYPASS_MASK;
 
-        updateRate = true;
+            updateRate = true;
+        }
     }
 
     return updateRate;
diff --git a/devices/MIMX95/MIMX95_elec_spec.h b/devices/MIMX95/MIMX95_elec_spec.h
index 5977fe5..8b9c0b6 100755
--- a/devices/MIMX95/MIMX95_elec_spec.h
+++ b/devices/MIMX95/MIMX95_elec_spec.h
@@ -175,6 +175,10 @@
 #define ES_NOM_KHZ_DISP             ES_666667KHZ
 #define ES_ODV_KHZ_DISP             ES_800000KHZ
 
+/* PLL time limits */
+#define ES_MAX_USEC_PLL_LOCK        100U
+#define ES_MAX_USEC_PLL_PREP        5U
+
 /* PLL frequency limits */
 #define ES_MIN_HZ_PLLVCO            2520000000ULL   /* 2.5GHz rounded to 24M */
 #define ES_MAX_HZ_PLLVCO            4992000000ULL   /* 5.0GHz rounded to 24M */