Verilator 5 Released

[wsnyder]

Verilator 5.002 2022-10-29

Major:

• This is a major new release.
• Require C++20 for the new --timing features. Upgrading to a C++20 or newer compiler is strongly recommended.
• Support the Active and NBA scheduling regions as defined by the SystemVerilog standard (IEEE 1800-2017 chapter 4). This means all generated clocks are now simulated correctly (Redesign of scheduling (fixing generated clocks) verilator#3278, IEEE compliant static scheduler verilator#3384). [Geza Lore, Shunyao CAD]
• Support timing controls (delays, event controls in any location, wait statements) and forks. [Krzysztof Bieganski, Antmicro Ltd]
  This may require adding --timing or --no-timing. See docs for details.
• Introduce a new combinational logic optimizer (DFG), that can yield significant performance improvements on some designs. [Geza Lore, Shunyao CAD]
• Add --binary option as alias of --main --exe --build --timing (Support option for simpler building of executables verilator#3625).
  For designs where C++ was only used to make a simple no-I/O testbench, we recommend abandoning that C++, and instead letting Verilator build it with --binary (or --main).

Minor:

• Split UNUSED warning into genvar, param, and signal warnings (Split unused genvar, param, and signal warnings verilator#3607). [Topa Topino]
• Support standalone 'this' in classes (FIx standalone use of "this" verilator#2594) (Standalone reference to 'this' is marked as a symbol-resolution error verilator#3248) (Support standalone 'this' in classes verilator#3675). [Arkadiusz Kozdra, Antmicro Ltd]
• Support tristate select/extend (Add handling of new tristate node types in visitCaseEq verilator#3604). [Ryszard Rozak, Antmicro Ltd>
• Support linting for top module interfaces (Support linting for top module interfaces verilator#3635). [Kanad Kanhere]
• Support virtual interfaces (Virtual interfaces support verilator#3654). [Arkadiusz Kozdra, Antmicro Ltd]
• Support class type params without defaults (Support class type params without defaults verilator#3693). [Krzysztof Bieganski, Antmicro Ltd]
• Support empty generate_regions (Naked begin/end block in module verilator#3695). [mpb27]
• Support access to constructs inside type parameters (Enable access to constructs inside type parameters verilator#3702). [Arkadiusz Kozdra, Antmicro Ltd]
• Add --dump-tree-dot to enable dumping Ast Tree .dot files (Ast Tree Visualization, --dump-tree-dot to enable dumping Ast Tree .dot files verilator#3636). [Marcel Chang]
• Add --get-supported to determine what features are in Verilator.
• Add error on real edge event control.
• Fix false LATCH warning on 'unique if' (unique annotation on if generates WARNING-LATCH  verilator#3088). [Rachit Nigam]
• Fix cell assigning integer array parameters (Internal error when assigning integer array parameter verilator#3299). [Michael Platzer]
• Fix LSB error on --hierarchical submodules (lib-create creates verilog DPI wrapper with non-matching ports (ignores LSB index) verilator#3539). [danbone]
• Fix $display of fixed-width numbers (print formatting of hex numbers, width does not match other simulators verilator#3565). [Iztok Jeras]
• Fix foreach and pre/post increment in functions (Compilation error - foreach on map inside a task verilator#3613). [Nandu Raj]
• Fix linker errors in user-facing timing functions (Always emit user-facing timing functions verilator#3657). [Krzysztof Bieganski, Antmicro Ltd]
• Fix null access on optimized-out fork statements (Fix null access on optimized-out fork statements verilator#3658). [Krzysztof Bieganski, Antmicro Ltd]
• Fix VPI inline module naming mismatch (Using VPI occasionally produces scope name with extra __PVT__ in the middle verilator#3690) (use shortName to fix VPI inline module naming mismatch verilator#3694). [Jiuyang Liu]
• Fix deadlock in timeprecision when using systemC (Fix deadlock in timeprecision when using systemC verilator#3707). [Kamil Rakoczy, Antmicro Ltd]
• Fix width mismatch on inside operator (Internal Error: V3DfgPeephole.cpp:843: Mismatched RHS width verilator#3714). [Alex Torregrosa]