diff --git a/crates/emitter/src/emitter.rs b/crates/emitter/src/emitter.rs index a25c2e5b..261ae4d2 100644 --- a/crates/emitter/src/emitter.rs +++ b/crates/emitter/src/emitter.rs @@ -920,6 +920,8 @@ impl Emitter { .iter() .any(|y| x.name() == y.identifier.identifier_token.token.text) }); + + let src_line = self.src_line; for (i, port) in unconnected_ports.enumerate() { if i >= 1 || !connected_ports.is_empty() { self.str(","); @@ -928,8 +930,10 @@ impl Emitter { let property = port.property(); self.str("."); + self.clear_adjust_line(); self.align_start(align_kind::IDENTIFIER); - self.token(&port.token); + self.align_duplicated_token(align_kind::IDENTIFIER, &port.token, 0); + self.duplicated_token(&port.token, 0); self.align_finish(align_kind::IDENTIFIER); self.space(1); self.str("("); @@ -939,6 +943,7 @@ impl Emitter { self.str(")"); } + self.src_line = src_line; self.generic_map.pop(); } diff --git a/testcases/map/testcases/sv/73_port_default_value.sv.map b/testcases/map/testcases/sv/73_port_default_value.sv.map index f775631e..cc855d60 100644 --- a/testcases/map/testcases/sv/73_port_default_value.sv.map +++ b/testcases/map/testcases/sv/73_port_default_value.sv.map @@ -1 +1 @@ -{"version":3,"file":"73_port_default_value.sv.map","sources":["../../../veryl/73_port_default_value.veryl"],"names":["","package","Package73",";","localparam","bit","A","=","0","endpackage","module","(","input","logic","i_a",",","i_b","i_c","output","o_d",")","always_comb","endmodule","Module73B","veryl_testcase___Module73A__0","u0","veryl_testcase_Package73::A","veryl_testcase___Module73A__1","u1","1","u2"],"mappings":"AAAAA,AAAAC,uBAAQC,SAAUC;IACdC,WAASC,IAAHC,EAAOC,EAAEC,CAACL;AACpBM;;AAEAC,qCAA6BC;IACpBC,OAAOC,MAAZC,GAAgCC;IAC3BH,OAAOC,MAAZG,GAAgCD;IAC3BH,OAAOC,MAAZI,GAAgCF;IAC3BG,OAAOL,MAAZM,GAAgCnB;AACpCoB,CAAEjB;IACEkB,YAAOF,IAAIZ,EAAEC,CAACL;AAClBmB;AAPAZ,qCAA6BC;IACpBC,OAAOC,MAAZC,GAAgCC;IAC3BH,OAAOC,MAAZG,GAAgCD;IAC3BH,OAAOC,MAAZI,GAAgCF;IAC3BG,OAAOL,MAAZM,GAAgCnB;AACpCoB,CAAEjB;IACEkB,YAAOF,IAAIZ,EAAEC,CAACL;AAClBmB;;AAEAZ,sBAAOa,SAAUpB;IACbH,AAASwB,8BAAJC;SATLX,KAAoBY;SACpBV,KAAoBR;SACpBS,KAAoBT;SACpBW,KAAoBnB;;IAMGG;IACvBH,AAAS2B,8BAAJC;SAVLd,KAAoBY;SACpBV,KAAoBa;SACpBZ,KAAoBT;SACpBW,KAAoBnB;;IAOGG;IACvBH,AAAS2B,8BAAJG,GAAmBnB;SACpBG,KAAGd,AAAEQ,EAACO;SACNC,KAAGhB,AAAEQ,EAACR;SAXViB,KAAoBT;SACpBW,KAAoBnB;;IAWpBoB,CAACjB;AACLmB"} \ No newline at end of file +{"version":3,"file":"73_port_default_value.sv.map","sources":["../../../veryl/73_port_default_value.veryl"],"names":["","package","Package73",";","localparam","bit","A","=","0","endpackage","module","(","input","logic","i_a",",","i_b","i_c","output","o_d","o_e",")","always_comb","endmodule","Module73B","_d","veryl_testcase___Module73A__0","u0","veryl_testcase_Package73::A","veryl_testcase___Module73A__1","u1","1","u2"],"mappings":"AAAAA,AAAAC,uBAAQC,SAAUC;IACdC,WAASC,IAAHC,EAAOC,EAAEC,CAACL;AACpBM;;AAEAC,qCAA6BC;IACpBC,OAAOC,MAAZC,GAAgCC;IAC3BH,OAAOC,MAAZG,GAAgCD;IAC3BH,OAAOC,MAAZI,GAAgCF;IAC3BG,OAAOL,MAAZM,GAAgCJ;IAC3BG,OAAOL,MAAZO,GAAgCpB;AACpCqB,CAAElB;IACEmB,YAAOH,IAAIZ,EAAEC,CAACL;IACdmB,YAAOF,IAAIb,EAAEC,CAACL;AAClBoB;AATAb,qCAA6BC;IACpBC,OAAOC,MAAZC,GAAgCC;IAC3BH,OAAOC,MAAZG,GAAgCD;IAC3BH,OAAOC,MAAZI,GAAgCF;IAC3BG,OAAOL,MAAZM,GAAgCJ;IAC3BG,OAAOL,MAAZO,GAAgCpB;AACpCqB,CAAElB;IACEmB,YAAOH,IAAIZ,EAAEC,CAACL;IACdmB,YAAOF,IAAIb,EAAEC,CAACL;AAClBoB;;AAEAb,sBAAOc,SAAUrB;IACLU,MAAJY,EAAStB;;IAEbH,AAAS0B,8BAAJC;SAbLb,KAAoBc;SACpBZ,KAAoBR;SACpBS,KAAoBT;SACpBW,KAAoBnB;SACpBoB,KAAoBpB;KASGG;IACvBH,AAAS6B,8BAAJC;SAdLhB,KAAoBc;SACpBZ,KAAoBe;SACpBd,KAAoBT;SACpBW,KAAoBnB;SACpBoB,KAAoBpB;KAUGG;IACvBH,AAAS6B,8BAAJG,GAAmBrB;SACpBG,KAAGd,AAAEQ,GAAEO;SACPC,KAAGhB,AAAEQ,GAAEO;SACPI,KAAGnB,AAAEyB,GAAEzB;SAhBXiB,KAAoBT;SAEpBY,KAAoBpB;IAepBqB,CAAClB;AACLoB"} \ No newline at end of file diff --git a/testcases/sv/73_port_default_value.sv b/testcases/sv/73_port_default_value.sv index 46cbc7eb..c375e359 100644 --- a/testcases/sv/73_port_default_value.sv +++ b/testcases/sv/73_port_default_value.sv @@ -6,40 +6,46 @@ module veryl_testcase___Module73A__0 ( input logic i_a, input logic i_b, input logic i_c, - output logic o_d + output logic o_d, + output logic o_e ); always_comb o_d = 0; + always_comb o_e = 0; endmodule module veryl_testcase___Module73A__1 ( input logic i_a, input logic i_b, input logic i_c, - output logic o_d + output logic o_d, + output logic o_e ); always_comb o_d = 0; + always_comb o_e = 0; endmodule module veryl_testcase_Module73B; + logic _d; + veryl_testcase___Module73A__0 u0 ( .i_a (veryl_testcase_Package73::A), .i_b (0 ), .i_c (0), - .o_d ( ) - ) - ; + .o_d ( ), + .o_e () + ); veryl_testcase___Module73A__1 u1 ( .i_a (veryl_testcase_Package73::A), .i_b (1 ), .i_c (0), - .o_d ( ) - ) - ; + .o_d ( ), + .o_e () + ); veryl_testcase___Module73A__1 u2 ( - .i_a (0), - .i_b (0), + .i_a (0 ), + .i_b (0 ), + .o_d (_d), .i_c (0), - .o_d ( ) - + .o_e () ); endmodule //# sourceMappingURL=../map/testcases/sv/73_port_default_value.sv.map diff --git a/testcases/veryl/73_port_default_value.veryl b/testcases/veryl/73_port_default_value.veryl index 1eba03f0..e6ae7658 100644 --- a/testcases/veryl/73_port_default_value.veryl +++ b/testcases/veryl/73_port_default_value.veryl @@ -7,15 +7,20 @@ module Module73A:: ( i_b: input logic = B , i_c: input logic = 0 , o_d: output logic = _ , + o_e: output logic = _ , ) { assign o_d = 0; + assign o_e = 0; } module Module73B { + var _d: logic; + inst u0: Module73A::<0>; inst u1: Module73A::<1>; inst u2: Module73A::<1> ( - i_a: 0, - i_b: 0, + i_a: 0 , + i_b: 0 , + o_d: _d, ); }