From 10875af005581d2f51d2c0ef91c642644f0ab85b Mon Sep 17 00:00:00 2001
From: wxue1 <xue1.wang@intel.com>
Date: Sun, 10 Jul 2022 19:17:28 -0700
Subject: [PATCH] Add new instruction ENDBR64 and ENDBR32

Intel IBT requires the target of any indirect CALL or JMP instruction
to be the ENDBR instruction;

Besides, fix the collision of /sse and /mod type when build.

Signed-off-by: Wang, Xue xue1.wang@intel.com
---
 docs/x86/optable.xml | 14 ++++++++++++++
 scripts/ud_opcode.py |  2 +-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/docs/x86/optable.xml b/docs/x86/optable.xml
index 3bda858..9c3ff67 100644
--- a/docs/x86/optable.xml
+++ b/docs/x86/optable.xml
@@ -1298,6 +1298,20 @@
         </def>
     </instruction>
 
+    <instruction>
+        <mnemonic>endbr64</mnemonic>
+        <def>
+            <opc>/sse=f3 0f 1e /mod=11 /reg=7 /rm=2 /m=64</opc>
+        </def>
+    </instruction>
+
+    <instruction>
+        <mnemonic>endbr32</mnemonic>
+        <def>
+            <opc>/sse=f3 0f 1e /mod=11 /reg=7 /rm=3 /m=32</opc>
+        </def>
+    </instruction>
+
     <instruction>
         <mnemonic>enter</mnemonic>
         <def>
diff --git a/scripts/ud_opcode.py b/scripts/ud_opcode.py
index fe1833d..6753f6d 100644
--- a/scripts/ud_opcode.py
+++ b/scripts/ud_opcode.py
@@ -387,7 +387,7 @@ def addInsn(self, **insnDef):
         # well the opcode table is packed. Also note, /sse must be
         # before /o, because /sse may consume operand size prefix
         # affect the outcome of /o.
-        for ext in ('/mod', '/x87', '/reg', '/rm', '/sse', '/o', '/a', '/m',
+        for ext in ('/sse', '/mod', '/x87', '/reg', '/rm', '/o', '/a', '/m',
                     '/vexw', '/vexl', '/3dnow', '/vendor'):
             if ext in opcexts:
                 opcodes.append(ext + '=' + opcexts[ext])