Refer design description, which consists of a description of the Efabless MPW shuttle design list currently in the CI. This list have MPW shuttle based designs details with following order:
CI Design NameProject Name:Project Owner:Project Number:Description:Executable CI Script:
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Actuator_Controller- Project Name: ActuatorController
- Project Owner: Josh Stevens
- Project Number: 765
- Description: This design is to precisely control the timing sequence of 10 micro-motors. The SPI interface allows a microcontroller to pass the required commands to adjust the firing order and width of the PWM pulses.
- Executable CI Script: AC_actuator_driver_controller | AC_cells_controller | AC_memory_controler | AC_spi_mod | AC_top
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alu_xor- Project Name: ALU
- Project Owner: Janani Aravind
- Project Number: 763
- Description: The ALU_XOR design implemented uses two copies of ALUs, one being the golden reference, and compares the output for any differences. This project aims to analyze the faults injected in real-time to identify the location/bits that have any impacts.
- Executable CI Script: alu_xor | alu_xor_wrapper
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APPROX_MULT- Project Name: APPROXIMATE Multiplier
- Project Owner: Rana Muhammad
- Project Number: 664
- Description: Approximate Image Processing is a field of research being explored to meet the computing demands with less resources while sacrificing some of the accuracy. Image processing is one such application where the accuracy can be dropped for increased performance in terms of power, time etc.
- Executable CI Script: APPROX_MULT
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acor_dct32- Project Name: Adaptive CORDIC-based 32-point DCT
- Project Owner: Lêc Hùng
- Project Number: 1060
- Description: We make implementation of a flexible 32-point Discrete Cosine Transform (DCT). The architecture is based on the fixed-rotation adaptive COordinate Rotation DIgital Computer (CORDIC) algorithm.
- Executable CI Script: acor_dct32
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asicle- Project Name: Asicle
- Project Owner: Tamas Hubai
- Project Number: 788
- Description: Okay, so Wordle took the net by storm and was ported to a myriad of platforms including retro computers and microcontrollers with tight constraints. But have you played it on raw silicon yet?
- Executable CI Script: asicle
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ASU_GP22 -
async_fib2- Project Name: Asynchronous Fibonacci counter
- Project Owner: Gal Nadrag
- Project Number: 808
- Description: The counter uses two phase dual rail logic. An asynchronous sequential logic circuit does not rely on the assumption that logic values only need to be valid within a window around the clock edge. Instead, the circuit needs to be valid all the time.
- Executable CI Script: async_fib2
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axi_dma_wrapper- Project Name: AXI DMA using Spinal HDL
- Project Owner: Pu Wang
- Project Number: 175
- Description: This is a DMA controller with AMBA AXI4 interface. This DMA controller is part of an ongoing effort to build an SoC with the state-of-art open source hardware development kits, such as Spinal HDL and cocotb.
- Executable CI Script: axi_dma_wrapper
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azadi_soc- Project Name: azadi_soc_ibex
- Project Owner: Zeeshan Rafique
- Project Number: 218
- Description: Azadi is an SoC with a 32-bit RISC-V signal core extended version of ibex we named it "buraq", it is a 3-stage pipeline core that implements the RV32IMF instruction set architecture, a limited number of peripherals UART, SPI, GPIO, PWM, and timer.
- Executable CI Script: azadi_soc
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azadi_soc_iii- Project Name: Azadi_III
- Project Owner: Rameen Anwar
- Project Number: 755
- Description: The Azadi-III includes the following peripherals. PWM 2-Channel, OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART QSPI SPI GPIOs Design Goals: Azadi-III is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices.
- Executable CI Script: azadi_soc_iii
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azadi_soc_iii_dft- Project Name: Azadi_DFT
- Project Owner: Rameen Anwar
- Project Number: 845
- Description: The Azadi-III includes the following peripherals. PWM 2-Channel, OpenRAM 1KB x 4 for ICCM 1KB x 4 for DCCM Ibex core(named as brq_core) FPU (single-precision) TileLink (UL) UART QSPI SPI GPIOs Design Goals: Azadi-III is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices.
- Executable CI Script: azadi_soc_iii_dft
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bitcoin_asic- Project Name: Bitcoin Mining Asic
- Project Owner: Constantine Mantas
- Project Number: 1318
- Description: This ASIC takes as an input the header of a Blockchain and simulates the bitcoin mining process.
- Executable CI Script: bc_sha1_top | btc_miner_top
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caravel_dsp- Project Name: caravel_dsp2
- Project Owner: Jayakumar Janarthanam
- Project Number: 180
- Description: DSP Functions
- Executable CI Script: caravel_dsp
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caravel_freqdiv- Project Name: iiitb_freqdiv
- Project Owner: Dantu Nandini Devi
- Project Number: 1299
- Description: This is a model of a Freqency Divider. This model will contain a 4 bit number lines to select by which factor does the input frequency has to be divided.
- Executable CI Script: caravel_freqdiv
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caravel_NNgen- Project Name: Tensor Calculation using NNgen
- Project Owner: Yinghao REN
- Project Number: 1077
- Description: This Project use NNgen(A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network) to generate a simple circuit.
- Executable CI Script: caravel_NNgen
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caravel_PISO- Project Name: iiitb_piso
- Project Owner: Mahati Basavaraju
- Project Number: 1298
- Description: 4-bit Parallel In Serial Out Shift Register
- Executable CI Script: caravel_PISO
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caravel_r2_4bit_bm- Project Name: Radix-2 4-bit Booths Multiplier
- Project Owner: Yashwant Moses
- Project Number: 1314
- Description: Booth's Multiplier is based on Booth's Multiplication Algorithm. It proposes an efficient way for multiplying two signed integers in there 2's complement form such that the number of partial products is reduced which ultimately lead to the reduction of number of addition operation required for generating the final result.
- Executable CI Script: caravel_r2_4bit_bm
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caravel_rtc- Project Name: iiitb_rtc
- Project Owner: BANDA ANUSHA
- Project Number: 1300
- Description: Real-Time Clock
- Executable CI Script: caravel_rtc
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caravel_rv32i- Project Name: iiitb_rv32i
- Project Owner: Vinay Rayapati
- Project Number: 1301
- Description: This project provides an insight into the working of a few important instructions of the instruction set of a Single cycle Reduced Instruction Set Computer - Five(RISC-V) Instruction Set Architecture suitable for use across wide-spectrum of Applications from low power embedded devices to high performance Cloud based Server processors.
- Executable CI Script: caravel_rv32i
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caravel_soc_now- Project Name: SoC_Now
- Project Owner: Usman Zain Ul Abedin
- Project Number: 1003
- Description: This SoC is generated by the SoC Now Generator which is the final year project of undergraduate students. It is written in Chisel.
- Executable CI Script: caravel_soc_now
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ChirstmasTreeController- Project Name: ChristmasTreeController
- Project Owner: Julien OURY
- Project Number: 746
- Description: A Christmas tree controller that include : Infrared receiver (protocol NEC), StepMotor controller (full-step, half-step, with strenght control), Led string controller (compatibles WS2812B), Pseudo-random generator (32bits)
- Executable CI Script: ChirstmasTreeController
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counter_alperen- Project Name: Alperens SOC
- Project Owner: Alperen Bolat
- Project Number: 114
- Description: Custom Risc V processor design
- Executable CI Script: counter_alperen
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counter_azadi- Project Name: Azadi_II
- Project Owner: Wajeh
- Project Number: 576
- Description: Azadi-II is aimed to extend the base ibex core(RV32IMC) with a fully functional single precision floating point unit and RISCV compliant debug module for on chip debugging and some standard peripherals for communicating with other devices. all these modules will be interlinked using standard Tilelink Bus protocol.
- Executable CI Script: counter_azadi
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counter_mpw4_mv- Project Name: Zero to ASIC Course MPW-2 re-run
- Project Owner: Matt Venn
- Project Number: 585
- Description: Re-hardened MPW2 group submission to fix clock issues and re-submit for MPW4.
- Executable CI Script: counter_mpw4_mv
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counter_mpw4_mv- Project Name: Zero to ASIC MPW4 rerun on MPW5
- Project Owner: Matt Venn
- Project Number: 753
- Description: Zero to ASIC MPW4 rerun on MPW5
- Executable CI Script: counter_mpw4_mv
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counter_eeuet- Project Name: Caravel-Sermo
- Project Owner: Tayyeb Mahmood
- Project Number: 116
- Description: The project implements a PID controller using encoder feedback and single channel of PWM output and is capable of driving a DC motor. The module configuration and data registers are accessible through Wishbone slave interface.
- Executable CI Script: counter_eeuet
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counter_efab- Project Name: Efabless processor
- Project Owner: Andrew Feldman
- Project Number: 427
- Description: Basic design to familiarize with this service
- Executable CI Script: counter_efab
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counter_hhj- Project Name: Caravel
- Project Owner: Lena Hwang
- Project Number: 515
- Description: A template SoC for Google sponsored Open MPW shuttles for SKY130
- Executable CI Script: counter_hhj
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counter_ICESOC- Project Name: ICESOC
- Project Owner: Nguyen Dao
- Project Number: 625
- Description: Ibex Crypto eFPGA SoC
- Executable CI Script: counter_ICESOC
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counter_mpw4_mv- Project Name: Zero to ASIC Course MPW-2 re-run
- Project Owner: Matt Venn
- Project Number: 585
- Description: Re-hardened MPW2 group submission to fix clock issues and re-submit for MPW4.
- Executable CI Script: counter_mpw4_mv
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counter_REST- Project Name: REST
- Project Owner: Sajjad Ahmed
- Project Number: 591
- Description: REST(Resource efficient SRAM based TCAM) is a test project for experimenting with SRAM based TCAMs in ASIC.
- Executable CI Script: counter_REST
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counter_REST- Project Name: REST_II
- Project Owner: Sajjad Ahmed
- Project Number: 798
- Description: REST(Resource efficient SRAM based TCAM) is a test project for experimenting with SRAM based TCAMs in ASIC.
- Executable CI Script: counter_REST
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counter_rgb- Project Name: Zero to ASIC group submission MPW3
- Project Owner: Matt Venn
- Project Number: 392
- Description: MPW3 submission
- Executable CI Script: counter_rgb
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counter_TestSOC- Project Name: Test project
- Project Owner: Andrej Čižmárik
- Project Number: 733
- Description: Test project
- Executable CI Script: counter_TestSOC
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counter_vsdsram- Project Name: VSD SRAM
- Project Owner: Shon Taware
- Project Number: 424
- Description: Aims at design of a SRAM cell array with a configuration of 1.8 V operating voltage and access time less than 2.5ns using Google SkyWater SKY130 PDKs and OpenRAM memory compiler.
- Executable CI Script: counter_vsdsram
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crypto_accelerator- Project Name: Crypto Accelerator v2
- Project Owner: Anish Singhani
- Project Number: 456
- Description: This is a cryptography accelerator ASIC designed using the SKY130 process node. It includes key-limited hardware implementations of cores for AES128/AES256 and SHA256, as well as an experimental VGA-based game demo. The eventual goal of this project is to use it for embedded/IoT security applications.
- Executable CI Script: accelerator_top
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crypto_aes128- Project Name: crypto_aes128
- Project Owner: Uriel Jaramillo Toral
- Project Number: 1291
- Description: AES128 project test
- Executable CI Script: crypto_aes128
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Elpis_Light- Project Name: Elpis Light processor
- Project Owner: Aurora Tomás
- Project Number: 468
- Description: This project is a light version of the Elpis core, which is a 5-stage pipelined and multi-cycle in-order processor based on RISC-V architecture, mixed with some MIPS ideas.
- Executable CI Script: Elpis_chip_controller | Elpis_core | Elpis_custom_sram
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ExperiarSoC- Project Name: Experiar SoC
- Project Owner: Wevel
- Project Number: 1001
- Description: Experiar SoC is a dual RV32I core processor with peripherals including PWM, SPI, UART, and VGA.
- Executable CI Script: ExpSoc_CaravelHost | ExpSoc_Flash | ExpSoc_Peripherals_Flat | ExperiarCore | ExpSoc_Video | ExpSoc_WishboneInterconnect
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eFPGA_v3_wrapper- Project Name: FABulous_Sky
- Project Owner: Nguyen Dao
- Project Number: 202
- Description: Demonstration of the Fabulous FPGA design flow using the Skywater 130 process. The design flow includes the specification of the routing fabric, individual tiles, and the exact fabric description.
- Executable CI Script: eFPGA_v3_wrapper
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FCNet_neuron- Project Name: pre-trained neural network for MNIST
- Project Owner: mxiangyue
- Project Number: 486
- Description: This project implements a pre-trained neural network for hand-written digits from MNIST dataset.
- Executable CI Script: FCNet_neuron
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Fixed2Float- Project Name: Fixed2Float_Converter
- Project Owner: Dhayalakumar Maruthamuthu
- Project Number: 455
- Description: This project is implementation for conversion of 19bit fixed point number to single precision IEEE floating point number.
- Executable CI Script: Fixed2Float
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FMAC- Project Name: Factored MAC for Systolic Array Architectures
- Project Owner: KASHIF INAYAT
- Project Number: 794
- Description: This is a factored MAC, in which we have designed the factored Radix-8 Booth Multiplier (16 bits) and accumulation is performed with 32 bits carry propagation adder (CPA). A radix-8 booth multiplier involves the dedicated pre-processing of complex booth recording on multiplier X and 3y=Y+2Y generation on the multiplicand Y.
- Executable CI Script: FMAC | FMAC_wrapper
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FPU -
FPU_Bfloat_16- Project Name: Floating_Point_Unit_Bfloat16
- Project Owner: merl dsu
- Project Number: 993
- Description: This is the first ever Bfloat16 precision floating point unit designed by undergraduate students of DHA Suffa University Pakistan.
- Executable CI Script: FPU_Bfloat_16
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FPU_Single_Precision- Project Name: Floating_Point_Unit_Single_Precision
- Project Owner: merl dsu
- Project Number: 981
- Description: This is the first ever Single Precision Floating Point Unit of IEEE-754 standard. It support all the basic floating point instruction mention in RISC-V specs.
- Executable CI Script: FPU_Single_Precision
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FPU_half_precision- Project Name: Floating_Point_Unit_Half_Precision
- Project Owner: merl dsu
- Project Number: 847
- Description: This is the first ever Half Precision Floating Point Unit of IEEE-754 standard. It support all the basic floating point instruction mention in RISC-V specs.
- Executable CI Script: FPU_half_precision
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fct_iot_biquad- Project Name: digital biquad filter
- Project Owner: Tiago Silva
- Project Number: 1088
- Description: This project contains a 16bit digital biquad filter.
- Executable CI Script: fct_iot_biquad | [fct_iot_bqmain][../scripts/fct_iot_bqmain]
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biquad_mpw7- Project Name: Digital Biquad Filter - mpw7
- Project Owner: Tiago Silva
- Project Number: 1243
- Description: 12 bit data, 16 bit coefficients. Tested in FPGA.
- Executable CI Script: biquad_mpw7
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figaro -
figaro_mpw7- Project Name: RNG based on a Figaro Oscillator
- Project Owner: Kaya Demir
- Project Number: 1235
- Description: A random number generator that uses the chaotic signals from a figaro based ring oscillator to generate bits.
- Executable CI Script: figaro_mpw7
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fuserisc- Project Name: FuseRISC
- Project Owner: Andrew Attwood
- Project Number: 134
- Description: FuseRISC will demonstrate the benefits of the tight coupling of RISC-V cores and eFPGA fabric for tensorflow micro applications. Two RISC-V cores will have ALU that are integrated directly with a customised eFPGA fabric generated using the FABulous eFPGA framework.
- Executable CI Script: core_sram | wb_mem_split | eFPGA_CPU_TOP
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fossiAES -
Ghazi_DFT -
GpioCtrl -
GPS_Baseband- Project Name: PICO Design Resubmission MPW5
- Project Owner: Ramakrishna P.V.
- Project Number: 796
- Description: This project includes two different designs submitted as part of SSCS PICO-2021. The two designs are GPS Baseband Engine, Polysilicon Resistor based Temperature sensor.
- Executable CI Script: GPS_Baseband
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graphics_controller- Project Name: Graphics Controller
- Project Owner: Vijayan Krishnan
- Project Number: 1303
- Description: The openGFX430 is a synthesizable Graphic controller written in Verilog and tailored for the openMSP430 core.
- Executable CI Script: graphics_controller
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hack_soc_wrapper- Project Name: Hack SoC
- Project Owner: Maximo Balestrini
- Project Number: 791
- Description: Hardware implementation of the Hack Computer from the Nand to Tetris courses
- Executable CI Script: hack_soc_wrapper
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hp35_core -
IIC_AudioDAC- Project Name: delta-sigma audio DAC
- Project Owner: Harald Pretl
- Project Number: 736
- Description: As a classroom project at Johannes Kepler University, we are designing a delta-sigma audio DAC, with a maximized digital and minimized analog content. The specifications are 16b, 48kHz sample rate with direct drive of line-out or headphones (load impedance 16 to 600Ohm). The design supports 1st or 2nd-order delta-sigma, volume control, and a FIFO asynchronous interface to a host system.
- Executable CI Script: IIC_AudioDAC
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jacaranda8- Project Name: caravel_jacaranda-8
- Project Owner: Yuki Azuma
- Project Number: 413
- Description: Jacaranda-8 is educational ISA for home-build CPU beginners. This project implements the microarchitecture: CHARLATAN which is a simple implementation of Jacaranda-8 ISA.
- Executable CI Script: jacaranda8
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junga_soc -
junga_soc_mpw5- Project Name: junga_soc_mpw5
- Project Owner: Lena Hwang
- Project Number: 780
- Description: Simple vexriscv based SoC
- Executable CI Script: junga_soc_mpw5
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kasirga_k0- Project Name: Kasirga K0
- Project Owner: İsmail Emir Yüksel
- Project Number: 638
- Description: RISC-V SoC
- Executable CI Script: c0_system_macro
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keyvalue_caravel- Project Name: Key Value store
- Project Owner: Giray Pultar
- Project Number: 509
- Description: A key value store using a wishbone interface, developed using migen.
- Executable CI Script: keyvalue_caravel
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koggestone_adder- Project Name: caravel_koggestone_adder_project
- Project Owner: Mohammed Zakir Hussain
- Project Number: 640
- Description: 16-bit kogge-stone adder Verilog implementation.
- In computing, the Kogge–Stone adder is a parallel prefix form carry look-ahead adder.
- Executable CI Script: koggestone_adder
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ks-guitar -
ks-guitar-2s- Project Name: Karplus-Strong Guitar (two-strings)
- Project Owner: Tamas Hubai
- Project Number: 660
- Description: Two string version of Karplus-Strong Guitar
- Executable CI Script: ks-guitar-2s
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leros_chip- Project Name: Leros
- Project Owner: Martin Schoeberl
- Project Number: 1262
- Description: The open-source Leros processor.
- Executable CI Script: leros_chip
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logic_bist_mpw4 -
logic_bist- Project Name: LBIST-MBIST
- Project Owner: Dinesh Annaya
- Project Number: 771
- Description: Logic built-in self-test (or LBIST) is a form of built-in self-test (BIST) in which hardware and/or software is built into integrated circuits allowing them to test their own operation.
- Executable CI Script: LBIST_mbist_top1 | LBIST_mbist_top2
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mpw5_marmot_asic- Project Name: Power Monitoring Microcontroller ASIC MARMOT
- Project Owner: Shumpei Kawasaki
- Project Number: 759
- Description: An application specific RISC-V microcontroller, MARMOT, was developed from a total scratch to a GDS in exactly one month without prior knowledge of OpenLane digital design tool flow. MARMOT stands for a Microcontroller Autonomous Resistant to Malware, Obtrusions and Tampering. Its IPs were derived from the Rocket SoC generator and mated to the Sky130A Caravel Harness. A MARMOT ASIC design objective is to capture high-frequency sampling output of the analog-to-digital converter connected to the current sensor in power rails of IoT power supply.
- Executable CI Script: marmot_asic
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marmot_asic- Project Name: MARMOT RISC-V SOC
- Project Owner: Shumpei Kawasaki
- Project Number: 853
- Description: A RISC-V ASIC (CSP60), a part of security function, will be prototyped using Google's free shuttle. The GDS layout was completed in March, 2022. ber of the same year, the ASIC will be integrated into the logic board on the flexible board.
- Executable CI Script: marmot_asic
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marmot_asic_v2- Project Name: Marmot RISC-V ASIC large memory and Motor Control
- Project Owner: Shumpei Kawasaki
- Project Number: 1288
- Description: Increased features (plus 8KB D-Cache and 3ch PWM) and improved clocking (25MHz > 50MHz) by mastering tools since MPW-6 MARMOT RISC-V, three months ago.
- Executable CI Script: marmot_asic_v2
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mbist_ctrl- Project Name: MBIST Controller
- Project Owner: Dinesh Annaya
- Project Number: 422
- Description: MBIST is a self-testing and repair mechanism which tests the memories through an effective set of algorithms to detect possibly all the faults that could be present inside a typical memory cell whether it is stuck-at (SAF), transition delay faults (TDF), coupling (CF) or neighborhood pattern sensitive faults (NPSF).
- Executable CI Script: mbist1 | mbist2 | wb_host | wb_interconnect
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memory_array_8x64- Project Name: Memory array
- Project Owner: Binoy B
- Project Number: 1203
- Description: Implementation of an 8x64 memory array
- Executable CI Script: memory_array_8x64
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miranda_fpga- Project Name: Miranda FPGA MPW7
- Project Owner: Alexander Monakhov
- Project Number: 1184
- Description: MPW7 attempt to tapeout our Miranda FPGA. Fract. LUT added. Advanced clock tree resources are in progress.
- Executable CI Script: miranda_fpga
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mpw5_4ft4 -
mpw-5c-C0 -
mpw5_L1cache- Project Name: mpw5_cache
- Project Owner: Shivani Shah
- Project Number: 673
- Description: Integrated a smaller version of the 4-way set associative 256B L1 cache as user project area in caravel SoC.
- Executable CI Script: mpw5_L1cache
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mpw5_microwatt- Project Name: Microwatt MPW5
- Project Owner: Anton Blanchard
- Project Number: 795
- Description: Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision binary floating-point unit as well as supervisor support that allows it to run Linux. There are hard macros for the 2 multipliers (integer and floating point), the 2 cache RAMs (icache and dcache) and the 4kB main RAM.
- Executable CI Script: mpw5_Microwatt_FP_DFFRFile | mpw5_Microwatt_multiply_add
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mpw6_hyperram- Project Name: HyperRAM Interface
- Project Owner: RECEP GÜNAY
- Project Number: 1004
- Description: Resubmission of Steve Goldsmith's project.
- Executable CI Script: mpw6_hyperram
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mpw6-leaf -
mpw6_REST_II- Project Name: REST_II
- Project Owner: Sajjad Ahmed
- Project Number: 1066
- Description: REST(Resource efficient SRAM based TCAM) is test project for exprimenting the SRAM based TCAMs in ASIC.
- Executable CI Script: mpw6_REST_II
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mpw6_aes_rng- Project Name: Cryptographically Secure RNG Slave
- Project Owner: RECEP GÜNAY
- Project Number: 1079 | 1182
- Description: Cryptographically Secure RNG Slave. Integrates AES cipher and double scroll chaotic RNG circuit to form a CSRNG. AES and Chaotic RNG can also be used separately.
- Executable CI Script: mpw6_aes_rng
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mpw6_alu_xor- Project Name: Four-Bit ALU_XOR - MPW-6
- Project Owner: Janani Aravind
- Project Number: 1053
- Description: This is a digital 4-bit ALU_XOR design.
- Executable CI Script: mpw6_alu_xor
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mpw6_alu_xor4- Project Name: SEL_SET
- Project Owner: Janani Aravind
- Project Number: 1065
- Description: Four-bit ALU that is hardened to mitigate Single-Event Latch-ups and Transients.
- Executable CI Script: mpw6_alu_xor4
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mpw6_microwatt- Project Name: Microwatt MPW6
- Project Owner: Anton Blanchard
- Project Number: 840
- Description: Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision binary floating-point unit as well as supervisor support that allows it to run Linux. There are hard macros for the 2 multipliers (integer and floating point), the 2 cache RAMs (icache and dcache) and the 4kB main RAM.
- Executable CI Script: Microwatt_FP_DFFRFile | Microwatt_multiply_add
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mpw7_microwatt- Project Name: Microwatt MPW7
- Project Owner: Anton Blanchard
- Project Number: 1165
- Description: Microwatt is a 64 bit OpenPOWER core written in VHDL. It includes an IEEE 754 double-precision binary floating-point unit as well as supervisor support that allows it to run Linux. There are hard macros for the 2 multipliers (integer and floating point), the 2 cache RAMs (icache and dcache) and the 4kB main RAM.
- Executable CI Script: mpw7_Microwatt_FP_DFFRFile | mpw7_Microwatt_multiply_add
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mpw5_open_eFPGA- Project Name: FABulous_eFPGA
- Project Owner: Nguyen Dao
- Project Number: 769
- Description: Demonstration of the open FABulous eFPGA using the OpenLane flow.
- Executable CI Script: mpw5_open_eFPGA
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mpw7_open_eFPGA- Project Name: FABulous_eFPGA_wb
- Project Owner: Nguyen Dao
- Project Number: 1335
- Description: This project demonstrates open source eFPGA generated by FABulous. This version is to support wishbone interface with updated DSP tiles.
- Executable CI Script: mpw5_open_eFPGA
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mpw5_prga- Project Name: ORDER_PRGA
- Project Owner: Georgios T
- Project Number: 742
- Description: A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing; 24-track routing channel with L1 tracks; Capable of implementing 16 out of 30 ISCAS'89 circuits.
- Executable CI Script: mpw5_prga | mpw5_prga_tile_clb
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mpw6_prga- Project Name: ORDER_PRGA
- Project Owner: Georgios T
- Project Number: 968
- Description: A 512-LUT4 FPGA generated using PRGA (Princeton Reconfigurable Gate Array); An 8x8 array of CLBs, each containing 8 LUT4s and 8 DFFs and a local programmable crossbar for intra-CLB routing; 24-track routing channel with L1 tracks; Capable of implementing 16 out of 30 ISCAS'89 circuits.
- Executable CI Script: mpw6_prga | mpw6_prga_tile_clb
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mpw7_prga- Project Name: PRGA-test
- Project Owner: Sam Lim
- Project Number: 1343
- Description: This repository is a branch of the caravel_user_project repository, modified for the tapeout of a 512-LUT4 FPGA generated using PRGA.
- Executable CI Script: mpw7_prga | mpw7_prga_tile_clb
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mpw5_raster_engine- Project Name: Raster_engine
- Project Owner: Mehmet Fatih Gülakar
- Project Number: 766
- Description: An implementation of a rasterization engine using Skywater 130 nm PDK.
- Executable CI Script: mpw5_raster_engine
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mpw7_AI_chip- Project Name: AI-CHIP-4-IN-1
- Project Owner: Taehyun Kim
- Project Number: 1338
- Description: In this chip there are four macros : 1. b-float FMA (16bit multiplication and 32bit accumulation) 2. 2x2 output stationary systolic array 3. 8x8 signed booth multiplier 4. 16 carry propagation adder
- Executable CI Script: mpw7_AI_chip
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mpw7_accelerator_core- Project Name: LABS Search
- Project Owner: Wouter van Verre
- Project Number: 1353
- Description: An accelerator core for finding binary sequence with low autocorellation values
- Executable CI Script: mpw7_accelerator_core
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mpw7_ICG -
mpw7_projtes- Project Name: Observability Project
- Project Owner: Akshaykumar Mehta
- Project Number: 1348
- Description: A step towards making silicon to application layer operate in discrete boxed functions.
- Executable CI Script: mpw7_projtes
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mpw7_RTCClock- Project Name: RTCClock
- Project Owner: Filippo Carastro
- Project Number: 1349
- Description: RTCClock is an open source IP used to have a clock inside microcontroller for project that need hours/day information.
- Executable CI Script: mpw7_RTCClock
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mpw7_SoomRV- Project Name: SoomRV
- Project Owner: Mathis Salmen
- Project Number: 1351
- Description: SoomRV is a simple superscalar Out-of-Order RISC-V microprocessor. It can execute 2 Instructions per cycle completely out of order, and also supports speculative execution and precise exceptions.
- Executable CI Script: mpw7_SoomRV
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mpw7_waprv- Project Name: WARP-V
- Project Owner: Ali Imran
- Project Number: 1287
- Description: WARP-V is an open-source CPU core generator written in TL-Verilog with support for RISC-V and MIPS I. It is a demonstration and exploration vehicle for the flexibility that is possible using the emerging "transaction-level design" methodology. This submission involves a 4-stage RISC-V CPU version of WARP-V.
- Executable CI Script: warpv_core | warpv_wb_interface
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mpw7_yonga_soc- Project Name: YONGA-MCU
- Project Owner: Burak Aykenar
- Project Number: 1331
- Description: Yonga-MCU is a 32-bit RISCV-IMC instruction set compatible SoC design with peripherals like UART, SPI and I2C. The design is based on famous pulp team's pulpino.
- Executable CI Script: yonga_mcu_axi_node_intf_wrap | yonga_mcu_mba_core_region_2 | yonga_mcu_peripherals_2
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multi_encoder- Project Name: Caravel_Multi_encoder
- Project Owner: Manikandan Nagarajan
- Project Number: 128
- Description: This work is an integrated multi purpose encoder design which can simultaneously get two 32-bit data and a key of 32-bit size for generating 32-bit encoded data.
- Executable CI Script: multi_encoder
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NAND_Flash5- Project Name: NAND Flash MPW-5
- Project Owner: Brandon Ong
- Project Number: 690
- Description: Small hand-drawn NAND flash array.
- Executable CI Script: NAND_Flash5
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OpenFASOC_puplpino- Project Name: Ibex Implementation
- Project Owner: Ming Hung Chen
- Project Number: 1085
- Description: Ibex implementation for pulpino design
- Executable CI Script: OpenFASOC_puplpino
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openram_openmpw- Project Name: OpenRAM Test Design
- Project Owner: Serdar Ünal
- Project Number: 978
- Description: This project was designed to be able to test the SRAM macros generated using OpenRAM flow.
- Executable CI Script: openram_openmpw
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patmos_chip- Project Name: Patmos Real-Time Processor
- Project Owner: Martin Schoeberl
- Project Number: 1046 | 1164
- Description: A time-predictable processor called Patmos. This was a 13-week project by 12 students at the Technical University of Denmark.
- Executable CI Script: patmos_chip
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peripheral_extender- Project Name: caravel_peripheral_extender
- Project Owner: Siva Prasad
- Project Number: 458
- Description: An attempt to integrate various peripherals like I2C, I2S, UART, SPI, QSPI , JTAG, PWM, GPIO , WS281B led controller to the Caravel SoC via the wishbone bus. The user address space is exploited as the register space for this controller.
- Executable CI Script: peripheral_extender
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picorF0 -
ppcpu- Project Name: ppcpu
- Project Owner: Piotr Wegrzyn
- Project Number: 1378
- Description: Pipelined 16 bit cpu with custom architecture
- Executable CI Script: ppcpu_clk_div | ppcpu_core | ppcpu_dcache | ppcpu_icache | ppcpu_top_cw_logic | ppcpu_upper_core_logic | ppcpu_uprj_w_const | ppcpu_wb_compressor | ppcpu_wb_cross_clk | ppcpu_wishbone_arbiter
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PSRAM_PRANG- Project Name: PSRAM Interface with PRNG
- Project Owner: Steven Goldsmith
- Project Number: 708
- Description: HyperRAM interface by Steve Goldsmith with an ACORN PRNG by Zhenle Cao.
- Executable CI Script: PSRAM_PRANG
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PWM-Generator- Project Name: PWM_Test
- Project Owner: Karthi Keyan
- Project Number: 503
- Description: NIL
- Executable CI Script: PWM-Generator
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pong-chip -
pwm_openmpw- Project Name: PWM
- Project Owner: Serdar Ünal
- Project Number: 727
- Description: PWM (Pulse Width Modulation) module
- Executable CI Script: pwm_openmpw
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qf100- Project Name: qf105
- Project Owner: Serge Bazanski
- Project Number: 760
- Description: This is a simple, microcontroller-style SoC based
around a Lanai core. Lanai is a
mysteriousRISC core that happens to have an LLVM target, and to which I've successfully ported rustc (to be upstreamed). The core implementation is quite spartan: 3-stage, in-order. Currently targeting a 50MHz fclk. - Executable CI Script: qf_mkLanaiCPU | qf_mkLanaiFrontend | qf_mkQF100Fabric | qf_mkQF100GPIO | qf_mkQF100KSC | qf_mkQF100SPI | qf_wrapper
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RAD_HARD_ALU- Project Name: ASIC Design of Fault Tolernt 16-Bit ALU
- Project Owner: Uzair Ahmad
- Project Number: 636
- Description: This project is the ASIC design of a 16-bit fault-tolerant ALU. As errors are very costly in mission-critical applications. The proposed ALU is implemented for space application by using the concept of hardware redundancy (TMR) with high fault-masking ratio (FMR) voter logic to tolerate the impacts of single event upset generated by radiation etc. and assure reliable functionality.
- Executable CI Script: RAD_HARD_ALU
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RV_1Cycle_CPU_Core- Project Name: RISC-V Single Cycle Core
- Project Owner: Garrett Botkin
- Project Number: 1292
- Description: First attempt at creating a RISC-V Single Cycle Core. Known issues are listed in the GitHub read me.
- Executable CI Script: RV_1Cycle_CPU_Core
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randsack- Project Name: Randsack
- Project Owner: Harrison Pham
- Project Number: 451
- Description: Random number generators and PUFs. Also a few simple peripherals to output the random values (PWM, etc).
- Executable CI Script: collapsering_macro | digitalcore_macro | ringosc_macro
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rift2core -
rioschip -
riscduino -
riscduino_S3- Project Name: Riscduino-SCore(S3)
- Project Owner: Dinesh Annaya
- Project Number: 1047
- Description: A arduino pin compatible Single RISCV 32 Bit core Project
- Executable CI Script: rdS3_ycr_iconnect | rdS3_ycr_core_top | rdS3_ycr_intf
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riscduino_S4- Project Name: Riscduino-SCore(S4)
- Project Owner: Dinesh Annaya
- Project Number: 1166
- Description: A arduino pin compatible Single RISCV 32 Bit core Project
- Executable CI Script: rdS4_ycr_iconnect | rdS4_ycr_core_top | rdS4_ycr_intf | rdS4_pinmux_top | rdS4_qspim_top | rdS4_uart_i2cm_usb_spi_top | rdS4_wb_interconnect | rdS4_wb_host
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riscduino_hikaysici- Project Name: Efabless_MPW6_riscduino
- Project Owner: hikaysici
- Project Number: 975
- Description: This is a clone project from dineshannayya/riscduino
- Executable CI Script: riscduino_hikaysici
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riscv_cpu_mpw7- Project Name: RISC-V CPU
- Project Owner: Steven Goldsmith
- Project Number: 1285
- Description: It's a simple risc-v cpu.
- Executable CI Script: riscv_cpu_mpw7 | riscv_cpu_counter
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rvcore_chip1- Project Name: RVcore Chip1
- Project Owner: Kenji Kise
- Project Number: 1293
- Description: We are developing an optimized RV32I processor named RVCoreP, adopting five-stage pipelining targetting both FPGAs and ASICs.
- Executable CI Script: rvcore_chip1
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rvj1-caravel-soc- Project Name: rvj1-caravel-soc
- Project Owner: Jure Vreca
- Project Number: 1043
- Description: Integrates the riscv-jedro-1 processor into a very simple system-on-a-chip design.
- Executable CI Script: rvj1-caravel-soc
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rvj1-caravel-soc_mpw7- Project Name: rvj1-caravel-soc-mpw7
- Project Owner: Jure Vreca
- Project Number: 1249
- Description: A simple SoC using the custom riscv-jedro-1 processor design.
- Executable CI Script: rvj1-caravel-soc_mpw7
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mpw5_riscduino_dcore- Project Name: Riscduino-DCore
- Project Owner: Dinesh Annaya
- Project Number: 718
- Description: Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targeted for efabless Shuttle program.
- Executable CI Script: rdd_ycr2_iconnect
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riscduino_dcore- Project Name: Riscduino-DCore
- Project Owner: Dinesh Annaya
- Project Number: 838
- Description: Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targeted for efabless Shuttle program.
- Executable CI Script: rdd_ycr2_iconnect
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mpw5_riscduino_qcore- Project Name: Riscduino-QCore
- Project Owner: Dinesh Annaya
- Project Number: 782
- Description: Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targeted for efabless Shuttle program.
- Executable CI Script: rdq_uart_i2cm_usb_spi_top | rdq_qspim_top | rdq_pinmux | rdq_ycr4_iconnect | rdq_ycr_core_top | rdq_ycr_intf
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riscduino_qcore- Project Name: Riscduino-QCore
- Project Owner: Dinesh Annaya
- Project Number: 839
- Description: Riscduino is a Dual 32 bit RISC V based SOC design pin compatible to arudino platform and this soc targeted for efabless Shuttle program.
- Executable CI Script: rdq_uart_i2cm_usb_spi_top | rdq_qspim_top | rdq_pinmux | rdq_ycr4_iconnect | rdq_ycr_core_top | rdq_ycr_intf
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rhythmIC -
rng_chaos -
rng_chaos_scroll- Project Name: RNG MULTI SCROLL CHAOS
- Project Owner: onurkrts
- Project Number: 973
- Description: In this study, a digital RNG based on chaotic oscillators was implemented using the SKY130 process node.
- Executable CI Script: rng_chaos_scroll
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rotfpga -
secure-memory- Project Name: Pseudo-Secure Memory
- Project Owner: Sukru Uzun
- Project Number: 800
- Description: Keeping your data secure. This project aims to secure data from adversaries. It has inherent SRAM to keep the data safe and they are kept as not plaintext but ciphered.
- Executable CI Script: secure-memory-proj | trng_wb_wrapper | secure-memory-wrapper
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seven_segments- Project Name: seven segment seconds
- Project Owner: Matt Venn
- Project Number: 963
- Description: walkthrough tutorial for Efabless
- Executable CI Script: seven_segments
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SHA1_engine- Project Name: SHA1_engine
- Project Owner: Konrad Rzeszutek Wilk
- Project Number: 151
- Description: The SHA1 engine, while not the most secure nowadays, is still used by git commits and TPM PCR values. It has the implementation of RFC3174 using Method 1 along with a WishBone implementation to slurp up 512 bits and then in 160 cycles provide the digest values.
- Executable CI Script: SHA1_engine
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soc_io_expander- Project Name: io_expander
- Project Owner: Siva Prasad
- Project Number: 147
- Description: A gpio expander for the caravel harness to realize a small microcontroller
- Executable CI Script: soc_io_expander
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SonarOnChip8- Project Name: SonarOnChip8
- Project Owner: Mauricio Alejandro Montanares Sepúlveda
- Project Number: 871
- Description: The project implements a digital system for signal processing to capture and process acoustics signals from 36 MEMS microphones with an extended frequency range up to 85 kHz (low ultrasonic band).
- Executable CI Script: SonarOnChip8
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soric_project- Project Name: SORIC
- Project Owner: Thinh Pham
- Project Number: 635
- Description: A SoC with two crypto-supported RISC-V cores.
- Executable CI Script: crypto_core | flexbex_core | soric_soc
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space_controller- Project Name: Space Controller
- Project Owner: Iván Rodríguez Ferrández
- Project Number: 583
- Description: This design is a radiation tolerant UART server that can be used for low level control of multiple input/output ports during a radiation testing campaign. The system features triple redundancy in order to ensure that the commands are properly executed.
- Executable CI Script: space_controller
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spectrometer_hyperspace- Project Name: Hyperspace
- Project Owner: Vladimir Milovanovi
- Project Number: 1018
- Description: A hybride parameterizable radar signal processing accelerator
- Executable CI Script: spectrometer_hyperspace
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spectrometer_hyperspace_mpw7- Project Name: Hyperspace-resubmission
- Project Owner: Vladimir Milovanovi
- Project Number: 1174
- Description: A hybride parameterizable radar signal processing accelerator
- Executable CI Script: spectrometer_hyperspace_mpw7
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sram_test -
subservient- Project Name: Subservient
- Project Owner: Klas Nordmark
- Project Number: 104
- Description: This project consists of an ASIC-adapted version of the award-winning bit-serial RISC-V processor SERV.
- Executable CI Script: subservient
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subservient_SOC- Project Name: Subservient_SOC
- Project Owner: Priyanka Dutta
- Project Number: 166
- Description: SERV is a bit-serial CPU which means that the internal datapath is one bit wide and it is the world's smallest CPU. Subservient SOC consists of multiple SERV modules each connected with openram memory
- Executable CI Script: subservient_SOC
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sudoku-accelerator- Project Name: Sudoku Accelerator
- Project Owner: Andrea Nall
- Project Number: 428
- Description: Sudoku accelerator module that is capable of running an 'only candidate' pass in 23 cycles and a 'naked singles' pass in 108 cycles.
- Executable CI Script: sudoku-accelerator
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SystolicArray- Project Name: Systolic Array Matrix Multiplier
- Project Owner: Ian Zhang
- Project Number: 1286
- Description: Systolic Array is a classical architecture that is recently revitalized among Neural Network accelerator designs. It is the heart of Google's TPUs and major workhorses of DSP engines. In this project, we manually build a 3x3 matrix multiplier with Multiply-Accumulate Units that support two popular data formats used in modern machine learning or neural networks applications.
- Executable CI Script: SystolicArray
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systolic_array- Project Name: Systolic_array
- Project Owner: Veerendra S Devaraddi
- Project Number: 784
- Description: Each node is a Processing ELement (PE) which takes in 3 inputs and produces an output. Each PE shifts the data horizontally and vertically to the neighboring PEs every clock cycle. Systolic arrays access the memory only once, and all the PEs transfer the data to the nearby PEs, thus reducing the memory access.
- Executable CI Script: systolic_array
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treepram -
treepram_red- Project Name: TreePRAM-red
- Project Owner: Tamas Hubai
- Project Number: 508
- Description: Parallel random access machines (PRAM) are a model of computation used in theoretical computer science. They consist of several independent processors (random access machines) communicating with each other by sharing the same memory.
- Executable CI Script: treepram_red
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UETRV_Ecore- Project Name: UETRV-ECore
- Project Owner: Muhammad Tahir
- Project Number: 776
- Description: The project is aimed at multi-axis motion control sub-system development. It integrates a RISC V 32I processor with a motor control module and is a complete SoC. The processor can boot from external flash (SPI interface) and supports vectored interrupts.
- Executable CI Script: UETRV_Core | UETRV_Motor_Top | UETRV_Wishbone_InterConnect
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uP16_ISA- Project Name: ISA 16-bit Microprocessor
- Project Owner: Aloke Das
- Project Number: 1189
- Description: This is simple microprocessor. Instruction Set Architecture (ISA). The data bus is 16 bits wide. Address bus is 12 bits wide. The instructions are like old 8086 microprocessors. This tape-out has 8KB on-chip RAM. Targeted for calculator, display board and small application.
- Executable CI Script: uP16_cpu | uP16_soc_config
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updown_caravel- Project Name: Updown Counter (Test)
- Project Owner: PRANAV LULU
- Project Number: 614
- Description: A simple Updown counter for demo purpose
- Executable CI Script: updown_caravel
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upb_natalius_soc- Project Name: Natalius_SoC
- Project Owner: Fabio Andres Guzman Figueroa
- Project Number: 1095
- Description: Natalius is a compact, capable and fully embedded 8 bit RISC processor core described 100% in Verilog. This processor includes a very tiny VGA Controller suitable for VideoGames.
- Executable CI Script: NSoC_dualport_sram
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uMotorSequencer- Project Name: MicroMotorSequencer
- Project Owner: Joshua Stevens
- Project Number: 1275
- Description: A phased PWM controller for micro motor control.
- Executable CI Script: ums_controller_core | ums_driver_core | ums_spi_controller
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vsdbabysoc- Project Name: VSDBabySoC
- Project Owner: Mufutau Akuruyejo
- Project Number: 519
- Description: VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
- Executable CI Script: vsdbabysoc | vsdbabysoc_wrapper
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vsdmemsoc- Project Name: VSDMemSoC
- Project Owner: Mufutau Akuruyejo
- Project Number: 483
- Description: VSDMemSoC is a small SoC including a RISCV-based processor named RVMYTH and an external 1kB SRAM Instruction Memory (IMem) to separate the processor core and the IMem.
- Executable CI Script: rvmyth_core
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waveform_generator- Project Name: Waveform Generator
- Project Owner: Leo Moser
- Project Number: 1202
- Description: A generic waveform generator divided into stimulus and driver units that can be arbitrarily interconnected.
- Executable CI Script: wfg_merge_memory | wfg_wb_memory | wfg_wb_mux | wfg_top |
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wishbone_CAN- Project Name: wishbone_CAN
- Project Owner: Zachary Ellis
- Project Number: 153
- Description: An implementation of a CAN bus controller as a wishbone peripheral for the open MPW shuttle
- Executable CI Script: wishbone_CAN
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yifive_a2- Project Name: yifive_a2
- Project Owner: Manikantasai2
- Project Number: 558
- Description: YiFive is a 32 bit RISC V based SOC design targeted for efabless Shuttle program. This project uses only open source tool set for simulation,synthesis and backend tools.
- Executable CI Script: clk_buf | clk_skew_adjust | glbl_cfg | sdram | spi_master | syntacore | uart_i2cm_usb
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yifive_r0- Project Name: YiFive (Risc V Based SOC)
- Project Owner: Dinesh Annaya
- Project Number: 152
- Description: YiFive SOC Integrated Syntacore SCR1 Open-source RISC-V compatible MCU-class core + 8 bit SDRAM Memory Controller + Quad SPI. Both Risc V and SDRAM controller are silicon-proven IP.
- Executable CI Script: yifive_r0
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yonga-100m-ethernet- Project Name: YONGA-100M Ethernet
- Project Owner: Abdullah YILDIZ
- Project Number: 436
- Description: YONGA-100M Ethernet is based on the implementation of Alex Forencich's 100Mbps Ethernet design.
- Executable CI Script: yonga-100m-ethernet
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yonga-can-controller- Project Name: YONGA-CAN Controller
- Project Owner: Abdullah YILDIZ
- Project Number: 962
- Description: YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.
- Executable CI Script: yonga-can-controller
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yonga-can-controller_mpw7- Project Name: YONGA-CAN Controller
- Project Owner: Abdullah YILDIZ
- Project Number: 1321
- Description: YONGA-CAN Controller is a partial implementation of CAN 2.0B standard.
- Executable CI Script: yonga-can-controller_mpw7
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yonga-lz4-decoder- Project Name: YONGA-LZ4 Decoder
- Project Owner: Abdullah YILDIZ
- Project Number: 162
- Description: YONGA-LZ4 Decoder is an implementation of the decoder of the popular LZ4 compression algorithm.
- Executable CI Script: yonga-lz4-decoder
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yonga_turbo_encoder- Project Name: YONGA-Turbo Encoder
- Project Owner: Abdullah YILDIZ
- Project Number: 657
- Description: YONGA-Turbo Encoder is an implementation of a high-performance forward error correction (FEC) coding technique.
- Executable CI Script: yonga_turbo_encoder
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yonga_modbus_controller- Project Name: YONGA-Modbus Controller
- Project Owner: Burak Yakup Çakar
- Project Number: 1023
- Description: A Modbus controller which has a read(03h) and a write(10h) function. The controller provides access to a 256x16 register space.
- Executable CI Script: yonga_modbus_controller
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yonga-serv-accelerator- Project Name: YONGA-SERV Accelerator
- Project Owner: Abdullah YILDIZ
- Project Number: 434
- Description: YONGA-SERV Accelerator includes the award-winning SERV RISC-V processor with a matrix multiplication accelerator.
- Executable CI Script: yonga-serv-accelerator
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zero_to_asic_mpw6- Project Name: Zero to ASIC Group submission MPW6
- Project Owner: Matt Venn
- Project Number: 833
- Description: Zero to ASIC course group submission MPW6
- Executable CI Script: zero_to_asic_mpw6