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FPGA_Top_Level.flow.rpt
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Flow report for FPGA_Top_Level
Wed Jul 17 00:41:22 2024
Quartus Prime Version 22.1std.2 Build 922 07/20/2023 SC Lite Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
8. Flow Messages
9. Flow Suppressed Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 2023 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions
and other software and tools, and any partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Intel Program License
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
+----------------------------------------------------------------------------------+
; Flow Summary ;
+---------------------------------+------------------------------------------------+
; Flow Status ; Successful - Wed Jul 17 00:41:22 2024 ;
; Quartus Prime Version ; 22.1std.2 Build 922 07/20/2023 SC Lite Edition ;
; Revision Name ; FPGA_Top_Level ;
; Top-level Entity Name ; FPGA_Top_Level ;
; Family ; Cyclone V ;
; Device ; 5CGTFD9E5F35C7 ;
; Timing Models ; Final ;
; Logic utilization (in ALMs) ; 52 / 113,560 ( < 1 % ) ;
; Total registers ; 199 ;
; Total pins ; 52 / 616 ( 8 % ) ;
; Total virtual pins ; 0 ;
; Total block memory bits ; 7,168 / 12,492,800 ( < 1 % ) ;
; Total DSP Blocks ; 0 / 342 ( 0 % ) ;
; Total HSSI RX PCSs ; 0 / 12 ( 0 % ) ;
; Total HSSI PMA RX Deserializers ; 0 / 12 ( 0 % ) ;
; Total HSSI TX PCSs ; 0 / 12 ( 0 % ) ;
; Total HSSI PMA TX Serializers ; 0 / 12 ( 0 % ) ;
; Total PLLs ; 2 / 20 ( 10 % ) ;
; Total DLLs ; 0 / 4 ( 0 % ) ;
+---------------------------------+------------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 07/17/2024 00:39:22 ;
; Main task ; Compilation ;
; Revision Name ; FPGA_Top_Level ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
; COMPILER_SIGNATURE_ID ; 238300910542522.172115696216640 ; -- ; -- ; -- ;
; EDA_ENABLE_GLITCH_FILTERING ; On ; -- ; -- ; eda_simulation ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_timing ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_boundary_scan ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_signal_integrity ;
; EDA_GENERATE_FUNCTIONAL_NETLIST ; Off ; -- ; -- ; eda_board_design_symbol ;
; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; Questa Intel FPGA (Verilog) ; <None> ; -- ; -- ;
; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; Instances/TX_PLL.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Instances/RX_PLL.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_TX.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_TX_inst.v ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_TX_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_TX.inc ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_TX.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_TX.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_RX.bsf ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_RX_inst.v ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_RX_bb.v ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_RX.inc ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_RX.cmp ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_RX.ppf ; -- ; -- ; -- ;
; MISC_FILE ; Instances/ALTDDIO_CLK_OUT.ppf ; -- ; -- ; -- ;
; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
; POWER_USE_DEVICE_CHARACTERISTICS ; MAXIMUM ; TYPICAL ; -- ; -- ;
; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
; VHDL_INPUT_VERSION ; VHDL_2008 ; VHDL_1993 ; -- ; -- ;
; VHDL_SHOW_LMF_MAPPING_MESSAGES ; Off ; -- ; -- ; -- ;
+-------------------------------------+----------------------------------------+---------------+-------------+-----------------------------------+
+--------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:11 ; 1.0 ; 4936 MB ; 00:00:20 ;
; Fitter ; 00:01:22 ; 1.0 ; 7901 MB ; 00:03:07 ;
; Assembler ; 00:00:12 ; 1.0 ; 5900 MB ; 00:00:12 ;
; Timing Analyzer ; 00:00:10 ; 1.1 ; 5656 MB ; 00:00:10 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 4962 MB ; 00:00:02 ;
; Total ; 00:01:57 ; -- ; -- ; 00:03:51 ;
+----------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------+
; Flow OS Summary ;
+----------------------+------------------+------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+----------------------+------------------+------------+------------+----------------+
; Analysis & Synthesis ; MSI ; Windows 10 ; 10.0 ; x86_64 ;
; Fitter ; MSI ; Windows 10 ; 10.0 ; x86_64 ;
; Assembler ; MSI ; Windows 10 ; 10.0 ; x86_64 ;
; Timing Analyzer ; MSI ; Windows 10 ; 10.0 ; x86_64 ;
; EDA Netlist Writer ; MSI ; Windows 10 ; 10.0 ; x86_64 ;
+----------------------+------------------+------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off FPGA_Top_Level -c FPGA_Top_Level
quartus_fit --read_settings_files=off --write_settings_files=off FPGA_Top_Level -c FPGA_Top_Level
quartus_asm --read_settings_files=off --write_settings_files=off FPGA_Top_Level -c FPGA_Top_Level
quartus_sta FPGA_Top_Level -c FPGA_Top_Level
quartus_eda --read_settings_files=off --write_settings_files=off FPGA_Top_Level -c FPGA_Top_Level