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<h1 align=center>The VHDL Cookbook</h1>
<p align=center>Peter J. Ashenden</p>
<h2>1. Introduction</h2>
VHDL is a language for describing digital electronic systems. It arose out of the United States Government’s Very High Speed Integrated Circuits (VHSIC) program, initiated in 1980. In the course of this program, it became clear that there was a need for a standard language for describing the structure and function of integrated circuits (ICs). Hence the VHSIC Hardware Description Language (VHDL) was developed, and subsequently adopted as a standard by the Institute of Electrical and Electronic Engineers (IEEE) in the US.
VHDL is designed to fill a number of needs in the design process. Firstly, it allows description of the structure of a design, that is how it is decomposed into sub-designs, and how those sub-designs are interconnected. Secondly, it allows the specification of the function of designs using familiar programming language forms. Thirdly, as a result, it allows a design to be simulated before being manufactured, so that designers can quickly compare alternatives and test for correctness without the delay and expense of hardware prototyping.
The purpose of this booklet is to give you a quick introduction to VHDL. This is done by informally describing the facilities provided by the language, and using examples to illustrate them. This booklet does not fully describe every aspect of the language. For such fine details, you should consult the IEEE Standard VHDL Language Reference Manual. However, be warned: the standard is like a legal document, and is very difficult to read unless you are already familiar with the language. This booklet does cover enough of the language for substantial model writing. It assumes you know how to write computer programs using a conventional programming language such as Pascal, C or Ada.
The remaining chapters of this booklet describe the various aspects of VHDL in a bottom-up manner. Chapter2 describes the facilities of VHDL which most resemble normal sequential programming languages. These include data types, variables, expressions, sequential statements and subprograms. Chapter3 then examines the facilities for describing the structure of a module and how it it decomposed into sub-modules. Chapter4 covers aspects of VHDL that integrate the programming language features with a discrete event timing model to allow simulation of behaviour. Chapter5 is a key chapter that shows how all these facilities are combined to form a complete model of a system. Then Chapter6 is a potpourri of more advanced features which you may find useful for modelling more complex systems.
Throughout this booklet, the syntax of language features is presented in Backus-Naur Form (BNF). The syntax specifications are drawn from the IEEE VHDL Standard. Concrete examples are also given to illustrate the language features. In some cases, some alternatives are omitted from BNF productions where they are not directly relevant to the context. For this reason, the full syntax is included in AppendixA, and should be consulted as a reference.
<h3>1.1. Describing Structure</h3>
A digital electronic system can be described as a module with inputs and/or outputs. The electrical values on the outputs are some function of the values on the inputs. Figure1-1(a) shows an example of this view of a digital system. The module F has two inputs, A and B, and an output Y. Using VHDL terminology, we call the module F a design entity, and the inputs and outputs are called ports.
One way of describing the function of a module is to describe how it is composed of sub-modules. Each of the sub-modules is an instance of some entity, and the ports of the instances are connected using signals. Figure1-1(b) shows how the entity F might be composed of instances of entities G, H and I. This kind of description is called a structural description. Note that each of the entities G, H and I might also have a structural description.
<h3>1.2. Describing Behaviour</h3>
In many cases, it is not appropriate to describe a module structurally. One such case is a module which is at the bottom of the hierarchy of some other structural description. For example, if you are designing a system using IC packages bought from an IC shop, you do not need to describe the internal structure of an IC. In such cases, a description of the function performed by the module is required, without reference to its actual internal structure. Such a description is called a functional or behavioural description.
To illustrate this, suppose that the function of the entity F in Figure1-1(a) is the exclusive-or function. Then a behavioural description of F could be the Boolean function
Y <span class="Statement">=</span> A <span class="Special">.</span> B <span class="Statement">+</span> A <span class="Special">.</span> B
More complex behaviours cannot be described purely as a function of inputs. In systems with feedback, the outputs are also a function of time. VHDL solves this problem by allowing description of behaviour in the form of an executable program. Chapters2 and4 describe the programming language facilities.
<h3>1.3. Discrete Event Time Model</h3>
Once the structure and behaviour of a module have been specified, it is possible to simulate the module by executing its behavioural description. This is done by simulating the passage of time in discrete steps. At some simulation time, a module input may be stimulated by changing the value on an input port. The module reacts by running the code of its behavioural description and scheduling new values to be placed on the signals connected to its output ports at some later simulated time. This is called scheduling a transaction on that signal. If the new value is different from the previous value on the signal, an event occurs, and other modules with input ports connected to the signal may be activated.
The simulation starts with an initialisation phase, and then proceeds by repeating a two-stage simulation cycle. In the initialisation phase, all signals are given initial values, the simulation time is set to zero, and each module’s behaviour program is executed. This usually results in transactions being scheduled on output signals for some later time.
In the first stage of a simulation cycle, the simulated time is advanced to the earliest time at which a transaction has been scheduled. All transactions scheduled for that time are executed, and this may cause events to occur on some signals.
In the second stage, all modules which react to events occurring in the first stage have their behaviour program executed. These programs will usually schedule further transactions on their output signals. When all of the behaviour programs have finished executing, the simulation cycle repeats. If there are no more scheduled transactions, the whole simulation is completed.
The purpose of the simulation is to gather information about the changes in system state over time. This can be done by running the simulation under the control of a simulation monitor. The monitor allows signals and other state information to be viewed or stored in a trace file for later analysis. It may also allow interactive stepping of the simulation process, much like an interactive program debugger.
<h3>1.4. A Quick Example</h3>
In this section we will look at a small example of a VHDL description of a two-bit counter to give you a feel for the language and how it is used. We start the description of an entity by specifying its external interface, which includes a description of its ports. So the counter might be defined as:
<span class="Statement">entity</span> count2 <span class="Statement">is</span>
<span class="Statement">generic</span> <span class="Special">(</span>prop_delay : <span class="Type">Time</span> <span class="Statement">:=</span> <span class="Constant">10 ns</span><span class="Special">);</span>
<span class="Statement">port</span> <span class="Special">(</span>clock : <span class="Statement">in</span> <span class="Type">bit</span><span class="Special">;</span> q1<span class="Special">,</span> q0 : <span class="Statement">out</span> <span class="Type">bit</span><span class="Special">);</span>
<span class="Statement">end</span> count2<span class="Special">;</span>
This specifies that the entity count2 has one input and two outputs, all of which are bit values, that is, they can take on the values '0' or '1'. It also defines a generic constant called prop_delay which can be used to control the operation of the entity (in this case its propagation delay). If no value is explicitly given for this value when the entity is used in a design, the default value of 10ns will be used.
An implementation of the entity is described in an architecture body. There may be more than one architecture body corresponding to a single entity specification, each of which describes a different view of the entity. For example, a behavioural description of the counter could be written as:
<span class="Statement">architecture</span> behaviour <span class="Statement">of</span> count2 <span class="Statement">is</span>
<span class="Statement">begin</span>
count_up: <span class="Statement">process</span> <span class="Special">(</span>clock<span class="Special">)</span>
<span class="Statement">variable</span> count_value : <span class="Type">natural</span> <span class="Statement">:=</span> <span class="Constant">0</span><span class="Special">;</span>
<span class="Statement">begin</span>
<span class="Statement">if</span> clock <span class="Statement">=</span> <span class="Constant">'1'</span> <span class="Statement">then</span>
count_value <span class="Statement">:=</span> <span class="Special">(</span>count_value <span class="Statement">+</span> <span class="Constant">1</span><span class="Special">)</span> <span class="Statement">mod</span> <span class="Constant">4</span><span class="Special">;</span>
q0 <span class="Statement"><=</span> <span class="Type">bit'</span>val<span class="Special">(</span>count_value <span class="Statement">mod</span> <span class="Constant">2</span><span class="Special">)</span> <span class="Statement">after</span> prop_delay<span class="Special">;</span>
q1 <span class="Statement"><=</span> <span class="Type">bit'</span>val<span class="Special">(</span>count_value <span class="Statement">/</span> <span class="Constant">2</span><span class="Special">)</span> <span class="Statement">after</span> prop_delay<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">if</span> <span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">process</span> count_up<span class="Special">;</span>
<span class="Statement">end</span> behaviour<span class="Special">;</span>
In this description of the counter, the behaviour is implemented by a process called count_up, which is sensitive to the input clock. A process is a body of code which is executed whenever any of the signals it is sensitive to changes value. This process has a variable called count_value to store the current state of the counter. The variable is initialised to zero at the start of simulation, and retains its value between activations of the process. When the clock input changes from '0' to '1', the state variable is incremented, and transactions are scheduled on the two output ports based on the new value. The assignments use the generic constant prop_delay to determine how long after the clock change the transaction should be scheduled. When control reaches the end of the process body, the process is suspended until another change occurs on clock.
The two-bit counter might also be described as a circuit composed of two T-flip-flops and an inverter, as shown in Figure1-2. This can be written in VHDL as:
<span class="Statement">architecture</span> structure <span class="Statement">of</span> count2 <span class="Statement">is</span>
<span class="Statement">component</span> t_flipflop
<span class="Statement">port</span> <span class="Special">(</span>
ck : <span class="Statement">in</span> <span class="Type">bit</span><span class="Special">;</span>
q : <span class="Statement">out</span> <span class="Type">bit</span>
<span class="Special">);</span>
<span class="Statement">end</span> <span class="Statement">component</span> <span class="Special">;</span>
<span class="Statement">component</span> inverter
<span class="Statement">port</span> <span class="Special">(</span>
a : <span class="Statement">in</span> <span class="Type">bit</span><span class="Special">;</span>
y : <span class="Statement">out</span> <span class="Type">bit</span>
<span class="Special">);</span>
<span class="Statement">end</span> <span class="Statement">component</span> <span class="Special">;</span>
<span class="Statement">signal</span> ff0<span class="Special">,</span> ff1<span class="Special">,</span> inv_ff0 : <span class="Type">bit</span><span class="Special">;</span>
<span class="Statement">begin</span>
bit_0 : t_flipflop <span class="Statement">port</span> <span class="Statement">map</span> <span class="Special">(</span>ck <span class="Statement">=></span> clock<span class="Special">,</span> q <span class="Statement">=></span> ff0<span class="Special">);</span>
inv : inverter <span class="Statement">port</span> <span class="Statement">map</span> <span class="Special">(</span>a <span class="Statement">=></span> ff0<span class="Special">,</span> y <span class="Statement">=></span> inv_ff0<span class="Special">);</span>
bit_1 : t_flipflop <span class="Statement">port</span> <span class="Statement">map</span> <span class="Special">(</span>ck <span class="Statement">=></span> inv_ff0<span class="Special">,</span> q <span class="Statement">=></span> ff1<span class="Special">);</span>
q0 <span class="Statement"><=</span> ff0<span class="Special">;</span>
q1 <span class="Statement"><=</span> ff1<span class="Special">;</span>
<span class="Statement">end</span> structure<span class="Special">;</span>
In this architecture, two component types are declared, t_flipflop and inverter, and three internal signals are declared. Each of the components is then instantiated, and the ports of the instances are mapped onto signals and ports of the entity. For example, bit_0 is an instance of the t_flipflop component, with its ck port connected to the clock port of the count2 entity, and its q port connected to the internal signal ff0. The last two signal assignments update the entity ports whenever the values on the internal signals change.
<h2>2. VHDL is Like a Programming Language</h2>
As mentioned in Section 1.2, the behaviour of a module may be described in programming language form. This chapter describes the facilities in VHDL which are drawn from the familiar programming language repertoire. If you are familiar with the Ada programming language, you will notice the similarity with that language. This is both a convenience and a nuisance. The convenience is that you don’t have much to learn to use these VHDL facilities. The problem is that the facilities are not as comprehensive as those of Ada, though they are certainly adequate for most modelling purposes.
<h3>2.1. Lexical Elements</h3>
<h4>2.1.0. Fundamental elements</h4>
<span class="Constant">upper_case_letter </span><span class="PreProc">::=</span>
<span class="bnfLine"> A B C D E F G H I J K L M N O P Q R S T U V W X Y Z À Á Â Ã Ä Å Æ Ç È É Ê Ë Ì Í Î Ï D. Ñ Ò Ó Ô Õ Ö Ø Ù Ú Û Ü Ý P'</span>
<span class="Constant">digit </span><span class="PreProc">::=</span>
<span class="bnfLine"> 0 1 2 3 4 5 6 7 8 9</span>
<span class="Constant">special_character </span><span class="PreProc">::=</span>
<span class="bnfLine"> " # & ' ( ) * + , - . / : ; < = > [ ] _ |</span>
<span class="Constant">space_character </span><span class="PreProc">::=</span>
<span class="bnfLine"> SPACE NBSP</span>
<span class="Constant">lower_case_letter </span><span class="PreProc">::=</span>
<span class="bnfLine"> a b c d e f g h i j k l m n o p q r s t u v w x y z ß à á â ã ä å æ ç è é ê ë ì í î ï ∂´ ñ ò ó ô õ ö ø ù ú û ü ý p' ÿ</span>
<span class="Constant">other_special_character </span><span class="PreProc">::=</span>
<span class="bnfLine"> ! $ % @ ? \ ^ ` { } ~ ¡ ¢ £ € ¥ | § ̈ © a « ¬ -® ̄ ° ± 2 3 ́ μ ¶ • ̧ 1 o » 1/4 1/2 3/4 ¿ ◊ ÷ - (soft hyphen)</span>
<span class="Constant">basic_graphic_character </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">upper_case_letter</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">digit</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">special_character</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">space_character</span>
<span class="Constant">graphic_character </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">basic_graphic_character</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">lower_case_letter</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">other_special_character</span>
<span class="Constant">basic_character </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">basic_graphic_character</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">format_effector</span>
<span class="Constant">format_effectors </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="Comment">-- The ISO (and ASCII) characters called horizontal tabulation, vertical tabulation, carriage return, line feed, and form feed.</span>
<h4>2.1.1. Comments</h4>
Comments in VHDL start with two adjacent hyphens (‘--’) and extend to the end of the line. They have no part in the meaning of a VHDL description.
<h4>2.1.2. Identifiers</h4>
Identifiers in VHDL are used as reserved words and as programmer defined names. They must conform to the rule:
<span class="Constant">identifier </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">basic_identifier</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">extended_identifier</span>
<span class="Constant">basic_identifier </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">letter</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> _ </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">letter_or_digit</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">letter_or_digit </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">letter</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">digit</span>
<span class="Constant">letter </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">upper_case_letter</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">lower_case_letter</span>
<span class="Constant">extended_identifier </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">\</span><span class="Statement"> </span><span class="bnfLine">graphic_character</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">graphic_character</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> </span><span class="bnfLine">\</span>
Note that case of letters is not considered significant, so the identifiers cat and Cat are the same. Underline characters in identifiers are significant, so This_Name and ThisName are different identifiers.
<h4>2.1.3. Numbers</h4>
Literal numbers may be expressed either in decimal or in a base between two and sixteen. If the literal includes a point, it represents a real number, otherwise it represents an integer. Decimal literals are defined by:
<span class="Constant">abstract_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">decimal_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">based_literal</span>
<span class="Constant">decimal_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">integer</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> . </span><span class="bnfLine">integer</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">exponent</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">integer </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">digit</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> _ </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">digit</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">exponent </span><span class="PreProc">::=</span>
<span class="Statement"> E </span><span class="bnfOr">[</span><span class="Statement"> + </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">integer</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> E - </span><span class="bnfLine">integer</span>
Some examples are:
<span class="Constant">0</span> <span class="Constant">1</span> <span class="Constant">123_456_789</span> <span class="Constant">987E6</span><span class="Comment"> -- integer literals</span>
<span class="Constant">0.0</span> <span class="Constant">0.5</span> <span class="Constant">2.718_28</span> <span class="Constant">12.4E-9</span><span class="Comment"> -- real literals</span>
Based literal numbers are defined by:
<span class="Constant">based_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">base</span><span class="Statement"> # </span><span class="bnfLine">based_integer</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> . </span><span class="bnfLine">based_integer</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> # </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">exponent</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">base </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">integer</span>
<span class="Constant">based_integer </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">extended_digit</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> _ </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">extended_digit</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">extended_digit </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">digit</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">letter</span>
The base and the exponent are expressed in decimal. The exponent indicates the power of the base by which the literal is multiplied. The letters A to F (upper or lower case) are used as extended digits to represent 10 to 15. Some examples:
<span class="Constant">2#1100_0100#</span> <span class="Constant">16#C4#</span> <span class="Constant">2#1.1111_1111_111#E+11</span> <span class="Constant">4#301#E1</span><span class="Comment"> -- the integer 196</span>
<span class="Constant">16#F.FF#E2</span><span class="Comment"> -- the real number 4095.0</span>
<h4>2.1.4. Characters</h4>
Literal characters are formed by enclosing an ASCII character in single-quote marks. For example:
<span class="Constant">character_literal </span><span class="PreProc">::=</span>
<span class="Statement"> ' </span><span class="bnfLine">graphic_character</span><span class="Statement"> '</span>
<span class="Constant">'A'</span> <span class="Constant">'*'</span> <span class="Constant">'''</span> <span class="Constant">' '</span>
<h4>2.1.5. Strings</h4>
Literal strings of characters are formed by enclosing the characters in double-quote marks. To include a double-quote mark itself in a string, a pair of double-quote marks must be put together. A string can be used as a value for an object which is an array of characters. Examples of strings:
<span class="Constant">string_literal </span><span class="PreProc">::=</span>
<span class="Statement"> " </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">graphic_character</span><span class="Statement"> </span><span class="bnfOr">|</span><span class="Statement"> "" </span><span class="bnfOr">}</span><span class="Statement"> "</span>
<span class="Constant">"A string"</span> <span class="Constant">""</span><span class="Comment"> -- empty string</span>
<span class="Constant">"A string in a string: ""A string"". "</span><span class="Comment"> -- contains quote marks</span>
<h4>2.1.6. Bit Strings</h4>
VHDL provides a convenient way of specifying literal values for arrays of type bit ('0's and '1's, see Section 2.2.5). The syntax is:
<span class="Constant">bit_string_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">base_specifier</span><span class="Statement"> " </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">bit_value</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> "</span>
<span class="Constant">base_specifier </span><span class="PreProc">::=</span>
<span class="Statement"> B </span><span class="bnfOr">|</span><span class="Statement"> O </span><span class="bnfOr">|</span><span class="Statement"> X</span>
<span class="Constant">bit_value </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">extended_digit</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> _ </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">extended_digit</span><span class="Statement"> </span><span class="bnfOr">}</span>
Base specifier B stands for binary, O for octal and X for hexadecimal. Some examples:
<span class="Constant">B"1010110"</span><span class="Comment"> -- length is 7</span>
<span class="Constant">O"126"</span><span class="Comment"> -- length is 9, equivalent to B"001_010_110"</span>
<span class="Constant">X"56"</span><span class="Comment"> -- length is 8, equivalent to B"0101_0110"</span>
<h4>2.1.7. Allowable replacements of characters</h4>
The following replacements are allowed for the vertical line, number sign, and quotation mark basic characters:
— A vertical line (|) can be replaced by an exclamation mark (!) where used as a delimiter.
— The number sign (#) of a based literal can be replaced by colons (:), provided that the replacement is done for both occurrences.
— The quotation marks (") used as string brackets at both ends of a string literal can be replaced by percent signs (%), provided that the enclosed sequence of characters contains no quotation marks, and provided that both string brackets are replaced. Any percent sign within the sequence of characters must then be doubled, and each such doubled percent sign is interpreted as a single percent sign value. The same replacement is allowed for a bit string literal, provided that both bit string brackets are replaced.
<h3>2.2. Data Types and Objects</h3>
VHDL provides a number of basic, or scalar, types, and a means of forming composite types. The scalar types include numbers, physical quantities, and enumerations (including enumerations of characters), and there are a number of standard predefined basic types. The composite types provided are arrays and records. VHDL also provides access types (pointers) and files, although these will not be fully described in this booklet.
A data type can be defined by a type declaration:
<span class="Constant">full_type_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> type </span><span class="bnfLine">identifier</span><span class="Statement"> is </span><span class="bnfLine">type_definition</span><span class="Statement"> ;</span>
<span class="Constant">type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">scalar_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">composite_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">access_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">file_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">protected_type_definition</span>
<span class="Constant">scalar_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">enumeration_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">integer_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">floating_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">physical_type_definition</span>
<span class="Constant">composite_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">array_type_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">record_type_definition</span>
Examples of different kinds of type declarations are given in the following sections.
<h4>2.2.1. Integer Types</h4>
An integer type is a range of integer values within a specified range. The syntax for specifying integer types is:
<span class="Constant">integer_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">range_constraint</span>
<span class="Constant">range_constraint </span><span class="PreProc">::=</span>
<span class="Statement"> range </span><span class="bnfLine">range_term</span>
<span class="Constant">range_term </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>range</i>_attribute_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">simple_expression</span><span class="Statement"> </span><span class="bnfLine">direction</span><span class="Statement"> </span><span class="bnfLine">simple_expression</span>
<span class="Constant">direction </span><span class="PreProc">::=</span>
<span class="Statement"> to </span><span class="bnfOr">|</span><span class="Statement"> downto</span>
The expressions that specify the range must of course evaluate to integer numbers. Types declared with the keyword to are called ascending ranges, and those declared with the keyword downto are called descending ranges. The VHDL standard allows an implementation to restrict the range, but requires that it must at least allow the range –2147483647 to +2147483647.
Some examples of integer type declarations:
<span class="Statement">type</span> byte_int <span class="Statement">is</span> <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> <span class="Constant">255</span><span class="Special">;</span>
<span class="Statement">type</span> signed_word_int <span class="Statement">is</span> <span class="Statement">range</span> –<span class="Constant">32768</span> <span class="Statement">to</span> <span class="Constant">32767</span><span class="Special">;</span>
<span class="Statement">type</span> bit_index <span class="Statement">is</span> <span class="Statement">range</span> <span class="Constant">31</span> <span class="Statement">downto</span> <span class="Constant">0</span><span class="Special">;</span>
There is a predefined integer type called integer. The range of this type is implementation defined, though it is guaranteed to include –2147483647 to +2147483647.
<h4>2.2.2. Physical Types</h4>
A physical type is a numeric type for representing some physical quantity, such as mass, length, time or voltage. The declaration of a physical type includes the specification of a base unit, and possibly a number of secondary units, being multiples of the base unit. The syntax for declaring physical types is:
<span class="Constant">physical_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">range_constraint</span>
<span class="Statement"> units </span><span class="bnfLine">base_unit_declaration</span>
<span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">secondary_unit_declaration</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Statement"> end units </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">physical_type_simple_name</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">base_unit_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span><span class="Statement"> ;</span>
<span class="Constant">secondary_unit_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span><span class="Statement"> = </span><span class="bnfLine">physical_literal</span><span class="Statement"> ;</span>
<span class="Constant">physical_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">abstract_literal</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine"><i>unit</i>_name</span>
Some examples of physical type declarations:
<span class="Statement">type</span> length <span class="Statement">is</span> <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> <span class="Constant">1E9</span>
<span class="Statement">units</span> um<span class="Special">;</span>
mm <span class="Statement">=</span> <span class="Constant">1000</span> um<span class="Special">;</span>
cm <span class="Statement">=</span> <span class="Constant">10</span> mm<span class="Special">;</span>
m <span class="Statement">=</span> <span class="Constant">1000</span> mm<span class="Special">;</span>
<span class="Statement">in</span> <span class="Statement">=</span> <span class="Constant">25.4</span> mm<span class="Special">;</span>
ft <span class="Statement">=</span> <span class="Constant">12</span> <span class="Statement">in</span><span class="Special">;</span>
yd <span class="Statement">=</span> <span class="Constant">3</span> ft<span class="Special">;</span>
rod <span class="Statement">=</span> <span class="Constant">198</span> <span class="Statement">in</span><span class="Special">;</span>
chain <span class="Statement">=</span> <span class="Constant">22</span> yd<span class="Special">;</span>
furlong <span class="Statement">=</span> <span class="Constant">10</span> chain<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">units</span><span class="Special">;</span>
<span class="Statement">type</span> resistance <span class="Statement">is</span> <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> <span class="Constant">1E8</span>
<span class="Statement">units</span> ohms<span class="Special">;</span>
kohms <span class="Statement">=</span> <span class="Constant">1000</span> ohms<span class="Special">;</span>
Mohms <span class="Statement">=</span> <span class="Constant">1E6</span> ohms<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">units</span><span class="Special">;</span>
The predefined physical type time is important in VHDL, as it is used extensively to specify delays in simulations. Its definition is:
<span class="Statement">type</span> <span class="Type">time</span> <span class="Statement">is</span> <span class="Statement">range</span> implementation_defined
<span class="Statement">units</span>
fs<span class="Special">;</span>
ps <span class="Statement">=</span> <span class="Constant">1000 fs</span><span class="Special">;</span>
ns <span class="Statement">=</span> <span class="Constant">1000 ps</span><span class="Special">;</span>
us <span class="Statement">=</span> <span class="Constant">1000 ns</span><span class="Special">;</span>
ms <span class="Statement">=</span> <span class="Constant">1000 us</span><span class="Special">;</span>
sec <span class="Statement">=</span> <span class="Constant">1000 ms</span><span class="Special">;</span>
min <span class="Statement">=</span> <span class="Constant">60 sec</span><span class="Special">;</span>
hr <span class="Statement">=</span> <span class="Constant">60 min</span><span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">units</span> <span class="Special">;</span>
To write a value of some physical type, you write the number followed by the unit. For example:
<span class="Constant">10</span> mm <span class="Constant">1</span> rod <span class="Constant">1200</span> ohm <span class="Constant">23 ns</span>
<h4>2.2.3. Floating Point Types</h4>
A floating point type is a discrete approximation to the set of real numbers in a specified range. The precision of the approximation is not defined by the VHDL language standard, but must be at least six decimal digits. The range must include at least –1E38 to +1E38. A floating point type is declared using the syntax:
<span class="Constant">floating_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">range_constraint</span>
Some examples are:
<span class="Statement">type</span> signal_level <span class="Statement">is</span> <span class="Statement">range</span> –<span class="Constant">10.00</span> <span class="Statement">to</span> <span class="Statement">+</span><span class="Constant">10.00</span><span class="Special">;</span>
<span class="Statement">type</span> probability <span class="Statement">is</span> <span class="Statement">range</span> <span class="Constant">0.0</span> <span class="Statement">to</span> <span class="Constant">1.0</span><span class="Special">;</span>
There is a predefined floating point type called real. The range of this type is implementation defined, though it is guaranteed to include –1E38 to +1E38.
<h4>2.2.4. Enumeration Types</h4>
An enumeration type is an ordered set of identifiers or characters. The identifiers and characters within a single enumeration type must be distinct, however they may be reused in several different enumeration types.
The syntax for declaring an enumeration type is:
<span class="Constant">enumeration_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> ( </span><span class="bnfLine">enumeration_literal</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">enumeration_literal</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> )</span>
<span class="Constant">enumeration_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">character_literal</span>
Some examples are:
<span class="Statement">type</span> logic_level <span class="Statement">is</span> <span class="Special">(</span>unknown<span class="Special">,</span> low<span class="Special">,</span> undriven<span class="Special">,</span> high<span class="Special">);</span>
<span class="Statement">type</span> alu_function <span class="Statement">is</span> <span class="Special">(</span>disable<span class="Special">,</span> pass<span class="Special">,</span> add<span class="Special">,</span> subtract<span class="Special">,</span> multiply<span class="Special">,</span> divide<span class="Special">);</span>
<span class="Statement">type</span> octal_digit <span class="Statement">is</span> <span class="Special">(</span><span class="Constant">'0'</span><span class="Special">,</span> <span class="Constant">'1'</span><span class="Special">,</span> <span class="Constant">'2'</span><span class="Special">,</span> <span class="Constant">'3'</span><span class="Special">,</span> <span class="Constant">'4'</span><span class="Special">,</span> <span class="Constant">'5'</span><span class="Special">,</span> <span class="Constant">'6'</span><span class="Special">,</span> <span class="Constant">'7'</span><span class="Special">);</span>
There are a number of predefined enumeration types, defined as follows:
<span class="Statement">type</span> severity_level <span class="Statement">is</span> <span class="Special">(</span><span class="Statement">note</span><span class="Special">,</span> <span class="Statement">warning</span><span class="Special">,</span> <span class="Statement">error</span><span class="Special">,</span> <span class="Statement">failure</span><span class="Special">);</span>
<span class="Statement">type</span> <span class="Type">boolean</span> <span class="Statement">is</span> <span class="Special">(</span><span class="Constant">false</span><span class="Special">,</span> <span class="Constant">true</span><span class="Special">);</span>
<span class="Statement">type</span> <span class="Type">bit</span> <span class="Statement">is</span> <span class="Special">(</span><span class="Constant">'0'</span><span class="Special">,</span> <span class="Constant">'1'</span><span class="Special">);</span>
<span class="Statement">type</span> <span class="Type">character</span> <span class="Statement">is</span> <span class="Special">(</span> NUL<span class="Special">,</span> SOH<span class="Special">,</span> BS<span class="Special">,</span> HT<span class="Special">,</span> DLE<span class="Special">,</span> DC1<span class="Special">,</span> CAN<span class="Special">,</span> EM<span class="Special">,</span> <span class="Constant">' '</span><span class="Special">,</span> <span class="Constant">'!'</span><span class="Special">,</span> <span class="Constant">'('</span><span class="Special">,</span> <span class="Constant">')'</span><span class="Special">,</span> <span class="Constant">'0'</span><span class="Special">,</span> <span class="Constant">'1'</span><span class="Special">,</span> <span class="Constant">'8'</span><span class="Special">,</span> <span class="Constant">'9'</span><span class="Special">,</span> <span class="Constant">'@'</span><span class="Special">,</span> <span class="Constant">'A'</span><span class="Special">,</span> <span class="Constant">'H'</span><span class="Special">,</span> <span class="Constant">'I'</span><span class="Special">,</span> <span class="Constant">'P'</span><span class="Special">,</span> <span class="Constant">'Q'</span><span class="Special">,</span> <span class="Constant">'X'</span><span class="Special">,</span> <span class="Constant">'Y'</span><span class="Special">,</span> <span class="Constant">'`'</span><span class="Special">,</span> <span class="Constant">'a'</span><span class="Special">,</span> <span class="Constant">'h'</span><span class="Special">,</span> <span class="Constant">'i'</span><span class="Special">,</span> <span class="Constant">'p'</span><span class="Special">,</span> <span class="Constant">'q'</span><span class="Special">,</span> <span class="Constant">'x'</span><span class="Special">,</span> <span class="Constant">'y'</span><span class="Special">,</span> STX<span class="Special">,</span> LF<span class="Special">,</span> DC2<span class="Special">,</span> SUB<span class="Special">,</span> <span class="Constant">'"'</span><span class="Special">,</span> <span class="Constant">'*'</span><span class="Special">,</span> <span class="Constant">'2'</span><span class="Special">,</span> <span class="Constant">':'</span><span class="Special">,</span> <span class="Constant">'B'</span><span class="Special">,</span> <span class="Constant">'J'</span><span class="Special">,</span> <span class="Constant">'R'</span><span class="Special">,</span> <span class="Constant">'Z'</span><span class="Special">,</span> <span class="Constant">'b'</span><span class="Special">,</span> <span class="Constant">'j'</span><span class="Special">,</span> <span class="Constant">'r'</span><span class="Special">,</span> <span class="Constant">'z'</span><span class="Special">,</span> ETX<span class="Special">,</span> VT<span class="Special">,</span> DC3<span class="Special">,</span> ESC<span class="Special">,</span> <span class="Constant">'#'</span><span class="Special">,</span> <span class="Constant">'+'</span><span class="Special">,</span> <span class="Constant">'3'</span><span class="Special">,</span> <span class="Constant">';'</span><span class="Special">,</span> <span class="Constant">'C'</span><span class="Special">,</span> <span class="Constant">'K'</span><span class="Special">,</span> <span class="Constant">'S'</span><span class="Special">,</span> <span class="Constant">'['</span><span class="Special">,</span> <span class="Constant">'c'</span><span class="Special">,</span> <span class="Constant">'k'</span><span class="Special">,</span> <span class="Constant">'s'</span><span class="Special">,</span> <span class="Constant">'{'</span><span class="Special">,</span> EOT<span class="Special">,</span> FF<span class="Special">,</span> DC4<span class="Special">,</span> FSP<span class="Special">,</span> <span class="Constant">'$'</span><span class="Special">,</span> <span class="Constant">','</span><span class="Special">,</span> <span class="Constant">'4'</span><span class="Special">,</span> <span class="Constant">'<'</span><span class="Special">,</span> <span class="Constant">'D'</span><span class="Special">,</span> <span class="Constant">'L'</span><span class="Special">,</span> <span class="Constant">'T'</span><span class="Special">,</span> <span class="Constant">'\'</span><span class="Special">,</span> <span class="Constant">'d'</span><span class="Special">,</span> <span class="Constant">'l'</span><span class="Special">,</span> <span class="Constant">'t'</span><span class="Special">,</span> <span class="Constant">'|'</span><span class="Special">,</span> ENQ<span class="Special">,</span> CR<span class="Special">,</span> NAK<span class="Special">,</span> GSP<span class="Special">,</span> <span class="Constant">'%'</span><span class="Special">,</span> <span class="Constant">'-'</span><span class="Special">,</span> <span class="Constant">'5'</span><span class="Special">,</span> <span class="Constant">'='</span><span class="Special">,</span> <span class="Constant">'E'</span><span class="Special">,</span> <span class="Constant">'M'</span><span class="Special">,</span> <span class="Constant">'U'</span><span class="Special">,</span> <span class="Constant">']'</span><span class="Special">,</span> <span class="Constant">'e'</span><span class="Special">,</span> <span class="Constant">'m'</span><span class="Special">,</span> <span class="Constant">'u'</span><span class="Special">,</span> <span class="Constant">'}'</span><span class="Special">,</span> ACK<span class="Special">,</span> SO<span class="Special">,</span> SYN<span class="Special">,</span> RSP<span class="Special">,</span> <span class="Constant">'&'</span><span class="Special">,</span> <span class="Constant">'.'</span><span class="Special">,</span> <span class="Constant">'6'</span><span class="Special">,</span> <span class="Constant">'>'</span><span class="Special">,</span> <span class="Constant">'F'</span><span class="Special">,</span> <span class="Constant">'N'</span><span class="Special">,</span> <span class="Constant">'V'</span><span class="Special">,</span> <span class="Constant">'^'</span><span class="Special">,</span> <span class="Constant">'f'</span><span class="Special">,</span> <span class="Constant">'n'</span><span class="Special">,</span> <span class="Constant">'v'</span><span class="Special">,</span> <span class="Constant">'~'</span><span class="Special">,</span> BEL<span class="Special">,</span> SI<span class="Special">,</span> ETB<span class="Special">,</span> USP<span class="Special">,</span> <span class="Constant">'''</span><span class="Special">,</span> <span class="Constant">'/'</span><span class="Special">,</span> <span class="Constant">'7'</span><span class="Special">,</span> <span class="Constant">'?'</span><span class="Special">,</span> <span class="Constant">'G'</span><span class="Special">,</span> <span class="Constant">'O'</span><span class="Special">,</span> <span class="Constant">'W'</span><span class="Special">,</span> <span class="Constant">'_'</span><span class="Special">,</span> <span class="Constant">'g'</span><span class="Special">,</span> <span class="Constant">'o'</span><span class="Special">,</span> <span class="Constant">'w'</span><span class="Special">,</span> DEL <span class="Special">);</span>
Note that type character is an example of an enumeration type containing a mixture of identifiers and characters. Also, the characters '0' and '1' are members of both bit and character . Where '0' or '1' occur in a program, the context will be used to determine which type is being used.
<h4>2.2.5. Arrays</h4>
An array in VHDL is an indexed collection of elements all of the same type. Arrays may be one-dimensional (with one index) or multidimensional (with a number of indices). In addition, an array type may be constrained, in which the bounds for an index are established when the type is defined, or unconstrained, in which the bounds are established subsequently.
The syntax for declaring an array type is:
<span class="Constant">array_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">unconstrained_array_definition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">constrained_array_definition</span>
<span class="Constant">unconstrained_array_definition </span><span class="PreProc">::=</span>
<span class="Statement"> array ( </span><span class="bnfLine">index_subtype_definition</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">index_subtype_definition</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> ) of </span><span class="bnfLine"><i>element</i>_subtype_indication</span>
<span class="Constant">constrained_array_definition </span><span class="PreProc">::=</span>
<span class="Statement"> array </span><span class="bnfLine">index_constraint</span><span class="Statement"> of </span><span class="bnfLine"><i>element</i>_subtype_indication</span>
<span class="Constant">index_subtype_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> range <></span>
<span class="Constant">index_constraint </span><span class="PreProc">::=</span>
<span class="Statement"> ( </span><span class="bnfLine">discrete_range</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">discrete_range</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> )</span>
<span class="Constant">discrete_range </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>discrete</i>_subtype_indication</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">range_term</span>
Subtypes, referred to in this syntax specification, will be discussed in detail in Section2.2.7.
Some examples of constrained array type declarations:
<span class="Statement">type</span> word <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span><span class="Constant">31</span> <span class="Statement">downto</span> <span class="Constant">0</span><span class="Special">)</span> <span class="Statement">of</span> <span class="Type">bit</span><span class="Special">;</span>
<span class="Statement">type</span> memory <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span>address<span class="Special">)</span> <span class="Statement">of</span> word<span class="Special">;</span>
<span class="Statement">type</span> transform <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span><span class="Constant">1</span> <span class="Statement">to</span> <span class="Constant">4</span><span class="Special">,</span> <span class="Constant">1</span> <span class="Statement">to</span> <span class="Constant">4</span><span class="Special">)</span> <span class="Statement">of</span> <span class="Type">real</span><span class="Special">;</span>
<span class="Statement">type</span> register_bank <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span>byte <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> <span class="Constant">132</span><span class="Special">)</span> <span class="Statement">of</span> <span class="Type">integer</span><span class="Special">;</span>
An example of an unconstrained array type declaration:
<span class="Statement">type</span> vector <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span><span class="Type">integer</span> <span class="Statement">range</span> <span class="Special"><>)</span> <span class="Statement">of</span> <span class="Type">real</span><span class="Special">;</span>
The symbol ‘<>’ (called a box) can be thought of as a place-holder for the index range, which will be filled in later when the array type is used. For example, an object might be declared to be a vector of 20 elements by giving its type as:
vector<span class="Special">(</span><span class="Constant">1</span> <span class="Statement">to</span> <span class="Constant">20</span><span class="Special">)</span>
There are two predefined array types, both of which are unconstrained. They are defined as:
<span class="Statement">type</span> <span class="Type">string</span> <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span> <span class="Type">positive</span> <span class="Statement">range</span> <span class="Special"><></span> <span class="Special">)</span> <span class="Statement">of</span> <span class="Type">character</span><span class="Special">;</span>
<span class="Statement">type</span> <span class="Type">bit_vector</span> <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span> <span class="Type">natural</span> <span class="Statement">range</span> <span class="Special"><></span> <span class="Special">)</span> <span class="Statement">of</span> <span class="Type">bit</span><span class="Special">;</span>
The types positive and natural are subtypes of integer, defined in Section2.2.7 below. The type bit_vector is particularly useful in modelling binary coded representations of values in simulations of digital systems.
An element of an array object can referred to by indexing the name of the object. For example, suppose a and b are one- and two-dimensional array objects respectively. Then the indexed names a(1) and b(1, 1) refer to elements of these arrays. Furthermore, a contiguous slice of a one dimensional array can be referred to by using a range as an index. For example a(8 to 15) is an eight-element array which is part of the array a.
Sometimes you may need to write a literal value of an array type. This can be done using an array aggregate, which is a list of element values. Suppose we have an array type declared as:
<span class="Statement">type</span> a <span class="Statement">is</span> <span class="Statement">array</span> <span class="Special">(</span><span class="Constant">1</span> <span class="Statement">to</span> <span class="Constant">4</span><span class="Special">)</span> <span class="Statement">of</span> <span class="Type">character</span><span class="Special">;</span>
and we want to write a value of this type containing the elements 'f', 'o', 'o', 'd' in that order. We could write an aggregate with positional association as follows:
<span class="Special">(</span><span class="Constant">'f'</span><span class="Special">,</span> <span class="Constant">'o'</span><span class="Special">,</span> <span class="Constant">'o'</span><span class="Special">,</span> <span class="Constant">'d'</span><span class="Special">)</span>
in which the elements are listed in the order of the index range, starting with the left bound of the range. Alternatively, we could write an aggregate with named association:
<span class="Special">(</span><span class="Constant">1</span> <span class="Statement">=></span> <span class="Constant">'f'</span><span class="Special">,</span> <span class="Constant">3</span> <span class="Statement">=></span> <span class="Constant">'o'</span><span class="Special">,</span> <span class="Constant">4</span> <span class="Statement">=></span> <span class="Constant">'d'</span><span class="Special">,</span> <span class="Constant">2</span> <span class="Statement">=></span> <span class="Constant">'o'</span><span class="Special">)</span>
In this case, the index for each element is explicitly given, so the elements can be in any order. Positional and named association can be mixed within an aggregate, provided all the positional associations come first. Also, the word others can be used in place of an index in a named association, indicating a value to be used for all elements not explicitly mentioned. For example, the same value as above could be written as:
<span class="Special">(</span><span class="Constant">'f'</span><span class="Special">,</span> <span class="Constant">4</span> <span class="Statement">=></span> <span class="Constant">'d'</span><span class="Special">,</span> <span class="Statement">others</span> <span class="Statement">=></span> <span class="Constant">'o'</span><span class="Special">)</span>
<h4>2.2.6. Records</h4>
VHDL provides basic facilities for records, which are collections of named elements of possibly different types. The syntax for declaring record types is:
<span class="Constant">record_type_definition </span><span class="PreProc">::=</span>
<span class="Statement"> record</span>
<span class="Statement"> </span><span class="bnfLine">element_declaration</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">element_declaration</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Statement"> end record </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>record_type</i>_simple_name</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">element_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier_list</span><span class="Statement"> : </span><span class="bnfLine">element_subtype_definition</span><span class="Statement"> ;</span>
<span class="Constant">identifier_list </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">identifier</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">element_subtype_definition </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">subtype_indication</span>
An example record type declaration:
<span class="Statement">type</span> instruction <span class="Statement">is</span>
<span class="Statement">record</span>
op_code : processor_op<span class="Special">;</span>
address_mode : mode<span class="Special">;</span>
operand1<span class="Special">,</span> operand2: <span class="Type">integer</span> <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> <span class="Constant">15</span><span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">record</span> <span class="Special">;</span>
When you need to refer to a field of a record object, you use a selected name. For example, suppose that r is a record object containing a field called f. Then the name r.f refers to that field.
As for arrays, aggregates can be used to write literal values for records. Both positional and named association can be used, and the same rules apply, with record field names being used in place of array index names.
<h4>2.2.7. Subtypes</h4>
The use of a subtype allows the values taken on by an object to be restricted or constrained subset of some base type. The syntax for declaring a subtype is:
<span class="Constant">subtype_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> subtype </span><span class="bnfLine">identifier</span><span class="Statement"> is </span><span class="bnfLine">subtype_indication</span><span class="Statement"> ;</span>
<span class="Constant">subtype_indication </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>resolution_function</i>_name</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">constraint</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">type_mark </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>type</i>_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>subtype</i>_name</span>
<span class="Constant">constraint </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">range_constraint</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">index_constraint</span>
There are two cases of subtypes. Firstly a subtype may constrain values from a scalar type to be within a specified range (a range constraint). For example:
<span class="Statement">subtype</span> pin_count <span class="Statement">is</span> <span class="Type">integer</span> <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> <span class="Constant">400</span><span class="Special">;</span>
<span class="Statement">subtype</span> digits <span class="Statement">is</span> <span class="Type">character</span> <span class="Statement">range</span> <span class="Constant">'0'</span> <span class="Statement">to</span> <span class="Constant">'9'</span><span class="Special">;</span>
Secondly, a subtype may constrain an otherwise unconstrained array
<span class="Statement">type</span> by specifying bounds <span class="Statement">for</span> the indices<span class="Special">.</span> <span class="Statement">For</span> example:
<span class="Statement">subtype</span> id <span class="Statement">is</span> <span class="Type">string</span><span class="Special">(</span><span class="Constant">1</span> <span class="Statement">to</span> <span class="Constant">20</span><span class="Special">);</span>
<span class="Statement">subtype</span> word <span class="Statement">is</span> <span class="Type">bit_vector</span><span class="Special">(</span><span class="Constant">31</span> <span class="Statement">downto</span> <span class="Constant">0</span><span class="Special">);</span>
There are two predefined numeric subtypes, defined as:
<span class="Statement">subtype</span> <span class="Type">natural</span> <span class="Statement">is</span> <span class="Type">integer</span> <span class="Statement">range</span> <span class="Constant">0</span> <span class="Statement">to</span> highest_integer
<span class="Statement">subtype</span> <span class="Type">positive</span> <span class="Statement">is</span> <span class="Type">integer</span> <span class="Statement">range</span> <span class="Constant">1</span> <span class="Statement">to</span> highest_integer
<h4>2.2.8. Object Declarations</h4>
An object is a named item in a VHDL description which has a value of a specified type. There are three classes of objects: constants, variables and signals. Only the first two will be discusses in this section; signals will be covered in Section3.2.1. Declaration and use of constants and variables is very much like their use in programming languages.
A constant is an object which is initialised to a specified value when it is created, and which may not be subsequently modified. The syntax of a constant declaration is:
<span class="Constant">constant_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> constant </span><span class="bnfLine">identifier_list</span><span class="Statement"> : </span><span class="bnfLine">subtype_indication</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> := </span><span class="bnfLine">expression</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
Constant declarations with the initialising expression missing are called deferred constants, and may only appear in package declarations (see Section2.5.3). The initial value must be given in the corresponding package body. Some examples:
<span class="Statement">constant</span> e : <span class="Type">real</span> <span class="Statement">:=</span> <span class="Constant">2.71828</span><span class="Special">;</span>
<span class="Statement">constant</span> delay : <span class="Type">Time</span> <span class="Statement">:=</span> <span class="Constant">5 ns</span><span class="Special">;</span>
<span class="Statement">constant</span> max_size : <span class="Type">natural</span><span class="Special">;</span>
A variable is an object whose value may be changed after it is created. The syntax for declaring variables is:
<span class="Constant">variable_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> shared </span><span class="bnfOr">]</span><span class="Statement"> variable </span><span class="bnfLine">identifier_list</span><span class="Statement"> : </span><span class="bnfLine">subtype_indication</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> := </span><span class="bnfLine">expression</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
The initial value expression, if present, is evaluated and assigned to the variable when it is created. If the expression is absent, a default value is assigned when the variable is created. The default value for scalar types is the leftmost value for the type, that is the first in the list of an enumeration type, the lowest in an ascending range, or the highest in a descending range. If the variable is a composite type, the default value is the composition of the default values for each element, based on the element types.
Some examples of variable declarations:
<span class="Statement">variable</span> count : <span class="Type">natural</span> <span class="Statement">:=</span> <span class="Constant">0</span><span class="Special">;</span>
<span class="Statement">variable</span> trace : trace_array<span class="Special">;</span>
Assuming the type trace_array is an array of boolean, then the initial value of the variable trace is an array with all elements having the value false.
Given an existing object, it is possible to give an alternate name to the object or part of it. This is done using and alias declaration. The syntax is:
<span class="Constant">alias_declaration </span><span class="PreProc">::=</span>
<span class="Statement"> alias </span><span class="bnfLine">alias_designator</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> : </span><span class="bnfLine">subtype_indication</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> is </span><span class="bnfLine">name</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">signature</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
<span class="Constant">alias_designator </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">character_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">operator_symbol</span>
A reference to an alias is interpreted as a reference to the object or part corresponding to the alias. For example:
<span class="Statement">variable</span> instr : <span class="Type">bit_vector</span><span class="Special">(</span><span class="Constant">31</span> <span class="Statement">downto</span> <span class="Constant">0</span><span class="Special">);</span>
<span class="Statement">alias</span> op_code : <span class="Type">bit_vector</span><span class="Special">(</span><span class="Constant">7</span> <span class="Statement">downto</span> <span class="Constant">0</span><span class="Special">)</span> <span class="Statement">is</span> instr<span class="Special">(</span><span class="Constant">31</span> <span class="Statement">downto</span> <span class="Constant">24</span><span class="Special">);</span>
declares the name op_code to be an alias for the left-most eight bits of instr.
<h4>2.2.9. Attributes</h4>
Types and objects declared in a VHDL description can have additional information, called attributes, associated with them. There are a number of standard pre-defined attributes, and some of those for types and arrays are discussed here. An attribute is referenced using the ‘'’ notation. For example,
thing'attr
refers to the attribute attr of the type or object thing.
Firstly, for any scalar type or subtype T, the following attributes can be used:
T<span class="Special">'left</span><span class="Comment"> -- Left bound of T</span>
T<span class="Special">'right</span><span class="Comment"> -- Right bound of T</span>
T<span class="Special">'low</span><span class="Comment"> -- Lower bound of T</span>
T<span class="Special">'high</span><span class="Comment"> -- Upper bound of T</span>
For an ascending range, T'left = T'low, and T'right = T'high. For a descending range, T'left = T'high, and T'right = T'low.
Secondly, for any discrete or physical type or subtype T, X a member of T, and N an integer, the following attributes can be used:
T<span class="Special">'pos</span><span class="Special">(</span>X<span class="Special">)</span><span class="Comment"> -- Position number of X in T</span>
T<span class="Special">'val</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Value at position N in T</span>
T<span class="Special">'leftof</span><span class="Special">(</span>X<span class="Special">)</span><span class="Comment"> -- Value in T which is one position left from X</span>
T<span class="Special">'rightof</span><span class="Special">(</span>X<span class="Special">)</span><span class="Comment"> -- Value in T which is one position right from X</span>
T<span class="Special">'pred</span><span class="Special">(</span>X<span class="Special">)</span><span class="Comment"> -- Value in T which is one position lower than X</span>
T<span class="Special">'succ</span><span class="Special">(</span>X<span class="Special">)</span><span class="Comment"> -- Value in T which is one position higher than X</span>
For an ascending range, T'leftof(X) = T'pred(X), and T'rightof(X) = T'succ(X). For a descending range, T'leftof(X) = T'succ(X), and T'rightof(X) = T'pred(X).
Thirdly, for any array type or object A, and N an integer between 1 and the number of dimensions of A, the following attributes can be used:
A<span class="Special">'left</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Left bound of index range of dim’n N of A</span>
A<span class="Special">'right</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Right bound of index range of dim’n N of A</span>
A<span class="Special">'low</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Lower bound of index range of dim’n N of A</span>
A<span class="Special">'high</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Upper bound of index range of dim’n N of A</span>
A<span class="Special">'range</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Index range of dim’n N of A</span>
A<span class="Special">'reverse_range</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Reverse of index range of dim’n N of A</span>
A<span class="Special">'length</span><span class="Special">(</span>N<span class="Special">)</span><span class="Comment"> -- Length of index range of dim’n N of A</span>
<h3>2.3. Expressions and Operators</h3>
Expressions in VHDL are much like expressions in other programming languages. An expression is a formula combining primaries with operators. Primaries include names of objects, literals, function calls and parenthesised expressions. Operators are listed in Table 2-1 in order of decreasing precedence.
<span class="Statement">**</span> <span class="Statement">abs</span> <span class="Statement">not</span>
<span class="Statement">*</span> <span class="Statement">/</span> <span class="Statement">mod</span> <span class="Statement">rem</span>
<span class="Statement">+</span> <span class="Special">(</span>sign<span class="Special">)</span> <span class="Statement">-</span> <span class="Special">(</span>sign<span class="Special">)</span>
<span class="Statement">+</span> <span class="Statement">-</span> <span class="Statement">&</span>
<span class="Statement">=</span> <span class="Statement">/=</span> <span class="Statement"><</span> <span class="Statement"><=</span> <span class="Statement">></span> <span class="Statement">>=</span>
<span class="Statement">and</span> <span class="Statement">or</span> <span class="Statement">nor</span> <span class="Statement">xor</span> <span class="Statement">nand</span>
Table 2-1. Operators and precedence.
The logical operators and, or, nand, nor, xor and not operate on values of type bit or boolean, and also on one-dimensional arrays of these types. For array operands, the operation is applied between corresponding elements of each array, yielding an array of the same length as the result. For bit and boolean operands, and , or, nand, and nor are ‘short-circuit’ operators, that is they only evaluate their right operand if the left operand does not determine the result. So and and nand only evaluate the right operand if the left operand is true or '1', and or and nor only evaluate the right operand if the left operand is false or '0'.
The relational operators =, /=, <, <=, > and >= must have both operands of the same type, and yield boolean results. The equality operators (= and /=) can have operands of any type. For composite types, two values are equal if all of their corresponding elements are equal. The remaining operators must have operands which are scalar types or one-dimensional arrays of discrete types.
The sign operators (+ and –) and the addition (+) and subtraction (–) operators have their usual meaning on numeric operands. The concatenation operator (&) operates on one-dimensional arrays to form a new array with the contents of the right operand following the contents of the left operand. It can also concatenate a single new element to an array, or two individual elements to form an array. The concatenation operator is most commonly used with strings.
The multiplication (*) and division (/) operators work on integer, floating point and physical types types. The modulus (mod) and remainder (rem) operators only work on integer types. The absolute value (abs) operator works on any numeric type. Finally, the exponentiation (**) operator can have an integer or floating point left operand, but must have an integer right operand. A negative right operand is only allowed if the left operand is a floating point number.
The complete syntax for VHDL expression follows:
<span class="Constant">expression </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> and </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> or </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> xor </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> nand </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> nor </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> xnor </span><span class="bnfLine">relation</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">relation </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">shift_expression</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">relational_operator</span><span class="Statement"> </span><span class="bnfLine">shift_expression</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">shift_expression </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">simple_expression</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">shift_operator</span><span class="Statement"> </span><span class="bnfLine">simple_expression</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">simple_expression </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">sign</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">term</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">adding_operator</span><span class="Statement"> </span><span class="bnfLine">term</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">sign </span><span class="PreProc">::=</span>
<span class="Statement"> + </span><span class="bnfOr">|</span><span class="Statement"> -</span>
<span class="Constant">term </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">factor</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">multiplying_operator</span><span class="Statement"> </span><span class="bnfLine">factor</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">factor </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">primary</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> ** </span><span class="bnfLine">primary</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> abs </span><span class="bnfLine">primary</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> not </span><span class="bnfLine">primary</span>
<span class="Constant">primary </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">literal</span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">aggregate</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">function_call</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">qualified_expression</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">type_conversion</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">allocator</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> ( </span><span class="bnfLine">expression</span><span class="Statement"> )</span>
<span class="Constant">name </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">simple_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">operator_symbol</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">selected_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">indexed_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">slice_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">attribute_name</span>
<span class="Constant">simple_name </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span>
<span class="Constant">operator_symbol </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">string_literal</span>
<span class="Constant">selected_name </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">prefix</span><span class="Statement"> . </span><span class="bnfLine">suffix</span>
<span class="Constant">prefix </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">function_call</span>
<span class="Constant">function_call </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>function</i>_name</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> ( </span><span class="bnfLine">actual_parameter_part</span><span class="Statement"> ) </span><span class="bnfOr">]</span>
<span class="Constant">actual_parameter_part </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>parameter</i>_association_list</span>
<span class="Constant">association_list </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">association_element</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">association_element</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">association_element </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">formal_part</span><span class="Statement"> => </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">actual_part</span>
<span class="Constant">formal_part </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">formal_designator</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>function</i>_name</span><span class="Statement"> ( </span><span class="bnfLine">formal_designator</span><span class="Statement"> ) </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> ( </span><span class="bnfLine">formal_designator</span><span class="Statement"> )</span>
<span class="Constant">formal_designator </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>generic</i>_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>port</i>_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>parameter</i>_name</span>
<span class="Constant">actual_part </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">actual_designator</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>function</i>_name</span><span class="Statement"> ( </span><span class="bnfLine">actual_designator</span><span class="Statement"> ) </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> ( </span><span class="bnfLine">actual_designator</span><span class="Statement"> )</span>
<span class="Constant">actual_designator </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">expression</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>signal</i>_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>variable</i>_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>file</i>_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> open</span>
<span class="Constant">suffix </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">simple_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">character_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">operator_symbol</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> all</span>
<span class="Constant">indexed_name </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">prefix</span><span class="Statement"> ( </span><span class="bnfLine">expression</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">expression</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> )</span>
<span class="Constant">slice_name </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">prefix</span><span class="Statement"> ( </span><span class="bnfLine">discrete_range</span><span class="Statement"> )</span>
<span class="Constant">discrete_range </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>discrete</i>_subtype_indication</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">range_term</span>
<span class="Constant">attribute_name </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">prefix</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">signature</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ' </span><span class="bnfLine">attribute_designator</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> ( </span><span class="bnfLine">expression</span><span class="Statement"> ) </span><span class="bnfOr">]</span>
<span class="Constant">signature </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> </span><span class="bnfLine">{</span><span class="Statement"> , </span><span class="bnfLine">type_mark</span><span class="Statement"> </span><span class="bnfLine">}</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> return </span><span class="bnfLine">type_mark</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Constant">attribute_designator </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine"><i>attribute</i>_simple_name</span>
<span class="Constant">literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">numeric_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">enumeration_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">string_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">bit_string_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> null</span>
<span class="Constant">numeric_literal </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">abstract_literal</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">physical_literal</span>
<span class="Constant">aggregate </span><span class="PreProc">::=</span>
<span class="Statement"> ( </span><span class="bnfLine">element_association</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> , </span><span class="bnfLine">element_association</span><span class="Statement"> </span><span class="bnfOr">}</span><span class="Statement"> )</span>
<span class="Constant">element_association </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">choices</span><span class="Statement"> => </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">expression</span>
<span class="Constant">qualified_expression </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> ' ( </span><span class="bnfLine">expression</span><span class="Statement"> ) </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> ' </span><span class="bnfLine">aggregate</span>
<span class="Constant">type_conversion </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">type_mark</span><span class="Statement"> ( </span><span class="bnfLine">expression</span><span class="Statement"> )</span>
<span class="Constant">allocator </span><span class="PreProc">::=</span>
<span class="Statement"> new </span><span class="bnfLine">subtype_indication</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> new </span><span class="bnfLine">qualified_expression</span>
<span class="Constant">multiplying_operator </span><span class="PreProc">::=</span>
<span class="Statement"> * </span><span class="bnfOr">|</span><span class="Statement"> / </span><span class="bnfOr">|</span><span class="Statement"> mod </span><span class="bnfOr">|</span><span class="Statement"> rem</span>
<span class="Constant">adding_operator </span><span class="PreProc">::=</span>
<span class="Statement"> + </span><span class="bnfOr">|</span><span class="Statement"> - </span><span class="bnfOr">|</span><span class="Statement"> &</span>
<span class="Constant">shift_operator </span><span class="PreProc">::=</span>
<span class="Statement"> sll </span><span class="bnfOr">|</span><span class="Statement"> </span><span class="Comment">-- (L := (L[L'length - 1, 0] & T'left)) x R</span>
<span class="Statement"> srl </span><span class="bnfOr">|</span><span class="Statement"> </span><span class="Comment">-- (L := (T'left & L[L'length - 1, 0])) x R</span>
<span class="Statement"> sla </span><span class="bnfOr">|</span><span class="Statement"> </span><span class="Comment">-- (L := (L[L'length - 1, 0] & L(L'right))) x R</span>
<span class="Statement"> sra </span><span class="bnfOr">|</span><span class="Statement"> </span><span class="Comment">-- (L := (L(L'left) & L[L'length - 1, 0])) x R</span>
<span class="Statement"> rol </span><span class="bnfOr">|</span><span class="Statement"> </span><span class="Comment">-- (L := (L[L'length - 1, 0] & L(L'left))) x R</span>
<span class="Statement"> ror </span><span class="Comment">-- (L := (L(L'right) & L[L'length - 1, 0])) x R</span>
<span class="Constant">relational_operator </span><span class="PreProc">::=</span>
<span class="Statement"> = </span><span class="bnfOr">|</span><span class="Statement"> /= </span><span class="bnfOr">|</span><span class="Statement"> < </span><span class="bnfOr">|</span><span class="Statement"> <= </span><span class="bnfOr">|</span><span class="Statement"> > </span><span class="bnfOr">|</span><span class="Statement"> >=</span>
<h3>2.4. Sequential Statements</h3>
VHDL contains a number of facilities for modifying the state of objects and controlling the flow of execution of models. These are discussed in this section.
<h4>2.4.1. Variable Assignment</h4>
As in other programming languages, a variable is given a new value using an assignment statement. The syntax is:
<span class="Constant">variable_assignment_statement </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">label</span><span class="Statement">: </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfLine">target</span><span class="Statement"> := </span><span class="bnfLine">expression</span><span class="Statement"> ;</span>
<span class="Constant">label </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span>
<span class="Constant">target </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">aggregate</span>
In the simplest case, the target of the assignment is an object name, and the value of the expression is given to the named object. The object and the value must have the same base type.
If the target of the assignment is an aggregate, then the elements listed must be object names, and the value of the expression must be a composite value of the same type as the aggregate. Firstly, all the names in the aggregate are evaluated, then the expression is evaluated, and lastly the components of the expression value are assigned to the named variables. This is effectively a parallel assignment. For example, if a variable r is a record with two fields a and b, then they could be exchanged by writing
<span class="Special">(</span>a <span class="Statement">=></span> r<span class="Special">.</span>b<span class="Special">,</span> b <span class="Statement">=></span> r<span class="Special">.</span>a<span class="Special">)</span> <span class="Statement">:=</span> r
(Note that this is an example to illustrate how such an assignment works; it is not an example of good programming practice!)
<h4>2.4.2. If Statement</h4>
The if statement allows selection of statements to execute depending on one or more conditions. The syntax is:
<span class="Constant">if_statement </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>if</i>_label</span><span class="Statement"> : </span><span class="bnfOr">]</span><span class="Statement"> if </span><span class="bnfLine">condition</span><span class="Statement"> then </span><span class="bnfLine">sequence_of_statements</span>
<span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> elsif </span><span class="bnfLine">condition</span><span class="Statement"> then </span><span class="bnfLine">sequence_of_statements</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> else </span><span class="bnfLine">sequence_of_statements</span><span class="Statement"> </span><span class="bnfOr">]</span>
<span class="Statement"> end if </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>if</i>_label</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
The conditions are expressions resulting in boolean values. The conditions are evaluated successively until one found that yields the value true. In that case the corresponding statement list is executed. Otherwise, if the else clause is present, its statement list is executed.
<h4>2.4.3. Case Statement</h4>
The case statement allows selection of statements to execute depending on the value of a selection expression. The syntax is:
<span class="Constant">case_statement </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>case</i>_label</span><span class="Statement"> : </span><span class="bnfOr">]</span><span class="Statement"> case </span><span class="bnfLine">expression</span><span class="Statement"> is</span>
<span class="Statement"> </span><span class="bnfLine">case_statement_alternative</span>
<span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">case_statement_alternative</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Statement"> end case </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>case</i>_label</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
<span class="Constant">case_statement_alternative </span><span class="PreProc">::=</span>
<span class="Statement"> when </span><span class="bnfLine">choices</span><span class="Statement"> => </span><span class="bnfLine">sequence_of_statements</span>
<span class="Constant">choices </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">choice</span><span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfOr">|</span><span class="Statement"> </span><span class="bnfLine">choice</span><span class="Statement"> </span><span class="bnfOr">}</span>
<span class="Constant">choice </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">simple_expression</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine">discrete_range</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> </span><span class="bnfLine"><i>element</i>_simple_name</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> others</span>
The selection expression must result in either a discrete type, or a one dimensional array of characters. The alternative whose choice list includes the value of the expression is selected and the statement list executed. Note that all the choices must be distinct, that is, no value may be duplicated. Furthermore, all values must be represented in the choice lists, or the special choice others must be included as the last alternative. If no choice list includes the value of the expression, the others alternative is selected. If the expression results in an array, then the choices may be strings or bit strings.
Some examples of case statements:
<span class="Statement">case</span> element_colour <span class="Statement">of</span>
<span class="Statement">when</span> red <span class="Statement">=></span> statements <span class="Statement">for</span> red<span class="Special">;</span>
<span class="Statement">when</span> green | blue <span class="Statement">=></span> statements <span class="Statement">for</span> green <span class="Statement">or</span> blue<span class="Special">;</span>
<span class="Statement">when</span> orange <span class="Statement">to</span> turquoise <span class="Statement">=></span> statements <span class="Statement">for</span> these colours<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">case</span> <span class="Special">;</span>
<span class="Statement">case</span> opcode <span class="Statement">of</span>
<span class="Statement">when</span> <span class="Constant">X"00"</span> <span class="Statement">=></span> perform_add<span class="Special">;</span>
<span class="Statement">when</span> <span class="Constant">X"01"</span> <span class="Statement">=></span> perform_subtract<span class="Special">;</span>
<span class="Statement">when</span> <span class="Statement">others</span> <span class="Statement">=></span> signal_illegal_opcode<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">case</span> <span class="Special">;</span>
<h4>2.4.4. Loop Statements</h4>
VHDL has a basic loop statement, which can be augmented to form the usual while and for loops seen in other programming languages. The syntax of the loop statement is:
<span class="Constant">loop_statement </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>loop</i>_label</span><span class="Statement"> : </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">iteration_scheme</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> loop</span>
<span class="Statement"> </span><span class="bnfLine">sequence_of_statements</span>
<span class="Statement"> end loop </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>loop</i>_label</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
<span class="Constant">iteration_scheme </span><span class="PreProc">::=</span>
<span class="Statement"> while </span><span class="bnfLine">condition</span><span class="Statement"> </span><span class="bnfOr">|</span>
<span class="Statement"> for </span><span class="bnfLine"><i>loop</i>_parameter_specification</span>
<span class="Constant">parameter_specification </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfLine">identifier</span><span class="Statement"> in </span><span class="bnfLine">discrete_range</span>
<span class="Constant">sequence_of_statements </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">{</span><span class="Statement"> </span><span class="bnfLine">sequential_statement</span><span class="Statement"> </span><span class="bnfOr">}</span>
If the iteration scheme is omitted, we get a loop which will repeat the enclosed statements indefinitely. An example of such a basic loop is:
<span class="Statement">loop</span>
do_something<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">loop</span> <span class="Special">;</span>
The while iteration scheme allows a test condition to be evaluated before each iteration. The iteration only proceeds if the test evaluates to true. If the test is false, the loop statement terminates. An example:
<span class="Statement">while</span> index <span class="Statement"><</span> length <span class="Statement">and</span> str<span class="Special">(</span>index<span class="Special">)</span> <span class="Statement">/=</span> <span class="Constant">' '</span> <span class="Statement">loop</span>
index <span class="Statement">:=</span> index <span class="Statement">+</span> <span class="Constant">1</span><span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">loop</span><span class="Special">;</span>
The for iteration scheme allows a specified number of iterations. The loop parameter specification declares an object which takes on successive values from the given range for each iteration of the loop. Within the statements enclosed in the loop, the object is treated as a constant, and so may not be assigned to. The object does not exist beyond execution of the loop statement. An example:
<span class="Statement">for</span> item <span class="Statement">in</span> <span class="Constant">1</span> <span class="Statement">to</span> last_item <span class="Statement">loop</span>
table<span class="Special">(</span>item<span class="Special">)</span> <span class="Statement">:=</span> <span class="Constant">0</span><span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">loop</span> <span class="Special">;</span>
There are two additional statements which can be used inside a loop to modify the basic pattern of iteration. The ‘next’ statement terminates execution of the current iteration and starts the subsequent iteration. The ‘exit’ statement terminates execution of the current iteration and terminates the loop. The syntax of these statements is:
<span class="Constant">next_statement </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">label</span><span class="Statement">: </span><span class="bnfOr">]</span><span class="Statement"> next </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>loop</i>_label</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> when </span><span class="bnfLine">condition</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
<span class="Constant">exit_statement </span><span class="PreProc">::=</span>
<span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine">label</span><span class="Statement">: </span><span class="bnfOr">]</span><span class="Statement"> exit </span><span class="bnfOr">[</span><span class="Statement"> </span><span class="bnfLine"><i>loop</i>_label</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> </span><span class="bnfOr">[</span><span class="Statement"> when </span><span class="bnfLine">condition</span><span class="Statement"> </span><span class="bnfOr">]</span><span class="Statement"> ;</span>
If the loop label is omitted, the statement applies to the inner-most enclosing loop, otherwise it applies to the named loop. If the when clause is present but the condition is false, the iteration continues normally. Some examples:
<span class="Statement">for</span> i <span class="Statement">in</span> <span class="Constant">1</span> <span class="Statement">to</span> max_str_len <span class="Statement">loop</span>
a<span class="Special">(</span>i<span class="Special">)</span> <span class="Statement">:=</span> buf<span class="Special">(</span>i<span class="Special">);</span>
<span class="Statement">exit</span> <span class="Statement">when</span> buf<span class="Special">(</span>i<span class="Special">)</span> <span class="Statement">=</span> NUL<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">loop</span><span class="Special">;</span>
outer_loop: <span class="Statement">loop</span>
inner_loop: <span class="Statement">loop</span>
do_something<span class="Special">;</span>
<span class="Statement">next</span> outer_loop <span class="Statement">when</span> temp <span class="Statement">=</span> <span class="Constant">0</span><span class="Special">;</span>
do_something_else<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">loop</span> inner_loop<span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">loop</span> outer_loop<span class="Special">;</span>
<h4>2.4.5. Null Statement</h4>
The null statement has no effect. It may be used to explicitly show that no action is required in certain cases. It is most often used in case statements, where all possible values of the selection expression must be listed as choices, but for some choices no action is required. For example:
<span class="Statement">case</span> controller_command <span class="Statement">is</span>
<span class="Statement">when</span> forward <span class="Statement">=></span> engage_motor_forward<span class="Special">;</span>
<span class="Statement">when</span> reverse <span class="Statement">=></span> engage_motor_reverse<span class="Special">;</span>
<span class="Statement">when</span> idle <span class="Statement">=></span> <span class="Statement">null</span><span class="Special">;</span>
<span class="Statement">end</span> <span class="Statement">case</span><span class="Special">;</span>