SMT based Standard Cell Layout Generator

This GitHub repo provides the C++ version SMT based standard cell layout generator.

The layout generation flow is shown in the below flow chart.

User Notes (for Installation)

• For dependency to fmt. Follow the installation guide here: fmt.
• For dependency to jsoncpp. Follow the installation guide here: jsoncpp.
• For dependency to boost_regex. Follow the installation guide here: boost_regex.

Run Guide

• Generate program files (Compile C++ codes)

# Compile genTestCase
make genTestCase

# Compile genSMTInput
make genSMTInput

# Compile convSMTResult
make convSMTResult

# Compile all three
make all

• Run program files

# Run genTestCase
./genTestCase {netlist_file} {size_offset} {fin_mode}
  - ex. ./genTestCase ./netlists/PROBE_3F.cdl 13 3
  - The cell list must be defined in the 'genTestCase.cpp' before compiling.
  
# Run genSMTInput
./genSMTInput {pinLayout_file} {json_file}
  - ex. ./genSMTInput ./pinLayouts_3F_5T/AND2_X1.pinLayout ./config/config_3F_5T_EL.json
  
# Run convSMTResult
./convSMTResult {Z3_file} {cell_name} {output_directory} {pinLayout_directory}
  - ex. ./convSMTResult ./Z3/XOR2_X1_3F_5T_ET_MPO2.z3 XOR2_X1 ./solutionSMT ./pinLayouts_3F_5T

Past & Related Repository

• FinFET Based
  • SMT-based-STDCELL-Layout-Generator [Link]
  • SMT-based-STDCELL-Layout-Generator-for-PROBE2.0 [Link]
• VFET Based
  • SMT-based-STDCELL-Layout-Generator-for-VFET [Link]
• CFET Based
  • SMT-based-STDCELL-Layout-Generator-for-CFET (Pending Open Source) [Link]
• PROBE3.0
  • Design-Technology pathfinding framework incorporating the SMT based cell layout generator [Link]

Knowledge Reference

• Park, Dong Won Dissertation: Logical Reasoning Techniques for Physical Layout in Deep Nanometer Technologies
• Ho, Chia-Tung Dissertation: Novel Computer Aided Design (CAD) Methodology for Emerging Technologies to Fight the Stagnation of Moore¡¯s Law
• D. Park, I. Kang, Y. Kim, S. Gao, B. Lin, and C.K. Cheng, "ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques," ACM/IEEE Int. Symp. on Physical Design, pp. 65-72, 2019. [Paper] [Slides]
• D. Park, D. Lee, I. Kang, S. Gao, B. Lin, C.K. Cheng, "SP&R: Simultaneous Placement and Routing Framework for Standard Cell Synthesis in Sub-7nm," IEEE Asia and South Pacific Design Automation, pp. 345-350, 2020. [Paper] [Slides]
• C.K. Cheng, C. Ho, D. Lee, and D. Park, "A Routability-Driven Complimentary-FET (CFET) Standard Cell Synthesis Framework using SMT," ACM/IEEE Int. Conf. on Computer-Aided Design, pp. 1-8, 2020. [Paper]
• D. Lee, C.T. Ho, I. Kang, S. Gao, B. Lin, and C.K. Cheng, "Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2021, Open Access. [Paper]
• C.K. Cheng, C.T. Ho, D. Lee, and B. Lin, "Multi-row Complementary-FET (CFET) Standard Cell Synthesis Framework using Satisfiability Modulo Theories (SMT)," IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2021, Open Access. [Paper]