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BUG: Use standard pathway to create inputs in parse_wiring_diagram.
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epatters committed Jan 27, 2020
1 parent 1fc4096 commit 223fa72
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions src/programs/JuliaPrograms.jl
Original file line number Diff line number Diff line change
Expand Up @@ -256,7 +256,6 @@ function parse_wiring_diagram(pres::Presentation, call::Expr0, body::Expr)::Wiri

# FIXME: Presentations should be uniquely associated with syntax systems.
syntax_module = Syntax.syntax_module(first(pres.generators))
signature_module = syntax_module.signature()

# Compile...
args = first.(parsed_args)
Expand All @@ -266,9 +265,10 @@ function parse_wiring_diagram(pres::Presentation, call::Expr0, body::Expr)::Wiri
func = eval(func_expr)

# ...and then evaluate function that records the function calls.
inputs = last.(parsed_args)
@assert all(has_generator(pres, name) for name in inputs)
diagram = WiringDiagram{signature_module.Hom}(inputs, empty(inputs))
arg_types = last.(parsed_args)
arg_obs = syntax_module.Ob[ generator(pres, name) for name in arg_types ]
inputs = to_wiring_diagram(otimes(arg_obs))
diagram = WiringDiagram(inputs, munit(typeof(inputs)))
v_in, v_out = input_id(diagram), output_id(diagram)
in_ports = [ Port(v_in, OutputPort, i) for i in eachindex(inputs) ]
recorder = f -> (args...) -> record_call!(diagram, f, args...)
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