floats: Add fcvt instructions for doubles, and fix their overflow behaviour to reflect the spec #53
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AntonLydike
added
bug
superlopuh
reviewed
May 14, 2024
riscemu/core/int32.py
Outdated
| @@ -284,3 +308,6 @@ def shift_right_logical(self, amount: Union["Int32", int]) -> "UInt32": | |||
| if isinstance(amount, Int32): | |||
| amount = amount.value | |||
| return UInt32(self.value >> amount) | |||
|
|
|||
| def signed(self) -> "Int32": | |||
| return Int32(self) | |||
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How should this handle overflow/negative values? It may be worth making this explicit.
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The ctypes.c_[u]int32 this wraps handles them natively when constructing a c_int32 from a c_uint32. I can make it more explicit by passing the ctypes type!
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This adds
fcvt.d.w[u]andfcvt.w[u].dinstructions, and fixes thefcvt.s.w[u]andfcvt.w[u].sinstructions overflow behavior to correctly reflect the spec (Thanks Markus Böck for digging this out, as it's a bit difficult to find in the spec itself).This also fixes a long standing bug in the way registers are stored that would introduce bugs in certain edge cases (registers are now always treated as signed values, just as the code expects in most places).
Pre-Merge Checklist:
CHANGELOG.md