Add support for booting on T8012 (T2) SoC

Makefile

@@ -95,7 +95,7 @@ OBJECTS := \
 	afk.o \
 	aic.o \
 	asc.o \
-	bootlogo_128.o bootlogo_256.o \
+	bootlogo_48.o bootlogo_128.o bootlogo_256.o \
 	chainload.o \
 	chainload_asm.o \
 	chickens.o \

data/makelogo.sh

@@ -1,3 +1,4 @@
 #!/usr/bin/env sh
+convert bootlogo_48.png -background black -flatten -depth 8 rgba:bootlogo_48.bin
 convert bootlogo_128.png -background black -flatten -depth 8 rgba:bootlogo_128.bin
 convert bootlogo_256.png -background black -flatten -depth 8 rgba:bootlogo_256.bin

src/fb.c

@@ -44,12 +44,19 @@ static struct {
     bool active;
 } console;
 
+extern u8 _binary_build_bootlogo_48_bin_start[];
 extern u8 _binary_build_bootlogo_128_bin_start[];
 extern u8 _binary_build_bootlogo_256_bin_start[];
 
 extern u8 _binary_build_font_bin_start[];
 extern u8 _binary_build_font_retina_bin_start[];
 
+const struct image logo_48 = {
+    .ptr = (void *)_binary_build_bootlogo_48_bin_start,
+    .width = 48,
+    .height = 48,
+};
+
 const struct image logo_128 = {
     .ptr = (void *)_binary_build_bootlogo_128_bin_start,
     .width = 128,
@@ -409,7 +416,13 @@ void fb_init(bool clear)
     fb.ptr = malloc(fb.size);
     memcpy(fb.ptr, fb.hwptr, fb.size);
 
-    if (cur_boot_args.video.depth & FB_DEPTH_FLAG_RETINA) {
+    // This is the touchbar, make everything tiny
+    if (chip_id == T8012) {
+        logo = &logo_48;
+        console.font.ptr = _binary_build_font_bin_start;
+        console.font.width = 8;
+        console.font.height = 16;
+    } else if (cur_boot_args.video.depth & FB_DEPTH_FLAG_RETINA) {
         logo = &logo_256;
         console.font.ptr = _binary_build_font_retina_bin_start;
         console.font.width = 16;

src/kboot.c

@@ -204,7 +204,8 @@ static int dt_set_chosen(void)
         printf("FDT: initrd at %p size 0x%lx\n", initrd_start, initrd_size);
     }
 
-    if (cur_boot_args.video.base) {
+    if (cur_boot_args.video.base &&
+        (adt_path_offset(adt, "/arm-io/disp0") > 0 || (chip_id != T8012 && chip_id != T7000))) {
         int fb = fdt_path_offset(dt, "/chosen/framebuffer");
         if (fb < 0)
             bail("FDT: /chosen node not found in devtree\n");
@@ -335,8 +336,26 @@ static int dt_set_memory(void)
     if (node < 0)
         bail("FDT: /memory node not found in devtree\n");
 
-    if (fdt_setprop(dt, node, "reg", memreg, sizeof(memreg)))
-        bail("FDT: couldn't set memory.reg property\n");
+    if (chip_id == T8012) {
+        u64 cache_min = ALIGN_UP(dram_max, BIT(29));
+        u64 cache_max = dram_base + dram_size;
+
+        /*
+         * Set the SSD cache as OS memory, supposedly we will deal with the x86 SSD interface with a
+         * kernel driver that allocates memory anyways
+         */
+        u64 memreg_t2[4] = {memreg[0], memreg[1], cpu_to_fdt64(cache_min),
+                            cpu_to_fdt64(cache_max - cache_min)};
+
+        printf("FDT: Usable memory range 2 (SSD cache): 0x%lx..0x%lx (0x%lx)\n", cache_min,
+               cache_max, cache_max - cache_min);
+
+        if (fdt_setprop(dt, node, "reg", memreg_t2, sizeof(memreg_t2)))
+            bail("FDT: couldn't set memory.reg property\n");
+    } else {
+        if (fdt_setprop(dt, node, "reg", memreg, sizeof(memreg)))
+            bail("FDT: couldn't set memory.reg property\n");
+    }
 
     return 0;
 }
@@ -2310,6 +2329,37 @@ static int dt_transfer_virtios(void)
     return 0;
 }
 
+static int dt_set_pmgr(void)
+{
+    if (chip_id != T8012)
+        return 0;
+
+    if (mem_size_actual > 0x40000000)
+        return 0;
+
+    int pmgr_node = fdt_path_offset(dt, "/soc/power-management@20e000000");
+    if (pmgr_node < 0) {
+        printf("FDT: Failed to find pmgr node\n");
+        return 0;
+    }
+
+    int dcs2_node = fdt_path_offset(dt, "/soc/power-management@20e000000/power-controller@80258");
+    if (dcs2_node < 0)
+        bail("FDT: failed to find ps_dcs2 node\n");
+
+    /* Allow failure */
+    fdt_delprop(dt, dcs2_node, "apple,always-on");
+
+    int dcs3_node = fdt_path_offset(dt, "/soc/power-management@20e000000/power-controller@80260");
+    if (dcs3_node < 0)
+        bail("FDT: failed to find ps_dcs3 node\n");
+
+    /* Allow failure */
+    fdt_delprop(dt, dcs3_node, "apple,always-on");
+
+    return 0;
+}
+
 void kboot_set_initrd(void *start, size_t size)
 {
     initrd_start = start;
@@ -2495,6 +2545,8 @@ int kboot_prepare_dt(void *fdt)
         return -1;
     if (dt_set_isp_fwdata())
         return -1;
+    if (dt_set_pmgr())
+        return -1;
 #ifndef RELEASE
     if (dt_transfer_virtios())
         return 1;

src/memory.c

@@ -380,8 +380,11 @@ static void mmu_map_mmio(void)
         u64 bus = ranges[2] | ((u64)ranges[3] << 32);
         u64 size = ranges[4] | ((u64)ranges[5] << 32);
 
-        mmu_add_mapping(bus, bus, size, MAIR_IDX_DEVICE_nGnRnE, PERM_RW_EL0);
+        /* T2 is really stupid */
+        if (chip_id == T8012)
+            size = ALIGN_UP(size, PAGE_SIZE);
 
+        mmu_add_mapping(bus, bus, size, MAIR_IDX_DEVICE_nGnRnE, PERM_RW_EL0);
         ranges += 6;
     }
 }

src/startup.c

@@ -134,7 +134,23 @@ void dump_boot_args(struct boot_args *ba)
             break;
     }
     if (!mem_size_actual) {
-        mem_size_actual = ALIGN_UP(ba->phys_base + ba->mem_size - 0x800000000, BIT(30));
+        if (chip_id == T8012) {
+            int anode = adt_path_offset(adt, "/arm-io/mcc");
+
+            /*
+             * Lower 512 MB intented for OS use, upper 512 or 1536 MB is some sort
+             * of SSD cache. Cannot use dram-size, it may not exist in older firmwares
+             * This property is changed from 4 to 2 by iBoot on 1 GB RAM models.
+             */
+
+            u32 dcs_num_channels = 0;
+            if (anode > 0 && ADT_GETPROP(adt, anode, "dcs_num_channels", &dcs_num_channels) > 0)
+                mem_size_actual = dcs_num_channels * 0x20000000;
+            else
+                mem_size_actual = 0x40000000;
+        } else {
+            mem_size_actual = ALIGN_UP(ba->phys_base + ba->mem_size - 0x800000000, BIT(30));
+        }
         printf("Correcting mem_size_actual to 0x%lx\n", mem_size_actual);
     }
 }