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Merge pull request #55 from yihuajack/evcd
Add Extended VCD (EVCD) support
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@@ -4,3 +4,4 @@ build | |
dist | ||
sootty.egg-info | ||
.private | ||
.vscode |
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$scope module testbench.adder_instance $end | ||
$var port 1 <0 data0 $end | ||
$var port 1 <1 data1 $end | ||
$var port 1 <2 data2 $end | ||
$var port 1 <3 data3 $end | ||
$var port 1 <4 carry $end | ||
$var port 1 <5 as $end | ||
$var port 1 <6 rdn $end | ||
$var port 1 <7 reset $end | ||
$var port 1 <8 test $end | ||
$var port 1 <9 write $end | ||
$upscope $end | ||
$enddefinitions $end | ||
#0 | ||
$dumpports | ||
pX 6 6 <0 | ||
pX 6 6 <1 | ||
pX 6 6 <2 | ||
pX 6 6 <3 | ||
pX 6 6 <4 | ||
pN 6 6 <5 | ||
pN 6 6 <6 | ||
pU 0 6 <7 | ||
pD 6 0 <8 | ||
pN 6 6 <9 | ||
$end | ||
#18 | ||
pH 0 6 <4 | ||
#20 | ||
pD 6 0 <5 | ||
pU 0 6 <6 | ||
pD 6 0 <9 | ||
#25 | ||
pf 0 0 <0 | ||
pf 0 0 <1 | ||
pf 0 0 <2 | ||
pf 0 0 <3 |
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$date June 26, 1989 10:05:41 | ||
$end | ||
$version VERILOG-SIMULATOR 1.0a | ||
$end | ||
$timescale 1 ns | ||
$end | ||
$scope module top $end | ||
$scope module m1 $end | ||
$var trireg 1 *@ net1 $end | ||
$var trireg 1 *# net2 $end | ||
$var trireg 1 *$ net3 $end | ||
$upscope $end | ||
$scope task t1 $end | ||
$var reg 32 (k accumulator[31:0] $end | ||
$var integer 32 {2 index $end | ||
$upscope $end | ||
$upscope $end | ||
$enddefinitions $end | ||
$comment | ||
$dumpvars was executed at time '#500'. | ||
All initial values are dumped at this time. | ||
$end | ||
#500 | ||
$dumpvars | ||
x*@ | ||
x*# | ||
x*$ | ||
bx (k | ||
bx {2 | ||
$end | ||
#505 | ||
0*@ | ||
1*# | ||
1*$ | ||
b10zx1110x11100 (k | ||
b1111000101z01x {2 | ||
#510 | ||
0*$ | ||
#520 | ||
1*$ | ||
#530 | ||
0*$ | ||
bz (k | ||
#535 | ||
$dumpall 0*@ 1*# 0*$ | ||
bz (k | ||
b1111000101z01x {2 | ||
$end | ||
#540 | ||
1*$ | ||
#1000 | ||
$dumpoff | ||
x*@ | ||
x*# | ||
x*$ | ||
bx (k | ||
bx {2 | ||
$end | ||
#2000 | ||
$dumpon | ||
z*@ | ||
1*# | ||
0*$ | ||
b0 (k | ||
bx {2 | ||
$end | ||
#2010 | ||
1*$ |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -1,37 +1,68 @@ | ||
$scope module testbench.adder_instance $end | ||
$var port 1 <0 data0 $end | ||
$var port 1 <1 data1 $end | ||
$var port 1 <2 data2 $end | ||
$var port 1 <3 data3 $end | ||
$var port 1 <4 carry $end | ||
$var port 1 <5 as $end | ||
$var port 1 <6 rdn $end | ||
$var port 1 <7 reset $end | ||
$var port 1 <8 test $end | ||
$var port 1 <9 write $end | ||
$comment | ||
File created using the following command: | ||
vcd file myevcdfile.evcd -dumpports | ||
$end | ||
$date | ||
Wed Aug 31 09:48:03 2022 | ||
$end | ||
$version | ||
dumpports ModelSim Version 10.2c | ||
$end | ||
$timescale | ||
1ns | ||
$end | ||
|
||
$scope module test_counter $end | ||
|
||
$scope module dut $end | ||
$var port [7:0] <0 count $end | ||
$var port 1 <1 clk $end | ||
$var port 1 <2 reset $end | ||
$upscope $end | ||
$upscope $end | ||
$enddefinitions $end | ||
#0 | ||
$dumpports | ||
pX 6 6 <0 | ||
pX 6 6 <1 | ||
pX 6 6 <2 | ||
pX 6 6 <3 | ||
pX 6 6 <4 | ||
pN 6 6 <5 | ||
pN 6 6 <6 | ||
pU 0 6 <7 | ||
pD 6 0 <8 | ||
pN 6 6 <9 | ||
pD 6 0 <2 | ||
pD 6 0 <1 | ||
pXXXXXXXX 66666666 66666666 <0 | ||
$end | ||
#18 | ||
pH 0 6 <4 | ||
#5 | ||
pU 0 6 <2 | ||
#8 | ||
pLLLLLLLL 66666666 00000000 <0 | ||
#9 | ||
pD 6 0 <2 | ||
#10 | ||
pU 0 6 <1 | ||
#12 | ||
pLLLLLLLH 66666660 00000006 <0 | ||
#20 | ||
pD 6 0 <5 | ||
pU 0 6 <6 | ||
pD 6 0 <9 | ||
#25 | ||
pf 0 0 <0 | ||
pf 0 0 <1 | ||
pf 0 0 <2 | ||
pf 0 0 <3 | ||
pD 6 0 <1 | ||
#30 | ||
pU 0 6 <1 | ||
#32 | ||
pLLLLLLHL 66666606 00000060 <0 | ||
#40 | ||
pD 6 0 <1 | ||
#50 | ||
pU 0 6 <1 | ||
#52 | ||
pLLLLLLHH 66666600 00000066 <0 | ||
#60 | ||
pD 6 0 <1 | ||
#70 | ||
pU 0 6 <1 | ||
#72 | ||
pLLLLLHLL 66666066 00000600 <0 | ||
#80 | ||
pD 6 0 <1 | ||
#90 | ||
pU 0 6 <1 | ||
#92 | ||
pLLLLLHLH 66666060 00000606 <0 | ||
#100 | ||
pD 6 0 <1 | ||
$vcdclose | ||
#100 | ||
$end |
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