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Reformatted tests
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Ben1152000 committed Jan 17, 2022
1 parent 3e9748c commit 226b773
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Showing 6 changed files with 52 additions and 34 deletions.
12 changes: 6 additions & 6 deletions tests/run_tests.py
Original file line number Diff line number Diff line change
@@ -1,16 +1,16 @@
if __name__ == "__main__":
tests = [
'test_general',
'test_limits',
'test_pyrtl',
'test_style',
'test_wire_types'
"test_general",
"test_limits",
"test_pyrtl",
"test_style",
"test_wire_types",
]

modules = map(__import__, tests)

for module in modules:
for name, test in module.__dict__.items():
if callable(test):
if name[:4] == 'test':
if name[:4] == "test":
test()
8 changes: 5 additions & 3 deletions tests/test_general.py
Original file line number Diff line number Diff line change
Expand Up @@ -10,12 +10,13 @@ def test_svg_output():

image = Visualizer().to_svg(wiretrace, start=0, length=8)

pattern = r'(?:<\?xml\b[^>]*>[^<]*)?(?:<!--.*?-->[^<]*)*(?:<svg|<!DOCTYPE svg)\b'
pattern = r"(?:<\?xml\b[^>]*>[^<]*)?(?:<!--.*?-->[^<]*)*(?:<svg|<!DOCTYPE svg)\b"
prog = re.compile(pattern, re.DOTALL)
assert prog.match(image.source) is not None

image.display()


def test_scope():
wiretrace = WireTrace().from_vcd("example/example2.vcd")

Expand All @@ -27,7 +28,7 @@ def test_scope():
# for group in group.groups:
# print('\t' * depth + group.name + ':')
# print_group(group, depth + 1)

# print_group(wiretrace.root)

assert wiretrace.num_wires() == 26
Expand All @@ -36,7 +37,8 @@ def test_scope():

image.display()


if __name__ == "__main__":
test_svg_output()
test_scope()
print('Success!')
print("Success!")
21 changes: 17 additions & 4 deletions tests/test_limits.py
Original file line number Diff line number Diff line change
Expand Up @@ -2,13 +2,26 @@


def test_limits():
assert str(LimitExpression("a + b & c - d + const 1").tree.pretty('\t')) == "&\n\t+\n\t\twire\ta\n\t\twire\tb\n\t+\n\t\t-\n\t\t\twire\tc\n\t\t\twire\td\n\t\tconst\t1\n"
assert (
str(LimitExpression("a + b & c - d + const 1").tree.pretty("\t"))
== "&\n\t+\n\t\twire\ta\n\t\twire\tb\n\t+\n\t\t-\n\t\t\twire\tc\n\t\t\twire\td\n\t\tconst\t1\n"
)

assert str(LimitExpression("after (acc clk == const 5) & ready & value & (3 next data == const 64)").tree.pretty('\t')) == "&\n\t&\n\t\t&\n\t\t\tafter\n\t\t\t\t==\n\t\t\t\t\tacc\n\t\t\t\t\t\twire\tclk\n\t\t\t\t\tconst\t5\n\t\t\twire\tready\n\t\twire\tvalue\n\t==\n\t\tnext\n\t\t\t3\n\t\t\twire\tdata\n\t\tconst\t64\n"
assert (
str(
LimitExpression(
"after (acc clk == const 5) & ready & value & (3 next data == const 64)"
).tree.pretty("\t")
)
== "&\n\t&\n\t\t&\n\t\t\tafter\n\t\t\t\t==\n\t\t\t\t\tacc\n\t\t\t\t\t\twire\tclk\n\t\t\t\t\tconst\t5\n\t\t\twire\tready\n\t\twire\tvalue\n\t==\n\t\tnext\n\t\t\t3\n\t\t\twire\tdata\n\t\tconst\t64\n"
)

assert str(LimitExpression("D1 & D2").tree.pretty('\t')) == "&\n\twire\tD1\n\twire\tD2\n"
assert (
str(LimitExpression("D1 & D2").tree.pretty("\t"))
== "&\n\twire\tD1\n\twire\tD2\n"
)


if __name__ == "__main__":
test_limits()
print('Success!')
print("Success!")
41 changes: 22 additions & 19 deletions tests/test_pyrtl.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,16 +5,16 @@
def test_counter():
pyrtl.reset_working_block()

i = pyrtl.Input(3, 'i')
counter = pyrtl.Register(3, 'counter')
o = pyrtl.Output(3, 'o')
i = pyrtl.Input(3, "i")
counter = pyrtl.Register(3, "counter")
o = pyrtl.Output(3, "o")

update = counter + i
counter.next <<= update
o <<= counter

sim = pyrtl.Simulation()
sim.step_multiple({'i': [1, 1, 1, 1, 1]})
sim.step_multiple({"i": [1, 1, 1, 1, 1]})
sim.tracer.render_trace()

wiretrace = WireTrace.from_pyrtl(sim.tracer)
Expand All @@ -40,7 +40,7 @@ def ALU(ctrl, a, b):
zero = pyrtl.WireVector(1)

with pyrtl.conditional_assignment:
with ctrl == AND:
with ctrl == AND:
result |= a & b
with ctrl == OR:
result |= a | b
Expand All @@ -49,7 +49,7 @@ def ALU(ctrl, a, b):
with ctrl == SUB:
result |= a - b

zero <<= (result == 0)
zero <<= result == 0
return result, zero

def ALUControl(op, func):
Expand All @@ -72,30 +72,33 @@ def ALUControl(op, func):
ctrl |= SUB
return ctrl

op = pyrtl.Input(2, 'op')
a = pyrtl.Input(16, 'a')
b = pyrtl.Input(16, 'b')
func = pyrtl.Input(2, 'func')
op = pyrtl.Input(2, "op")
a = pyrtl.Input(16, "a")
b = pyrtl.Input(16, "b")
func = pyrtl.Input(2, "func")

r = pyrtl.Output(16, 'result')
z = pyrtl.Output(1, 'zero')
r = pyrtl.Output(16, "result")
z = pyrtl.Output(1, "zero")

ctl = ALUControl(op, func)
r_o, z_o, = ALU(ctl, a, b)
(
r_o,
z_o,
) = ALU(ctl, a, b)
r <<= r_o
z <<= z_o

sim_inputs = {
'op': [0]*2 + [1]*2 + [2]*2 + [3]*2,
'a': [2,1]*4,
'b': [1,0,1,0]*2,
'func': [0]*6 + [0,1]
"op": [0] * 2 + [1] * 2 + [2] * 2 + [3] * 2,
"a": [2, 1] * 4,
"b": [1, 0, 1, 0] * 2,
"func": [0] * 6 + [0, 1],
}

sim = pyrtl.Simulation()

sim.step_multiple(sim_inputs)
sim.tracer.render_trace(trace_list=['op','func','a','b','result','zero'])
sim.tracer.render_trace(trace_list=["op", "func", "a", "b", "result", "zero"])

wiretrace = WireTrace.from_pyrtl(sim.tracer)
Visualizer().to_svg(wiretrace).display()
Expand All @@ -104,4 +107,4 @@ def ALUControl(op, func):
if __name__ == "__main__":
test_counter()
test_alu()
print('Success!')
print("Success!")
2 changes: 1 addition & 1 deletion tests/test_style.py
Original file line number Diff line number Diff line change
Expand Up @@ -14,4 +14,4 @@ def test_style_class():

if __name__ == "__main__":
test_style_class()
print('Success!')
print("Success!")
2 changes: 1 addition & 1 deletion tests/test_wire_types.py
Original file line number Diff line number Diff line change
Expand Up @@ -9,4 +9,4 @@ def test_data_types():

if __name__ == "__main__":
test_data_types()
print('Success!')
print("Success!")

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