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i2c_reva.c
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i2c_reva.c
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/******************************************************************************
*
* Copyright (C) 2022-2023 Maxim Integrated Products, Inc. All Rights Reserved.
* (now owned by Analog Devices, Inc.),
* Copyright (C) 2023 Analog Devices, Inc. All Rights Reserved. This software
* is proprietary to Analog Devices, Inc. and its licensors.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************/
#include <stdio.h>
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "mxc_device.h"
#include "mxc_assert.h"
#include "mxc_lock.h"
#include "mxc_sys.h"
#include "mxc_delay.h"
#include "i2c_regs.h"
#include "i2c.h"
#include "i2c_reva.h"
#include "dma.h"
#include "dma_reva.h"
/* **** Variable Declaration **** */
typedef struct {
mxc_i2c_reva_req_t *req;
int master; // 1 for Master, 0 for slave
int channelTx; // DMA channel for TX transaction
int channelRx; // DMA channel for RX transaction
volatile int writeDone; // Write done flag
volatile int readDone; // Flag done flag
bool dma_initialized; // Check to see whether DMA was initialized
mxc_dma_reva_regs_t *dma; // Save DMA Instance
} mxc_i2c_reva_req_state_t;
static mxc_i2c_reva_req_state_t states[MXC_I2C_INSTANCES];
void *AsyncRequests[MXC_I2C_INSTANCES];
unsigned int AsyncWritten[MXC_I2C_INSTANCES];
unsigned int AsyncRead[MXC_I2C_INSTANCES];
/* **** Function Prototypes **** */
void MXC_I2C_RevA_AsyncCallback(mxc_i2c_reva_regs_t *i2c, int retVal);
void MXC_I2C_RevA_AsyncStop(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_AbortAsync(mxc_i2c_reva_regs_t *i2c);
void MXC_I2C_RevA_MasterAsyncHandler(int i2cNum);
int MXC_I2C_RevA_DMAHandler(mxc_i2c_reva_req_t *req);
void MXC_I2C_RevA_SlaveAsyncHandler(mxc_i2c_reva_regs_t *i2c, mxc_i2c_reva_slave_handler_t callback,
uint32_t *int_en, int *retVal);
/* ************************************************************************* */
/* Control/Configuration functions */
/* ************************************************************************* */
int MXC_I2C_RevA_Init(mxc_i2c_reva_regs_t *i2c, int masterMode, unsigned int slaveAddr)
{
int err;
int8_t i2cNum;
if (i2c == NULL) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
if ((err = MXC_I2C_Recover((mxc_i2c_regs_t *)i2c, 16)) != E_NO_ERROR) {
return err;
}
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN;
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
// Set the thresholds here and allow the user to change them as needed
MXC_I2C_SetTXThreshold((mxc_i2c_regs_t *)i2c, 2); // set TX threshold to 2 bytes
MXC_I2C_SetRXThreshold((mxc_i2c_regs_t *)i2c, 6); // set RX threshold to 6 bytes
if (!masterMode) {
MXC_I2C_SetSlaveAddr((mxc_i2c_regs_t *)i2c, slaveAddr, 0);
states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 0;
} else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_MST_MODE;
states[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)].master = 1;
}
// Prepare I2C instance state.
states[i2cNum].channelTx = E_NO_DEVICE;
states[i2cNum].channelRx = E_NO_DEVICE;
states[i2cNum].writeDone = 0;
states[i2cNum].readDone = 0;
states[i2cNum].dma_initialized = false;
return E_NO_ERROR;
}
int MXC_I2C_RevA_SetSlaveAddr(mxc_i2c_reva_regs_t *i2c, unsigned int slaveAddr, int idx)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
if (idx >= (sizeof(i2c->slave_multi) / sizeof(uint32_t))) {
return E_NOT_SUPPORTED;
}
if (slaveAddr > MXC_F_I2C_REVA_SLAVE_MULTI_ADDR) {
// Only support addresses up to 10 bits
return E_BAD_PARAM;
}
i2c->slave_multi[idx] = 0;
if (slaveAddr > MXC_I2C_REVA_MAX_ADDR_WIDTH) {
// Set for 10bit addressing mode
i2c->slave_multi[idx] = MXC_F_I2C_REVA_SLAVE_MULTI_EXT_ADDR_EN;
}
i2c->slave_multi[idx] |= slaveAddr;
return E_NO_ERROR;
}
int MXC_I2C_RevA_Shutdown(mxc_i2c_reva_regs_t *i2c)
{
int8_t i2cNum;
if (i2c == NULL) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
i2c->ctrl = 0;
i2c->inten0 = 0;
i2c->inten1 = 0;
i2c->intfl0 = i2c->intfl0;
i2c->intfl1 = i2c->intfl1;
i2c->rxctrl0 = 0;
i2c->rxctrl1 = 0;
i2c->txctrl0 = 0;
i2c->txctrl1 = 0;
states[i2cNum] = (const mxc_i2c_reva_req_state_t){ 0 };
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
if (states[i2cNum].dma_initialized == true) {
#if TARGET_NUM == 32665
MXC_DMA_DeInit((mxc_dma_regs_t *)(states[i2cNum].dma));
#else
MXC_DMA_DeInit();
#endif
// Release any acquired DMA channels.
if (states[i2cNum].channelTx >= 0) {
MXC_DMA_ReleaseChannel(states[i2cNum].channelTx);
states[i2cNum].channelTx = E_NO_DEVICE;
}
if (states[i2cNum].channelRx >= 0) {
MXC_DMA_ReleaseChannel(states[i2cNum].channelRx);
states[i2cNum].channelRx = E_NO_DEVICE;
}
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_SetFrequency(mxc_i2c_reva_regs_t *i2c, unsigned int hz)
{
unsigned int ticksTotal, hiClks, lowClks;
if (i2c == NULL) {
return E_NULL_PTR;
}
if (hz > MXC_I2C_REVA_FASTPLUS_SPEED && hz <= MXC_I2C_REVA_HIGH_SPEED) {
// Enable high speed mode
int hsLowClks, hsHiClks;
// Calculate the period of SCL and set up 33% duty cycle
ticksTotal = PeripheralClock / hz;
hsLowClks = (ticksTotal * 2) / 3 - 1;
hsHiClks = ticksTotal / 3 - 1;
// For rounding errors, adjust by 1 clock tick
if (ticksTotal % 2) {
hsHiClks++;
}
// If we're too slow for high speed, bail out
if ((hsHiClks > 0xF) || (hsLowClks > 0xF)) {
return E_BAD_PARAM;
}
hsLowClks = (hsLowClks << MXC_F_I2C_REVA_HSCLK_LO_POS) & MXC_F_I2C_REVA_HSCLK_LO;
hsHiClks = (hsHiClks << MXC_F_I2C_REVA_HSCLK_HI_POS) & MXC_F_I2C_REVA_HSCLK_HI;
i2c->hsclk = (hsLowClks | hsHiClks);
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_HS_EN;
hz = MXC_I2C_REVA_FAST_SPEED; // High speed preambles will be sent at 400kHz
} else if (hz > MXC_I2C_REVA_HIGH_SPEED) {
return E_BAD_PARAM;
}
// Calculate the period of SCL, 50% duty cycle
ticksTotal = PeripheralClock / hz;
hiClks = (ticksTotal >> 1) - 1;
lowClks = (ticksTotal >> 1) - 1;
// Adjust for rounding errors
if (ticksTotal % 2) {
hiClks++;
}
// Check for maximum/minimum supported speeds
if ((hiClks > MXC_F_I2C_REVA_CLKHI_HI) || (lowClks == 0)) {
return E_BAD_PARAM;
}
i2c->clklo = lowClks & MXC_F_I2C_REVA_CLKLO_LO;
i2c->clkhi = hiClks & MXC_F_I2C_REVA_CLKHI_HI;
// Return the actual speed set, since it won't be exactly what's requested
return MXC_I2C_GetFrequency((mxc_i2c_regs_t *)i2c);
}
unsigned int MXC_I2C_RevA_GetFrequency(mxc_i2c_reva_regs_t *i2c)
{
unsigned int sclCycles = 2;
// sclCycles Initialized to 2 b/c formula is sclCycles = (lo_clks + 1) + (hi_clks + 1)
if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_HS_EN) {
// HS-Mode enabled, calculate HS Frequency
sclCycles += (i2c->hsclk & MXC_F_I2C_REVA_HSCLK_LO) >> MXC_F_I2C_REVA_HSCLK_LO_POS;
sclCycles += (i2c->hsclk & MXC_F_I2C_REVA_HSCLK_HI) >> MXC_F_I2C_REVA_HSCLK_HI_POS;
} else {
// HS-Mode not enabled, calculate nominal frequency
sclCycles += (i2c->clklo & MXC_F_I2C_REVA_CLKLO_LO);
sclCycles += (i2c->clkhi & MXC_F_I2C_REVA_CLKHI_HI);
}
return PeripheralClock / sclCycles;
}
int MXC_I2C_RevA_ReadyForSleep(mxc_i2c_reva_regs_t *i2c)
{
if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) {
return E_BAD_PARAM;
}
if (AsyncRequests[MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c)] != NULL) {
return E_BUSY;
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_SetClockStretching(mxc_i2c_reva_regs_t *i2c, int enable)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
if (enable) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_CLKSTR_DIS;
} else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_CLKSTR_DIS;
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_GetClockStretching(mxc_i2c_reva_regs_t *i2c)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
return !((i2c->ctrl & MXC_F_I2C_REVA_CTRL_CLKSTR_DIS) >> MXC_F_I2C_REVA_CTRL_CLKSTR_DIS_POS);
}
int MXC_I2C_RevA_DMA_Init(mxc_i2c_reva_regs_t *i2c, mxc_dma_reva_regs_t *dma, bool use_dma_tx,
bool use_dma_rx)
{
int8_t i2cNum;
int8_t rxChannel;
int8_t txChannel;
if (i2c == NULL || dma == NULL) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
if (states[i2cNum].dma_initialized == false) {
#if TARGET_NUM == 32665
MXC_DMA_Init((mxc_dma_regs_t *)dma);
#else
MXC_DMA_Init();
#endif
}
// Release any acquire DMA TX channels before configuring.
if (states[i2cNum].channelTx != E_NO_DEVICE) {
MXC_DMA_ReleaseChannel(states[i2cNum].channelTx);
}
// Release any acquire DMA RX channels before configuring.
if (states[i2cNum].channelRx != E_NO_DEVICE) {
MXC_DMA_ReleaseChannel(states[i2cNum].channelRx);
}
// Set up I2C DMA TX.
if (use_dma_tx == true) {
#if TARGET_NUM == 32665
txChannel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma);
#else
txChannel = MXC_DMA_AcquireChannel();
#endif
// Set Source and Destination Widths.
MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_SRCWD,
(MXC_DMA_WIDTH_BYTE << MXC_F_DMA_REVA_CTRL_SRCWD_POS));
MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_DSTWD,
(MXC_DMA_WIDTH_BYTE << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
// Set Source and Destination Increment.
MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_SRCINC,
(1 << MXC_F_DMA_REVA_CTRL_SRCINC_POS));
MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_DSTINC,
(0 << MXC_F_DMA_REVA_CTRL_DSTINC_POS));
if (states[i2cNum].master) {
MXC_DMA_SetCallback(txChannel, MXC_I2C_RevA_DMACallback);
} else {
MXC_DMA_SetCallback(txChannel, NULL);
}
MXC_DMA_EnableInt(txChannel);
MXC_DMA_SetChannelInterruptEn(txChannel, 0, 1);
states[i2cNum].channelTx = txChannel;
}
// Set up I2C DMA RX.
if (use_dma_rx == true) {
#if TARGET_NUM == 32665
rxChannel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma);
#else
rxChannel = MXC_DMA_AcquireChannel();
#endif
// Set Source and Destination Widths.
MXC_SETFIELD(dma->ch[rxChannel].ctrl, MXC_F_DMA_REVA_CTRL_SRCWD,
(MXC_DMA_WIDTH_BYTE << MXC_F_DMA_REVA_CTRL_SRCWD_POS));
MXC_SETFIELD(dma->ch[rxChannel].ctrl, MXC_F_DMA_REVA_CTRL_DSTWD,
(MXC_DMA_WIDTH_BYTE << MXC_F_DMA_REVA_CTRL_DSTWD_POS));
// Set Source and Destination Increment.
MXC_SETFIELD(dma->ch[rxChannel].ctrl, MXC_F_DMA_REVA_CTRL_SRCINC,
(0 << MXC_F_DMA_REVA_CTRL_SRCINC_POS));
MXC_SETFIELD(dma->ch[rxChannel].ctrl, MXC_F_DMA_REVA_CTRL_DSTINC,
(1 << MXC_F_DMA_REVA_CTRL_DSTINC_POS));
if (states[i2cNum].master) {
MXC_DMA_SetCallback(rxChannel, MXC_I2C_RevA_DMACallback);
} else {
MXC_DMA_SetCallback(rxChannel, NULL);
}
MXC_DMA_EnableInt(rxChannel);
MXC_DMA_SetChannelInterruptEn(rxChannel, 0, 1);
states[i2cNum].channelRx = rxChannel;
}
states[i2cNum].dma_initialized = true;
states[i2cNum].dma = dma;
return E_NO_ERROR;
}
int MXC_I2C_RevA_DMA_GetTXChannel(mxc_i2c_reva_regs_t *i2c)
{
int i2cNum;
if (i2c == NULL) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
return states[i2cNum].channelTx;
}
int MXC_I2C_RevA_DMA_GetRXChannel(mxc_i2c_reva_regs_t *i2c)
{
int i2cNum;
if (i2c == NULL) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
return states[i2cNum].channelRx;
}
int MXC_I2C_RevA_DMA_SetRequestSelect(mxc_i2c_reva_regs_t *i2c, mxc_dma_reva_regs_t *dma,
uint32_t txReqSel, uint32_t rxReqSel)
{
int i2cNum;
uint32_t txChannel;
uint32_t rxChannel;
if (i2c == NULL || dma == NULL) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
txChannel = states[i2cNum].channelTx;
rxChannel = states[i2cNum].channelRx;
// This function will overwrite the current DMA TX/RX Request Selects.
if (txReqSel != -1) {
MXC_SETFIELD(dma->ch[txChannel].ctrl, MXC_F_DMA_REVA_CTRL_REQUEST, txReqSel);
}
if (rxReqSel != -1) {
MXC_SETFIELD(dma->ch[rxChannel].ctrl, MXC_F_DMA_REVA_CTRL_REQUEST, rxReqSel);
}
return E_NO_ERROR;
}
/* ************************************************************************* */
/* Low-level functions */
/* ************************************************************************* */
int MXC_I2C_RevA_Start(mxc_i2c_reva_regs_t *i2c)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
// If we have an incomplete transfer, we need to do a restart
if (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_START) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START; // No check for start generation
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_Stop(mxc_i2c_reva_regs_t *i2c)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_STOP) {}
return E_NO_ERROR;
}
int MXC_I2C_RevA_WriteByte(mxc_i2c_reva_regs_t *i2c, unsigned char byte)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
if (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {
return E_OVERFLOW;
}
// I'm depending on an interrupt flag here
// This might cause issues with the transaction level functions to come
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK, MXC_I2C_REVA_INTFL1_MASK);
i2c->fifo = byte;
while (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_EM)) {}
return i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DATA_ERR;
}
int MXC_I2C_RevA_ReadByte(mxc_i2c_reva_regs_t *i2c, unsigned char *byte, int ack)
{
if ((i2c == NULL) || (byte == NULL)) {
return E_NULL_PTR;
}
if (i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM) {
return E_UNDERFLOW;
}
*byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA);
if (ack) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK;
} else {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_IRXM_ACK;
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_ReadByteInteractive(mxc_i2c_reva_regs_t *i2c, unsigned char *byte,
mxc_i2c_reva_getAck_t getAck)
{
if ((i2c == NULL) || (byte == NULL)) {
return E_NULL_PTR;
}
if (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM)) {
return E_UNDERFLOW;
}
*byte = (uint8_t)(i2c->fifo & MXC_F_I2C_REVA_FIFO_DATA);
if (getAck == NULL) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS;
} else {
i2c->ctrl |= (!!getAck((mxc_i2c_reva_regs_t *)i2c, *byte))
<< MXC_F_I2C_REVA_CTRL_IRXM_ACK_POS;
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_Write(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len)
{
int notAcked = 0;
unsigned written = 0;
if (i2c == NULL) {
return E_NULL_PTR;
}
if ((bytes == NULL) || (len == NULL)) {
return E_NULL_PTR;
}
for (; written < *len; written++) {
int retVal = MXC_I2C_WriteByte((mxc_i2c_regs_t *)i2c, bytes[written]);
if (retVal >= 0) {
notAcked += retVal;
} else {
*len = written;
return retVal;
}
}
*len = written;
notAcked = (notAcked > 0) ? 1 : 0;
return notAcked;
}
int MXC_I2C_RevA_Read(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack)
{
unsigned read = 0;
if (i2c == NULL) {
return E_NULL_PTR;
}
if ((bytes == NULL) || (len == NULL)) {
return E_NULL_PTR;
}
for (; read < *len - 1; read++) {
int retVal = MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), 1);
if (retVal != E_NO_ERROR) {
*len = read;
return retVal;
}
}
read++;
*len = read;
return MXC_I2C_ReadByte((mxc_i2c_regs_t *)i2c, &(bytes[read]), ack);
}
int MXC_I2C_RevA_ReadRXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
unsigned int len)
{
unsigned read = 0;
if ((i2c == NULL) || (bytes == NULL)) {
return E_NULL_PTR;
}
while ((len > read) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_RX_EM))) {
bytes[read++] = i2c->fifo;
}
return read;
}
int MXC_I2C_RevA_ReadRXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_dma_regs_t *dma)
{
uint8_t i2cNum;
mxc_dma_srcdst_t srcdst;
if ((i2c == NULL) || (bytes == NULL)) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
if (states[i2cNum].channelRx == E_NO_DEVICE) {
return E_BAD_STATE;
}
srcdst.ch = states[i2cNum].channelRx;
srcdst.dest = bytes;
srcdst.len = len;
MXC_DMA_SetSrcDst(srcdst);
MXC_DMA_Start(states[i2cNum].channelRx);
i2c->dma |= MXC_F_I2C_REVA_DMA_RX_EN;
return E_NO_ERROR;
}
int MXC_I2C_RevA_GetRXFIFOAvailable(mxc_i2c_reva_regs_t *i2c)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
return (i2c->rxctrl1 & MXC_F_I2C_REVA_RXCTRL1_LVL) >> MXC_F_I2C_REVA_RXCTRL1_LVL_POS;
}
int MXC_I2C_RevA_WriteTXFIFO(mxc_i2c_reva_regs_t *i2c, volatile unsigned char *bytes,
unsigned int len)
{
unsigned written = 0;
if ((i2c == NULL) || (bytes == NULL)) {
return E_NULL_PTR;
}
while ((len > written) && (!(i2c->status & MXC_F_I2C_REVA_STATUS_TX_FULL))) {
i2c->fifo = bytes[written++];
}
return written;
}
int MXC_I2C_RevA_WriteTXFIFODMA(mxc_i2c_reva_regs_t *i2c, unsigned char *bytes, unsigned int len,
mxc_dma_regs_t *dma)
{
int8_t i2cNum;
mxc_dma_srcdst_t srcdst;
if ((i2c == NULL) || (bytes == NULL)) {
return E_NULL_PTR;
}
i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c);
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START;
if (states[i2cNum].channelTx == E_NO_DEVICE) {
return E_BAD_STATE;
}
srcdst.ch = states[i2cNum].channelTx;
srcdst.source = bytes;
srcdst.len = len;
MXC_DMA_SetSrcDst(srcdst);
MXC_DMA_Start(states[i2cNum].channelTx);
i2c->dma |= MXC_F_I2C_REVA_DMA_TX_EN;
return E_NO_ERROR;
}
int MXC_I2C_RevA_GetTXFIFOAvailable(mxc_i2c_reva_regs_t *i2c)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
int txFIFOlen = (i2c->fifolen & MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH) >>
MXC_F_I2C_REVA_FIFOLEN_TX_DEPTH_POS;
return txFIFOlen -
((i2c->txctrl1 & MXC_F_I2C_REVA_TXCTRL1_LVL) >> MXC_F_I2C_REVA_TXCTRL1_LVL_POS);
}
void MXC_I2C_RevA_ClearRXFIFO(mxc_i2c_reva_regs_t *i2c)
{
i2c->rxctrl0 |= MXC_F_I2C_REVA_RXCTRL0_FLUSH;
while (i2c->rxctrl0 & MXC_F_I2C_REVA_RXCTRL0_FLUSH) {}
}
void MXC_I2C_RevA_ClearTXFIFO(mxc_i2c_reva_regs_t *i2c)
{
i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_FLUSH;
while (i2c->txctrl0 & MXC_F_I2C_REVA_TXCTRL0_FLUSH) {}
}
int MXC_I2C_RevA_GetFlags(mxc_i2c_reva_regs_t *i2c, unsigned int *flags0, unsigned int *flags1)
{
if (i2c == NULL) {
return E_NULL_PTR;
}
if ((flags0 == NULL) || (flags1 == NULL)) {
return E_BAD_PARAM;
}
*flags0 = i2c->intfl0;
*flags1 = i2c->intfl1;
return E_NO_ERROR;
}
void MXC_I2C_RevA_ClearFlags(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1)
{
i2c->intfl0 = flags0;
i2c->intfl1 = flags1;
}
void MXC_I2C_RevA_EnableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1)
{
i2c->inten0 |= flags0;
i2c->inten1 |= flags1;
}
void MXC_I2C_RevA_DisableInt(mxc_i2c_reva_regs_t *i2c, unsigned int flags0, unsigned int flags1)
{
i2c->inten0 &= ~flags0;
i2c->inten1 &= ~flags1;
}
int MXC_I2C_RevA_Recover(mxc_i2c_reva_regs_t *i2c, unsigned int retries)
{
int err;
unsigned int i;
if (i2c == NULL) {
return E_NULL_PTR;
}
err = E_COMM_ERR;
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_EN;
int swBit = i2c->ctrl & MXC_F_I2C_REVA_CTRL_BB_MODE;
if (i2c == NULL) {
return E_NULL_PTR;
}
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_BB_MODE;
// Follow the procedure detailed in the header file
// Delay 10uS between each step to give the line/slaves time to react
for (i = 0; i < retries; i++) {
MXC_Delay(10);
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SCL_OUT;
MXC_Delay(10);
if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT;
continue; // Give up and try again
}
MXC_Delay(10);
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_SDA_OUT;
MXC_Delay(10);
if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA) {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT;
continue; // Give up and try again
}
MXC_Delay(10);
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SDA_OUT;
MXC_Delay(10);
if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_SDA)) {
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT | MXC_F_I2C_REVA_CTRL_SDA_OUT;
continue; // Give up and try again
}
MXC_Delay(10);
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_SCL_OUT;
MXC_Delay(10);
if (i2c->ctrl & MXC_F_I2C_REVA_CTRL_SCL) {
err = E_NO_ERROR; // We have control
break;
}
}
if (swBit == 0) {
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_BB_MODE;
}
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_EN;
return err;
}
void MXC_I2C_RevA_EnablePreload(mxc_i2c_reva_regs_t *i2c)
{
i2c->txctrl0 |= MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE;
}
void MXC_I2C_RevA_DisablePreload(mxc_i2c_reva_regs_t *i2c)
{
i2c->txctrl0 &= ~MXC_F_I2C_REVA_TXCTRL0_PRELOAD_MODE;
}
void MXC_I2C_RevA_EnableGeneralCall(mxc_i2c_reva_regs_t *i2c)
{
i2c->ctrl |= MXC_F_I2C_REVA_CTRL_GC_ADDR_EN;
}
void MXC_I2C_RevA_DisableGeneralCall(mxc_i2c_reva_regs_t *i2c)
{
i2c->ctrl &= ~MXC_F_I2C_REVA_CTRL_GC_ADDR_EN;
}
void MXC_I2C_RevA_SetTimeout(mxc_i2c_reva_regs_t *i2c, unsigned int timeout)
{
i2c->timeout |= (timeout & 0xFFFF);
}
unsigned int MXC_I2C_RevA_GetTimeout(mxc_i2c_reva_regs_t *i2c)
{
return (i2c->timeout & 0xFFFF);
}
/* ************************************************************************* */
/* Transaction level functions */
/* ************************************************************************* */
int MXC_I2C_RevA_MasterTransaction(mxc_i2c_reva_req_t *req)
{
mxc_i2c_reva_regs_t *i2c = req->i2c; // Save off pointer for faster access
unsigned int written = 0;
unsigned int read = 0;
if (req->addr > MXC_I2C_REVA_MAX_ADDR_WIDTH) {
return E_NOT_SUPPORTED;
}
if (MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c) < 0) {
return E_BAD_PARAM;
}
if (!(i2c->ctrl & MXC_F_I2C_REVA_CTRL_MST_MODE)) {
return E_BAD_STATE;
}
// if(!read | write)
// Start
// send addr w/ write bit
// if(Write)
// send tx_len data
// return if error (or NACK)
// if(Read)
// if(Write)
// send restart
// else
// send start
// send addr w/ read bit
// read rx_len bytes acking all
// stop or restart
// return good or error
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c, MXC_I2C_REVA_INTFL0_MASK,
MXC_I2C_REVA_INTFL1_MASK); // Clear all I2C Interrupts
MXC_I2C_ClearTXFIFO((mxc_i2c_regs_t *)i2c);
MXC_I2C_ClearRXFIFO((mxc_i2c_regs_t *)i2c);
i2c->inten0 = 0;
i2c->inten1 = 0;
if ((req->rx_len == 0) || (req->tx_len != 0)) {
// Load the slave address with write bit set
i2c->fifo = (req->addr << 1) & ~0x1;
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_START;
}
while (req->tx_len > written) {
if (i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_TX_THD) {
written += MXC_I2C_WriteTXFIFO((mxc_i2c_regs_t *)i2c, &req->tx_buf[written],
req->tx_len - written);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_TX_THD;
}
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
req->tx_len = written;
MXC_I2C_Stop((mxc_i2c_regs_t *)i2c);
return E_COMM_ERR;
}
}
MXC_I2C_ClearFlags((mxc_i2c_regs_t *)i2c,
MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_RX_THD, 0);
if (req->rx_len != 0) {
if (req->rx_len > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0;
} else {
i2c->rxctrl1 = req->rx_len; // 0 for 256, otherwise number of bytes to read
}
MXC_I2C_Start((mxc_i2c_regs_t *)i2c); // Start or Restart as needed
while (i2c->mstctrl & MXC_F_I2C_REVA_MSTCTRL_RESTART) {}
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
}
while (req->rx_len > read) {
if (i2c->intfl0 & (MXC_F_I2C_REVA_INTFL0_RX_THD | MXC_F_I2C_REVA_INTFL0_DONE)) {
read +=
MXC_I2C_ReadRXFIFO((mxc_i2c_regs_t *)i2c, &req->rx_buf[read], req->rx_len - read);
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_RX_THD;
}
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
req->rx_len = read;
MXC_I2C_Stop((mxc_i2c_regs_t *)i2c);
return E_COMM_ERR;
}
/*
if ((i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE) && (req->rx_len > read) &&
(MXC_I2C_RevA_GetRXFIFOAvailable(i2c) == 0)) {
if ((req->rx_len - read) > MXC_I2C_REVA_MAX_FIFO_TRANSACTION) {
i2c->rxctrl1 = 0;
} else {
i2c->rxctrl1 = (req->rx_len - read); // 0 for 256, otherwise number of bytes to read
}
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE;
i2c->fifo = (req->addr << 1) | 0x1; // Load slave address with read bit.
}
*/
}
if (req->restart) {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_RESTART;
} else {
i2c->mstctrl |= MXC_F_I2C_REVA_MSTCTRL_STOP;
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_STOP)) {}
// Wait for Transaction to finish
}
while (!(i2c->intfl0 & MXC_F_I2C_REVA_INTFL0_DONE)) {}
// Wait for Transaction to finish
i2c->intfl0 = MXC_F_I2C_REVA_INTFL0_DONE | MXC_F_I2C_REVA_INTFL0_STOP;
if (i2c->intfl0 & MXC_I2C_REVA_ERROR) {
return E_COMM_ERR;
}
return E_NO_ERROR;
}
int MXC_I2C_RevA_MasterTransactionAsync(mxc_i2c_reva_req_t *req)
{
int i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)(req->i2c));
mxc_i2c_reva_regs_t *i2c = req->i2c;