[CHERI-RISCV] Swap CheriStoreCond_r operand order to match AMO_rr

CTSRD-CHERI · Nov 25, 2020 · 8053c29 · 8053c29
1 parent b1f71b8
commit 8053c29
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Showing 2 changed files with 5 additions and 9 deletions.
diff --git a/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp b/llvm/lib/Target/RISCV/RISCVExpandAtomicPseudoInsts.cpp
@@ -968,11 +968,9 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchg(
       BuildMI(LoopTailMBB, DL, TII->get(RISCV::ADDI), ScratchReg)
           .addReg(NewValReg)
           .addImm(0);
-      // Note: SC_*_CAP has the address register as the second argument not the
-      // first even though it is called rs1 in tablegen.
       BuildMI(LoopTailMBB, DL, SCInst, ScratchReg)
-          .addReg(ScratchReg)
-          .addReg(AddrReg);
+          .addReg(AddrReg)
+          .addReg(ScratchReg);
     } else {
       BuildMI(LoopTailMBB, DL, SCInst, ScratchReg)
           .addReg(AddrReg)
@@ -1094,11 +1092,9 @@ bool RISCVExpandAtomicPseudo::expandAtomicCmpXchgCap(
     //   bnez scratch, loophead
     BuildMI(LoopTailMBB, DL, TII->get(RISCV::CMove), ScratchReg)
         .addReg(NewValReg);
-    // Note: SC_C_CAP has the address register as the second argument not the
-    // first even though it is called rs1 in tablegen.
     BuildMI(LoopTailMBB, DL, SCInst, ScratchReg)
-        .addReg(ScratchReg)
-        .addReg(AddrReg);
+        .addReg(AddrReg)
+        .addReg(ScratchReg);
     // In the explicit case the output register of SC_C_CAP/DDC is a capability
     // register so we have to extract the GPR register.
     SCResultReg = TRI->getSubReg(ScratchReg, RISCV::sub_cap_addr);

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -120,7 +120,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $rs2" in
 class CheriStoreCond_r<bits<5> op, string opcodestr, RegisterClass rs2Class,
                        RegisterOperand rs1Operand>
     : RVInstCheriTwoSrc<0x7c, op, 0, OPC_CHERI, (outs rs2Class:$rd),
-                        (ins rs2Class:$rs2, rs1Operand:$rs1),
+                        (ins rs1Operand:$rs1, rs2Class:$rs2),
                         opcodestr, "$rs2, $rs1">;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in