Merge pull request #25 from Energy-MAC/jd/0-2_bug_fixes

add LITS predicate to ports

src/structs/generator_components/avr.jl

@@ -2,7 +2,7 @@ abstract type AVR <: GeneratorComponent end
 
 @def avr_ports begin
       state_input = Vector{Symbol}()
-      inner_input = [V_pss_var, VI_gen_var, VR_gen_var]
+      inner_input = [LITS.V_pss_var, LITS.VI_gen_var, LITS.VR_gen_var]
 end
 
 """

src/structs/generator_components/machine.jl

@@ -2,7 +2,7 @@ abstract type Machine <: GeneratorComponent end
 
 @def machine_ports begin
     state_input = [:δ, :ω, :Vf]
-    inner_input = [VI_gen_var, VR_gen_var]
+    inner_input = [LITS.VI_gen_var, LITS.VR_gen_var]
 end
 
 

src/structs/generator_components/pss.jl

@@ -2,7 +2,7 @@ abstract type PSS <: GeneratorComponent end
 
 @def pss_ports begin
       state_input = [:ω]
-      inner_input = [τe_var, VR_gen_var]
+      inner_input = [LITS.τe_var, LITS.VR_gen_var]
   end
 
 

src/structs/generator_components/shaft.jl

@@ -2,7 +2,7 @@ abstract type Shaft <: GeneratorComponent end
 
 @def shaft_ports begin
     state_input = Vector{Int64}()
-    inner_input = [τe_var, τm_var]
+    inner_input = [LITS.τe_var, LITS.τm_var]
 end
 
 

src/structs/inverter_components/converter.jl

@@ -7,7 +7,7 @@ abstract type Converter <: InverterComponent end
 
 @def converter_ports begin
     state_input = Vector{Symbol}()
-    inner_input = [md_var, mq_var, Vdc_var, Vdcnv_var,Vqcnv_var]
+    inner_input = [LITS.md_var, LITS.mq_var, LITS.Vdc_var, LITS.Vdcnv_var, LITS.Vqcnv_var]
 end
 
 """

src/structs/inverter_components/filter.jl

@@ -3,7 +3,7 @@ abstract type Filter <: InverterComponent end
 @def filter_ports begin
     #TODO: If converter has dynamics, need to connect state_input
     state_input = [:δθ_vsm] #[:Vd_c, :Vq_c] #, :Id_c, :Iq_c]
-    inner_input = [VR_inv_var,VI_inv_var,Vdcnv_var,Vqcnv_var,δdqRI_var,Vdo_var,Vqo_var]
+    inner_input = [LITS.VR_inv_var, LITS.VI_inv_var, LITS.Vdcnv_var, LITS.Vqcnv_var, LITS.δdqRI_var, LITS.Vdo_var, LITS.Vqo_var]
 end
 
 """

src/structs/inverter_components/frequency_estimator.jl

@@ -3,7 +3,7 @@ abstract type FrequencyEstimator <: InverterComponent end
 @def freq_estimation_ports begin
     state_input = [:vd_cap,:vq_cap, :δθ_vsm]
     #TODO: Move PLL to PCC, i.e. move v_cap (D'Arco v_o), to inner inputs
-    inner_input = [Vdo_var,Vqo_var,δdqRI_var,ω_freq_estimator_var]
+    inner_input = [LITS.Vdo_var, LITS.Vqo_var, LITS.δdqRI_var, LITS.ω_freq_estimator_var]
 end
 
 """

src/structs/inverter_components/outer_control.jl

@@ -5,7 +5,7 @@ abstract type ReativePowerControl end
 
 @def outercontrol_ports begin
     state_input = [:vpll_d, :vpll_q, :ε_pll, :vd_cap, :vq_cap, :id_o, :iq_o]
-    inner_input = [Vdo_var, Vdo_var, ω_freq_estimator_var]
+    inner_input = [LITS.Vdo_var, LITS.Vdo_var, LITS.ω_freq_estimator_var]
 end
 
 """

src/structs/inverter_components/voltage_source_control.jl

@@ -2,7 +2,7 @@ abstract type VSControl <: InverterComponent end
 
 @def vscontrol_ports begin
     state_input = [:id_o, :iq_o, :id_c, :iq_c, :vd_cap, :vq_cap]
-    inner_input = [Vdo_var, Vqo_var, v_control_var, ω_control_var]
+    inner_input = [LITS.Vdo_var, LITS.Vqo_var, LITS.v_control_var, LITS.ω_control_var]
 end
 
 """