Merge branch 'main' of https://github.com/FPGAwars/iceWires

FPGAwars · Nov 4, 2023 · 5e23b06 · 5e23b06
2 parents 49c79f9 + 7453474
commit 5e23b06
Show file tree

Hide file tree

Showing 2 changed files with 70 additions and 64 deletions.
diff --git a/README.md b/README.md
@@ -1270,54 +1270,57 @@ For installing and using this colection in Icestudio follow these steps:
         * **08-bits**
           * **Alhambra-II**
             * 01-Manual-testing
-      * **16-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **17-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **18-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **19-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **20-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **21-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **22-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **23-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **24-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **25-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **26-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **27-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **28-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **29-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **30-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
-      * **31-bits**
-        * **Alhambra-II**
-          * 01-Manual-testing
+      * **09-16-bits**
+        * **16-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+      * **17-24-bits**
+        * **17-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **18-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **19-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **20-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **21-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **22-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **23-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **24-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+      * **25-31-bits**
+        * **25-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **26-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **27-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **28-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **29-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **30-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
+        * **31-bits**
+          * **Alhambra-II**
+            * 01-Manual-testing
   * **Wires**
     * **Bus-2**
       * **Alhambra-II**

diff --git a/locale/translation.js b/locale/translation.js
@@ -2105,22 +2105,9 @@ gettext('01-Manual-testing');
 gettext('Copy-15: Copy the input wire twice and generate a 15 bits Bus output (Verilog implementation)');
 gettext('## 15-Uint32 Manual testing');
 gettext('02-08-bits');
-gettext('16-bits');
-gettext('17-bits');
-gettext('18-bits');
-gettext('19-bits');
-gettext('20-bits');
-gettext('21-bits');
-gettext('22-bits');
-gettext('23-bits');
-gettext('24-bits');
-gettext('25-bits');
-gettext('26-bits');
-gettext('27-bits');
-gettext('28-bits');
-gettext('29-bits');
-gettext('30-bits');
-gettext('31-bits');
+gettext('09-16-bits');
+gettext('17-24-bits');
+gettext('25-31-bits');
 gettext('02-bits');
 gettext('08-bits');
 gettext('Alhambra-II');
@@ -2131,10 +2118,19 @@ gettext('## Uint32-2bit Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('## 08-Uint32 Manual testing');
+gettext('16-bits');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('UINT32-16bit-verilog:  Extend a 16-bit unsigned integer to 32-bits. Verilog implementation ');
 gettext('## Uint32-16bit Manual testing');
+gettext('17-bits');
+gettext('18-bits');
+gettext('19-bits');
+gettext('20-bits');
+gettext('21-bits');
+gettext('22-bits');
+gettext('23-bits');
+gettext('24-bits');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('UINT32-17bit-verilog:  Extend a 17-bit unsigned integer to 32-bits. Verilog implementation ');
@@ -2167,6 +2163,13 @@ gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('UINT32-24bit-verilog:  Extend a 24-bit unsigned integer to 32-bits. Verilog implementation ');
 gettext('## Uint32-24bit Manual testing');
+gettext('25-bits');
+gettext('26-bits');
+gettext('27-bits');
+gettext('28-bits');
+gettext('29-bits');
+gettext('30-bits');
+gettext('31-bits');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
 gettext('UINT32-25bit-verilog:  Extend a 25-bit unsigned integer to 32-bits. Verilog implementation ');