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Releases: FilMarini/FPGA_CDR_core

v1.1.1

23 Aug 18:17
@FilMarini FilMarini
v1.1.1
74ec39e
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v1.1

23 Oct 08:52
@FilMarini FilMarini
v1.1
12c4d73
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v1.1

now system clk is settable. solved bug on out cdr clk frequency.

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v1.0

22 Oct 12:02
@FilMarini FilMarini
v1.0
447e978
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v1.0

Clock recovery up to 250 Mbps

Assets 3
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