Upload mtb-pdl-cat1 3.6.0.26528 [1771]

Infineon · Sep 5, 2023 · 5322fee · 5322fee
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diff --git a/README.md b/README.md
@@ -47,4 +47,4 @@ See the [PDL API Reference Manual Getting Started section](https://infineon.gith
 New versions of PDL from 2.0 onwards are now be available in [mtb-pdl-cat1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html) repo and [psoc6pdl](https://infineon.github.io/psoc6pdl/pdl_api_reference_manual/html/index.html) repo will no longer be updated in future.
 
 ---
-© Cypress Semiconductor Corporation (an Infineon company), 2022.
+© Cypress Semiconductor Corporation (an Infineon company), 2023.
diff --git a/RELEASE.md b/RELEASE.md
@@ -1,4 +1,4 @@
-# MTB CAT1 Peripheral Driver Library v3.4.0
+# MTB CAT1 Peripheral Driver Library v3.6.0
 
 Please refer to the [README.md](./README.md) and the
 [PDL API Reference Manual](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html)
@@ -8,44 +8,29 @@ Some restrictions apply to the PSoC 64 devices configuration. Please refer to [P
 
 ## Implementation Details
 
-* Cryptolite Support for ECDSA verify for HASHZERO message added.
-* CAT1C:Enabled wait-states API.
-* Glitch filter support added for TCPWM version 3 and above.
-* CAT1A: Added new 80-m-csp package mpns in PSoC 6-256K family. MPNs starting with CY8C6144FMI, CY8C6244FMI.
+* CAT1B: CYW20829 Enhancements
+* CAT1B: CYW20829 DSRAM support for ARM Compiler
+* CAT1B Defect Fix: For API Cy_WDT_SetIgnoreBits, valid input range is changed to 0-21 for CAT1B devices, this will change the API's behaviour, follow the API documentation and use this API accordingly.
 
 ## Build Changes
 
 ## Personalities Changes
-* Added Personalities : smartio-4.0.cypersonality
-* Updated Personalities : bakclk-3.0.cypersonality, timerclk-3.0.cypersonality, tickclk-3.0.cypersonality, sysclock-3.0.cypersonality, power_v3-1.0.cypersonality, power_v2-1.0.cypersonality, pin-3.0.cypersonality, pclk_v2-1.0.cypersonality,
-  mfclk-3.0.cypersonality, hfclk-3.0.cypersonality, hfclk_v2-1.0.cypersonality, eco-3.0.cypersonality, uart-3.0.cypersonality, tdm-1.1.cypersonality, smif_v2-1.0.cypersonality, smartio-3.0.cypersonality, sd_host-1.0.cypersonality, pwm_v2-1.0.cypersonality, pdm_pcm_v2-3.0.cypersonality, mcwdt-3.0.cypersonality, i2c-4.0.cypersonality, canfd-3.0.cypersonality
+* Updated Personalities : pilo-3.0.cypersonality, power_v2-1.0.cypersonality
 
 ## Added Drivers
 
+
 ## Updated Drivers
+* [SYSCLK 3.80](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysclk.html)
+* [CRYPTOLITE 2.40](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__cryptolite.html)
+* [SYSPM 5.95](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syspm.html)
+* [WDT 1.70](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__wdt.html)
 
-* [CANFD 1.40](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__canfd.html)
-* [CRYPTO 2.90](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__crypto.html)
-* [CRYPTOLITE 2.30](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__cryptolite.html)
-* [DMA 2.70](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__dma.html)
-* [GPIO 1.90](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__gpio.html)
-* [IPC 1.91](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ipc.html)
-* [LPCOMP 1.60](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__lpcomp.html)
-* [SMIF 2.60](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__smif.html)
-* [SYSCLK 3.70](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysclk.html)
-* [SYSFAULT 1.20](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysfault.html)
-* [SYSLIB 3.40](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syslib.html)
-* [SYSPM 5.94](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syspm.html)
-* [TCPWM 1.60](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__tcpwm.html)
 
 ### Drivers with patch version updates
+* [EFUSE 2.30.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__efuse.html)
+
 
-* [ETHIF 1.10.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ephy.html)
-* [PRA 2.40.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__pra.html)
-* [SMARTIO 1.0.3](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__smartio.html)
-* [SYSINT 1.90.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysint.html)
-* [SYSTICK 1.70.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__arm__system__timer.html)
-* [TRIGMUX 1.60.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__trigmux.html)
 ### Obsoleted part numbers
 
 The ModusToolbox Device Configurator can not create the designs targeting the obsolete PSoC 6 part numbers.

diff --git a/device-info/personalities/platform/pilo-3.0.cypersonality b/device-info/personalities/platform/pilo-3.0.cypersonality
@@ -49,6 +49,7 @@
   <ConfigFirmware>
     <ConfigInclude value="cy_sysclk.h" include="true" />
     <ConfigDefine name="CY_CFG_SYSCLK_PILO_ENABLED" value="1" public="false" include="true" />
-    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_PiloInit()" body="    Cy_SysClk_PiloEnable();" public="false" include="true"  />
+    <ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_PiloInit()" body="    Cy_SysClk_PiloEnable();&#xA;&#xA;    if(!Cy_SysClk_PiloOkay())&#xA;    {&#xA;        Cy_SysPm_TriggerXRes();&#xA;    }" public="false" include="`${(&quot;mxs40ssrss&quot; eq getIpBlockName())}`" />
+	<ConfigFunction signature="__STATIC_INLINE void Cy_SysClk_PiloInit()" body="    Cy_SysClk_PiloEnable();" public="false" include="`${(&quot;mxs40srss&quot; eq getIpBlockName()) || (&quot;mxs22srss&quot; eq getIpBlockName())}`"/>
   </ConfigFirmware>
 </Personality>
diff --git a/device-info/personalities/platform/power_v2-1.0.cypersonality b/device-info/personalities/platform/power_v2-1.0.cypersonality
@@ -95,33 +95,33 @@
                                                                                    actPwrMode eq POWER_PROFILE_1   ? &quot;1.16V High Power&quot;   :
                                                                                    actPwrMode eq POWER_PROFILE_2A  ? &quot;1.16V High Power&quot;   :
                                                                                    actPwrMode eq POWER_PROFILE_2B  ? &quot;1.1V Low Power&quot;   :
-                                                                                   actPwrMode eq POWER_PROFILE_3   ? &quot;0.9V Low Power&quot;   :
+                                                                                   actPwrMode eq POWER_PROFILE_3   ? &quot;1.0V Low Power&quot;   :
 																				   &quot;1.16V High Power&quot;}`" visible="false" editable="false" desc="Core Buck Voltage and Mode." />
 
     <ParamString id="coreBuckVoltMacro" name="Core Buck Voltage Macro" group="Internal" default="`${coreBuckParam eq &quot;1.16V High Power&quot;    ? &quot;CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V&quot;   :
                                                                                    coreBuckParam eq &quot;1.1V Low Power&quot;   ? &quot;CY_SYSPM_CORE_BUCK_VOLTAGE_1_10V&quot;   :
-                                                                                   coreBuckParam eq &quot;0.9V Low Power&quot;   ? &quot;CY_SYSPM_CORE_BUCK_VOLTAGE_0_90V&quot;   :
+                                                                                   coreBuckParam eq &quot;1.0V Low Power&quot;   ? &quot;CY_SYSPM_CORE_BUCK_VOLTAGE_1_00V&quot;   :
 																				   &quot;CY_SYSPM_CORE_BUCK_VOLTAGE_1_16V&quot;}`" visible="false" editable="false" desc="Core Buck Voltage Macro." />
 
     <ParamString id="coreBuckModeMacro" name="Core Buck Mode Macro" group="Internal" default="`${coreBuckParam eq &quot;1.16V High Power&quot;    ? &quot;CY_SYSPM_CORE_BUCK_MODE_HP&quot;   :
                                                                                    coreBuckParam eq &quot;1.1V Low Power&quot;   ? &quot;CY_SYSPM_CORE_BUCK_MODE_LP&quot;   :
-                                                                                   coreBuckParam eq &quot;0.9V Low Power&quot;   ? &quot;CY_SYSPM_CORE_BUCK_MODE_LP&quot;   :
+                                                                                   coreBuckParam eq &quot;1.0V Low Power&quot;   ? &quot;CY_SYSPM_CORE_BUCK_MODE_LP&quot;   :
 																				   &quot;CY_SYSPM_CORE_BUCK_MODE_HP&quot;}`" visible="false" editable="false" desc="Core Buck Mode Macro." />
 
     <ParamString id="coreBuckVoltagemode" name="Core Buck Voltage and Mode" group="Operating Conditions" default="`${coreBuckParam}`" visible="true" editable="false" desc="Core Buck Voltage and Mode.." />
 
     <!-- SDR0 Regulator -->
     <ParamString id="sdr0Param" name="SDR0 Parameters" group="Internal" default="`${actPwrMode eq POWER_PROFILE_0    ? &quot;1.1V Regulated&quot;   :
-                                                                                   actPwrMode eq POWER_PROFILE_1   ? &quot;0.9V Regulated&quot;   :
+                                                                                   actPwrMode eq POWER_PROFILE_1   ? &quot;1.0V Regulated&quot;   :
                                                                                    actPwrMode eq POWER_PROFILE_2A  ? &quot;1.1V Regulated&quot;   :
                                                                                    actPwrMode eq POWER_PROFILE_2B  ? &quot;1.1V Bypassed&quot;   :
-                                                                                   actPwrMode eq POWER_PROFILE_3   ? &quot;0.9V Bypassed&quot;   :
+                                                                                   actPwrMode eq POWER_PROFILE_3   ? &quot;1.0V Bypassed&quot;   :
 																				   &quot;1.1V Regulated&quot;}`" visible="false" editable="false" desc="SDR0 Regulator Voltage and Mode." />
 
     <ParamString id="sdr0VoltMacro" name="SDR0 Voltage Macro" group="Internal" default="`${sdr0Param eq &quot;1.1V Regulated&quot;    ? &quot;CY_SYSPM_SDR_VOLTAGE_1_100V&quot;   :
                                                                                    sdr0Param eq &quot;1.1V Bypassed&quot;   ? &quot;CY_SYSPM_SDR_VOLTAGE_1_100V&quot;   :
-                                                                                   sdr0Param eq &quot;0.9V Regulated&quot;   ? &quot;CY_SYSPM_SDR_VOLTAGE_0_900V&quot;   :
-                                                                                   sdr0Param eq &quot;0.9V Bypassed&quot;   ? &quot;CY_SYSPM_SDR_VOLTAGE_0_900V&quot;   :
+                                                                                   sdr0Param eq &quot;1.0V Regulated&quot;   ? &quot;CY_SYSPM_SDR_VOLTAGE_1_000V&quot;   :
+                                                                                   sdr0Param eq &quot;1.0V Bypassed&quot;   ? &quot;CY_SYSPM_SDR_VOLTAGE_1_000V&quot;   :
 																				   &quot;CY_SYSPM_SDR_VOLTAGE_1_100V&quot;}`" visible="false" editable="false" desc="SDR0 Voltage Macro." />
 
     <ParamString id="sdr0Voltagemode" name="SDR0 Regulator Voltage and Mode" group="Operating Conditions" default="`${sdr0Param}`" visible="true" editable="false" desc="SDR0 Regulator Voltage and Mode.." />

diff --git a/docs/pdl_api_reference_manual/html/group__group__cryptolite.html b/docs/pdl_api_reference_manual/html/group__group__cryptolite.html
@@ -151,6 +151,8 @@ <h1><a class="anchor" id="group_cryptolite_changelog"></a>
 <tr>
 <th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
 <tr>
+<td>2.40 </td><td>Updated value of CY_CRYPTOLITE_DEF_TRNG_GARO macro. </td><td>Usability enhancement.  </td></tr>
+<tr>
 <td>2.30 </td><td>Updated APIs <a class="el" href="group__group__cryptolite__lld__asymmetric__functions.html#ga956dd70a876047166b391430eb7d1c58">Cy_Cryptolite_ECC_VerifyHash</a> and <a class="el" href="group__group__cryptolite__lld__aes__functions.html#ga96a14d14eef1ba7bf51a97ff809cce84">Cy_Cryptolite_Aes_Ctr</a>. </td><td>Support for ECDSA verify for HASHZERO message added and MISRA 2012 violation fix  </td></tr>
 <tr>
 <td>2.20 </td><td><ul>

diff --git a/docs/pdl_api_reference_manual/html/group__group__cryptolite__macros.html b/docs/pdl_api_reference_manual/html/group__group__cryptolite__macros.html
@@ -95,7 +95,7 @@
 <tr class="memdesc:ga7eac54119684a61960a41fddb15f6dd8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driver major version. <br /></td></tr>
 <tr class="separator:ga7eac54119684a61960a41fddb15f6dd8"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:ga4e726b7e6e5ddfbf255642c1e9b1e0ee"><td class="memItemLeft" align="right" valign="top"><a id="ga4e726b7e6e5ddfbf255642c1e9b1e0ee"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__cryptolite__macros.html#ga4e726b7e6e5ddfbf255642c1e9b1e0ee">CY_CRYPTOLITE_DRV_VERSION_MINOR</a>&#160;&#160;&#160;30</td></tr>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__cryptolite__macros.html#ga4e726b7e6e5ddfbf255642c1e9b1e0ee">CY_CRYPTOLITE_DRV_VERSION_MINOR</a>&#160;&#160;&#160;40</td></tr>
 <tr class="memdesc:ga4e726b7e6e5ddfbf255642c1e9b1e0ee"><td class="mdescLeft">&#160;</td><td class="mdescRight">Driver minor version. <br /></td></tr>
 <tr class="separator:ga4e726b7e6e5ddfbf255642c1e9b1e0ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:gaa20ad3f832c26fc7a5af6ba2affd98cf"><td class="memItemLeft" align="right" valign="top"><a id="gaa20ad3f832c26fc7a5af6ba2affd98cf"></a>

diff --git a/docs/pdl_api_reference_manual/html/group__group__efuse.html b/docs/pdl_api_reference_manual/html/group__group__efuse.html
@@ -91,7 +91,8 @@
 <p>The functions and other declarations used in this driver are in cy_efuse.h. You can include cy_pdl.h to get access to all functions and declarations in the PDL.</p>
 <p>The eFuse driver enables reading the state of any bit.</p><ul>
 <li>CAT1A devices does not support writing to eFuse memory. Writing an eFuse bit is typically done by a production programmer. Fuses are programmed via the PSoC Programmer tool that parses the hex file and extracts the necessary information; the fuse data must be located at the dedicated section in the hex file. For more details see <a href="http://www.cypress.com/documentation/programming-specifications/psoc-6-programming-specifications">PSoC 6 Programming Specifications</a></li>
-<li>CAT1B devices support writing to eFuse memory.</li>
+<li>CAT1B devices support writing to eFuse memory. <dl class="section note"><dt>Note</dt><dd>Blowing eFuses is normally performed during device provisioning; eFuses are not intended to be programmed by the customer</dd></dl>
+</li>
 <li>CAT1C devices does not support writing to eFuse memory.</li>
 </ul>
 <p>One eFuse macro consists of 256 bits (32 * 8). Consult the device-specific datasheet to determine how many macros a device has. These are implemented as a regular Advanced High-performance Bus (AHB) peripheral with the following characteristics:</p><ul>
@@ -110,6 +111,8 @@ <h1><a class="anchor" id="group_efuse_changelog"></a>
 <tr>
 <th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
 <tr>
+<td>2.30.1 </td><td>Minor documentation updates. </td><td>Added a note for CAT1B family of devices.  </td></tr>
+<tr>
 <td>2.30 </td><td>Updated Cy_EFUSE_WriteBit API. </td><td>Fix minor compilation warning.  </td></tr>
 <tr>
 <td>2.20 </td><td>Updated driver to support the CAT1C family of devices. </td><td>Added new family of devices.  </td></tr>

diff --git a/docs/pdl_api_reference_manual/html/group__group__sysclk.html b/docs/pdl_api_reference_manual/html/group__group__sysclk.html
@@ -116,6 +116,8 @@ <h1><a class="anchor" id="group_sysclk_changelog"></a>
 <tr>
 <th>Version</th><th>Changes</th><th>Reason for Change </th></tr>
 <tr>
+<td>3.80 </td><td>Added <a class="el" href="group__group__sysclk__pilo__funcs.html#ga3a27da8dadb92695750b12f41c91be06">Cy_SysClk_PiloOkay</a> new API and few macros. Updated <a class="el" href="group__group__sysclk__pilo__funcs.html#ga92e44b1390d7cabf2c597c45a5fdd309">Cy_SysClk_PiloEnable</a>. </td><td>Usability enhancement.  </td></tr>
+<tr>
 <td>3.70 </td><td>Added new APIs <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga67797f8c99ea82f42ee9c851c0c320cf">Cy_SysClk_ClkPwrSetDivider</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga1e5eb62dc8e5d6e2868ad6e9ab4e10da">Cy_SysClk_ClkPwrGetDivider</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga9c2e470db36c5e854811d539035d0ad0">Cy_SysClk_ClkPwrGetFrequency</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga56d3459b796e0c51e85da74ba368eab7">Cy_SysClk_ClkPwrSetSource</a>, <a class="el" href="group__group__sysclk__clk__pwr__funcs.html#ga35a0804ce9e5014d36a0fdfe6edd0db2">Cy_SysClk_ClkPwrGetSource</a>. <br />
  and enum <a class="el" href="group__group__sysclk__clk__pwr__enums.html#gaea34f48dfb3fbef4d7ff33862cbd2f0a">cy_en_clkpwr_in_sources_t</a>  </td><td>Support Added for future devices of the CAT1B.  </td></tr>
 <tr>