Upload mtb-pdl-cat1 3.3.0.21979 [982]

EULA.txt

@@ -1,4 +1,4 @@
-CYPRESS END USER LICENSE AGREEMENT
+CYPRESS (AN INFINEON COMPANY) END USER LICENSE AGREEMENT
 
 PLEASE READ THIS END USER LICENSE AGREEMENT ("Agreement") CAREFULLY BEFORE
 DOWNLOADING, INSTALLING, COPYING, OR USING THIS SOFTWARE AND ACCOMPANYING
@@ -22,9 +22,8 @@ PURCHASER.
 
     "Development Tools" means software that is intended to be installed on a
       personal computer and used to create programming code for Firmware,
-      Drivers, or Host Applications.  Examples of Development Tools are
-      Cypress's PSoC Creator software, Cypress's WICED SDKs, and Cypress's
-      ModusToolbox software.
+      Drivers, or Host Applications.  Examples of Development Tools are Cypress's
+      PSoC Creator software, Cypress's AIROC SDKs, and Cypress's ModusToolbox software.
 
     "Firmware" means software that executes on a Cypress hardware product.
 
@@ -87,11 +86,12 @@ Software is subject to the applicable license agreement and not this
 Agreement.  If you are entitled to receive the source code from Cypress for
 any Third Party Software included with the Software, either the source code
 will  be included with the Software or you may obtain the source code at no
-charge from <http://www.cypress.com/go/opensource>.  The applicable license
-terms will accompany each source code package.  To review the license terms
-applicable to any Third Party Software for which Cypress is not required to
-provide you with source code, please see the Software's installation directory
-on your computer.
+charge from
+<https://www.infineon.com/cms/en/design-support/software/free-and-open-source-software-foss/>.
+The applicable license terms will accompany each source code package.
+To review the license terms applicable to any Third Party Software for which
+Cypress is not required to provide you with source code, please see the
+Software's installation directory on your computer.
 
 4. Proprietary Rights; Ownership.  The Software, including all intellectual
 property rights therein, is and will remain the sole and exclusive property of
@@ -182,10 +182,10 @@ Software shall be only those set forth in this Agreement.
 registration on Cypress IoT Community Forum or other Cypress websites,
 including contact information or other personal information, may be collected
 and used by Cypress consistent with its Data Privacy Policy
-(www.cypress.com/privacy-policy), as updated or revised from time to time, and
-may be provided to its third party sales representatives, distributors and
-other entities conducting sales activities for Cypress for sales-related and
-other business purposes.
+(https://www.infineon.com/cms/en/about-infineon/privacy-policy/), as updated
+or revised from time to time, and may be provided to its third party sales
+representatives, distributors and other entities conducting sales activities
+for Cypress for sales-related and other business purposes.
 
 12. General.  This Agreement will bind and inure to the benefit of each
 party's successors and assigns, provided that you may not assign or transfer

README.md

@@ -2,7 +2,7 @@
 
 ### Overview
 The Cypress PDL simplifies software development for CAT1 family of devices.
-The PDL integrates device header files, startup code, and 
+The PDL integrates device header files, and 
 peripheral drivers into a single package. The drivers abstract the hardware functions into a set of 
 easy-to-use APIs. These are fully documented in the [PDL API Reference Manual](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html). 
 

RELEASE.md

@@ -1,4 +1,4 @@
-# MTB CAT1 Peripheral Driver Library v3.2.0
+# MTB CAT1 Peripheral Driver Library v3.3.0
 
 Please refer to the [README.md](./README.md) and the
 [PDL API Reference Manual](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/index.html)
@@ -8,25 +8,46 @@ Some restrictions apply to the PSoC 64 devices configuration. Please refer to [P
 
 ## Implementation Details
 
-* TRNG enchacements to support health monitor check.
+* Crypto AES GCM support for CAT1A
+* Inrush mode selection support in BT-IPC for CAT1B
+* DEEPSLEEP-RAM support addition for CAT1B
 * Bug fixes
+* MISRA 2012 fixes done for few drivers
 
 ## Build Changes
 
 ## Personalities Changes
 
-* Updated eco-3.0.cypersonality, extclk-3.0.cypersonality, wco-3.0.cypersonality, pin-3.0.cypersonality, and sar-6.0.cypersonality
+* Updated Personalities : counter_v2-1.0.cypersonality, counter-1.0.cypersonality, csd-3.0.cypersonality, emusb-1.0.cypersonality,
+  i2c-4.0.cypersonality, mcwdt_v2-1.0.cypersonality, pwm_v2-1.0.cypersonality, quaddec_v2-1.0.cypersonality, sar2-1.0.cypersonality, sar-6.0.cypersonality, shiftreg_v2-1.0.cypersonality, smif_v2-1.0.cypersonality, althf-1.1.cypersonality, bakclk-3.0.cypersonality, eco_prescaler-1.0.cypersonality, fll-4.0.cypersonality, hfclk_v2-1.0.cypersonality, iho-1.0.cypersonality, lfclk-3.0.cypersonality, mfclk-3.0.cypersonality, mfo-3.0.cypersonality, periclk-2.0.cypersonality, pin-3.0.cypersonality, power_v2-1.0.cypersonality, sysclock-3.0.cypersonality 
 
 ## Added Drivers
 
 ## Updated Drivers
 
-* [SYSPM 5.91](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syspm.html)
-* [CRYPTO 2.70](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__crypto.html)
+* [ADCMIC 1.10](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__adcmic.html)
+* [CRYPTO 2.80](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__crypto.html)
+* [CRYPTOLITE 2.10](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__cryptolite.html)
+* [EPHY 1.10](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ephy.html)
+* [EFUSE 2.30](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__efuse.html)
+* [EMAC 1.10](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ethif.html)
+* [GPIO 1.80](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__gpio.html)
+* [IPC 1.90](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__ipc.html)
+* [SCB 3.10](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__scb.html)
+* [SMIF 2.50](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__smif.html)
+* [SYSTICK 1.70](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__arm__system__timer.html)
+* [SYSCLK 3.60](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysclk.html)
+* [SYSFAULT 1.10](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysfault.html)
+* [SYSINT 1.90](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__sysint.html)
+* [SYSLIB 3.30](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syslib.html)
+* [SYSPM 5.92](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__syspm.html)
+* [TCPWM 1.50](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__tcpwm.html)
+* [TRIGMUX 1.60](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__trigmux.html)
+* [USBFS 2.20.3](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__usbfs__dev__drv.html)
+* [WDT 1.60](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__wdt.html)
 
-### Drivers with patch version updates
 
-* [SegLCD 1.10.1](https://infineon.github.io/mtb-pdl-cat1/pdl_api_reference_manual/html/group__group__seglcd.html)
+### Drivers with patch version updates
 
 ### Obsoleted part numbers
 
@@ -85,5 +106,6 @@ This version of PDL was validated for compatibility with the following Software
 * [XMC7000](https://www.infineon.com/cms/en/product/microcontroller/32-bit-industrial-microcontroller-based-on-arm-cortex-m/32-bit-xmc7000-industrial-microcontroller-arm-cortex-m7/)
 * [Infineon](http://www.infineon.com)
 
+
 ---
-© Cypress Semiconductor Corporation (an Infineon company), 2022.
+© Cypress Semiconductor Corporation (an Infineon company), 2023.

device-info/device-db-supplemental/Connectivity-BT-WIFI/.timestamp

@@ -1 +1 @@
-2022-12-12 23:53:13
+2023-03-20 00:20:01

device-info/device-db-supplemental/Connectivity-BT-WIFI/55500A0/studio_5.0/view.xml

@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="utf-8"?>
+<View xmlns="http://cypress.com/xsd/cystudioview_v1">
+  <PinResourceType value="ioss[0].port[%1$d].pin[%2$d]" />
+  <Profiles>
+    <Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="4" description="System configuration" resources="srss[\[\.].*" />
+    <Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="2" description="Pin configuration" resources="ioss[\[\.].*" />
+    <Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="1" description="Peripheral Hardware Block configuration" resources=".*" />
+    <!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify display order/code gen order for Analog/routing.-->
+    <Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" >
+      <Includes />
+    </Profile>
+  </Profiles>
+</View>

device-info/device-db-supplemental/Connectivity-BT-WIFI/studio_5.0/view.xml

@@ -2,14 +2,20 @@
 <View xmlns="http://cypress.com/xsd/cystudioview_v1">
   <Connectivity location="connectivity" />
   <Wounding location="chipresourcewoundings.xml" />
-  <!-- %1$d is for the port number which should always be 0 -->
+  <!-- %1$d is for the port number which should always be 0 so we can use it instead of a zero because using %2 without %1 will get the wrong result. -->
   <PinResourceType value="ioss[%1$d].pin[%2$d]" />
+  <!--There are no TriggerGroup type="MUX" in triggers.cydata so TrigMuxConnectTemplate is not used.-->
+  <TrigMuxConnectTemplate value="/* NOT USED */" />
+  <!--There are no TriggerGroup type="ONE_TO_ONE" in triggers.cydata so TrigMuxSelectTemplate is not used.-->
+  <TrigMuxSelectTemplate value="/* NOT USED */" />
   <Profiles>
     <Profile displayName="Connectivity" fileName="connectivity_wifi" evalPriority="1" displayPriority="4" description="Connectivity Wi-Fi configuration" resources="(wifi)(\[\d+\])?\..+" />
     <Profile displayName="Connectivity" fileName="connectivity_bt" evalPriority="1" displayPriority="4" description="Connectivity BT configuration" resources="(bt)(\[\d+\])?\..+" />
     <Profile displayName="Connectivity" fileName="connectivity_coex" evalPriority="1" displayPriority="4" description="Connectivity Coex configuration" resources="(coex)(\[\d+\])?\..+" />
     <Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="2" description="Pin configuration" resources=".*" />
     <!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify code gen order for routing.-->
-    <Profile purpose="ROUTING" displayName="" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" />
+    <Profile purpose="ROUTING" displayName="" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" >
+      <Includes />
+    </Profile>
   </Profiles>
 </View>

device-info/device-db-supplemental/MXS40/.timestamp

@@ -1 +1 @@
-2022-12-12 23:53:13
+2023-03-20 00:20:00

device-info/device-db-supplemental/MXS40/studio_5.0/view.xml

@@ -3,13 +3,21 @@
   <Connectivity location="connectivity" />
   <Wounding location="chipresourcewoundings.xml" />
   <PinResourceType value="ioss[0].port[%1$d].pin[%2$d]" />
+  <TrigMuxConnectTemplate value="Cy_TrigMux_Connect(${CyMarkIn}, ${CyMarkOut}, false, ${CyMarkType});" />
+  <TrigMuxSelectTemplate value="Cy_TrigMux_Select(${CyMarkOut}, false, ${CyMarkType});" />
   <Profiles>
     <Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="4" description="System configuration" resources="srss(\[\d+\])?\.(clock|power|eeprom)(\[\d+\])?.*|cpuss(\[\d+\])?\.dap(\[\d+\])?" />
     <Profile displayName="DMA" fileName="dmas" evalPriority="3" displayPriority="6" description="DMA configuration" resources="cpuss(\[\d+\])?\.(dw|dmac).*" />
     <Profile displayName="Peripheral-Clocks" fileName="clocks" evalPriority="2" displayPriority="5" description="Clock configuration" resources="peri(\[\d+\])?(\.group(\[\d+\])?)?(\.div_.*)?" />
     <Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="2" description="Pin configuration" resources="ioss[\[\.].*" />
     <Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="1" description="Peripheral Hardware Block configuration" resources=".*" />
     <!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify display order/code gen order for Analog/routing.-->
-    <Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" />
+    <Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" >
+      <Includes>
+        <Include value="cy_trigmux.h" public="false" />
+        <Include value="stdbool.h" public="false" />
+        <Include value="cy_device_headers.h" public="false" />
+      </Includes>
+    </Profile>
   </Profiles>
 </View>

device-info/device-db-supplemental/MXS40Sv2/.timestamp

@@ -1 +1 @@
-2022-12-12 23:53:13
+2023-03-20 00:20:00

device-info/device-db-supplemental/MXS40Sv2/studio_5.0/view.xml

@@ -3,13 +3,21 @@
   <Connectivity location="connectivity" />
   <Wounding location="chipresourcewoundings.xml" />
   <PinResourceType value="ioss[0].port[%1$d].pin[%2$d]" />
+  <TrigMuxConnectTemplate value="Cy_TrigMux_Connect(${CyMarkIn}, ${CyMarkOut}, false, ${CyMarkType});" />
+  <TrigMuxSelectTemplate value="Cy_TrigMux_Select(${CyMarkOut}, false, ${CyMarkType});" />
   <Profiles>
     <Profile displayName="System" diagramType="CLOCKS" fileName="system" evalPriority="1" displayPriority="4" description="System configuration" resources="srss(\[\d+\])?\.(clock|power)(\[\d+\])?.*|cpuss(\[\d+\])?\.dap(\[\d+\])?" />
     <Profile displayName="DMA" fileName="dmas" evalPriority="3" displayPriority="6" description="DMA configuration" resources="cpuss(\[\d+\])?\.(dw|dmac|mxdw|mxahbdmac).*" />
     <Profile displayName="Peripheral-Clocks" fileName="clocks" evalPriority="2" displayPriority="5" description="Clock configuration" resources="peri(\[\d+\])?\.group(\[\d+\])?(\.div_.*)?" />
     <Profile displayName="Pins" diagramType="PACKAGE" fileName="pins" evalPriority="6" displayPriority="2" description="Pin configuration" resources="ioss[\[\.].*" />
     <Profile displayName="Peripherals" fileName="peripherals" evalPriority="5" displayPriority="1" description="Peripheral Hardware Block configuration" resources=".*" />
     <!--This won't match any HW locations because it is after the catchall (.*). This is on purpose and needed to specify display order/code gen order for Analog/routing.-->
-    <Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" />
+    <Profile purpose="ROUTING" displayName="Analog-Routing" diagramType="ANALOG" fileName="routing" evalPriority="4" displayPriority="3" description="Establishes all necessary connections between hardware elements." resources="NONE" >
+      <Includes>
+        <Include value="cy_trigmux.h" public="false" />
+        <Include value="stdbool.h" public="false" />
+        <Include value="cy_device_headers.h" public="false" />
+      </Includes>
+    </Profile>
   </Profiles>
 </View>

device-info/device-db-supplemental/version.xml

@@ -1 +1 @@
-<version>4.0.2.2983</version>
+<version>4.1.0.3437</version>

device-info/personalities/peripheral/counter-1.0.cypersonality

@@ -255,7 +255,7 @@
     <ConfigInclude value="cy_sysclk.h" include="`${pclkOk}`" />
     <ConfigInclude value="cycfg_routing.h" include="true" />
     <ConfigInclude value="cyhal_hwmgr.h" include="true" guard="defined (CY_USING_HAL)" />
-    
+
     <ConfigDefine name="`${INST_NAME}`_HW" value="TCPWM`${tcpwmInst}`" public="true" include="true" />
     <ConfigDefine name="`${INST_NAME}`_NUM" value="`${cntInst}`UL" public="true" include="true" />
     <ConfigDefine name="`${INST_NAME}`_MASK" value="(1UL &lt;&lt; `${cntInst}`)" public="true" include="true" />
@@ -269,7 +269,7 @@
       <Member name="compareOrCapture" value="`${CompareOrCapture}`" />
       <Member name="compare0" value="`${Compare0}`" />
       <Member name="compare1" value="`${Compare1}`" />
-      <Member name="enableCompareSwap" value="`${EnableCompareSwap}`" />
+      <Member name="enableCompareSwap" value="`${pCCeqCompare ? EnableCompareSwap : pCCeqCompare}`" />
       <Member name="interruptSources" value="`${InterruptSource}`" />
       <Member name="captureInputMode" value="`${CaptureInput eq CY_TCPWM_INPUT_DISABLED ? defineInputDisabled : CaptureInput}`" />
       <Member name="captureInput" value="`${CaptureInput eq CY_TCPWM_INPUT_DISABLED ? &quot;CY_TCPWM_INPUT_0&quot; : (definePrefix . &quot;_CAPTURE_VALUE&quot;)}`" />