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Precompiling is the same (but slow ~100s, I do not understand why; I had this also in #853, then it reverse to normal timings without any changes from my part…).
On a simple silicon supercell of size 2×2×2 the cold and hot timings are similar:
master: 22s then 6.29s
branch: 24.2s then 6.57s
So if the change seems fine for you, I will test this on more robust test cases (ideas are welcome).